Intel PXA250 and PXA210 Applications Processors

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I2C 7.1.2 Digital-to-Analog Converter (DAC) Figure 7-1 shows the schematic for connecting the I 2 C interface to a Linear Technology micropower DAC. The DAC output is connected to the buck converter feedback path and is controlled by the I 2 C bus interface unit. The DAC can modify the voltage of the feedback path, which effects the processor core voltage. Figure 7-1. Linear Technology DAC with I 2 C Interface DC3P3V R165 1.00M U30 4 VCC LTC1663 SA_I2C_SDA 1 SDA VOUT 3 SA_I2C_SCL 5 SCL GND 2 LTEP LTC1663C35 A8752-01 The signals SA_I2C_SDA and SA_I2C_SCL correspond to the applications processor signals SDA and SCL, respectively. 7.1.3 Other Uses of I 2 C Figure 7-2 shows the I 2 C signals passing through an analog switch to a compact flash socket. Since the CF socket has all of the signals to support two CF cards, and this design only uses one CF card, the signals meant for a second card are being used for alternate functions. If you decide not to use a CF card, a different application using a CF card socket could be designed to utilize the I 2 C bus interface unit. If this alternate function is used, the I 2 C bus can be enabled to the CF socket by asserting the signal SA_I2C_ENAB shown in the diagram. If the user decides to use a CF Card, negate the SA_I2C_ENAB signal so the I 2 C bus traffic does not interfere with the CF card. Note: The CF card socket is disabled if a device is inserted in the expansion bus. 7-2 PXA250 and PXA210 Applications Processors Design Guide
. I2C Figure 7-2. Using an Analog Switch to Allow a Second CF Card DC3P3V U26 MAX4547 V* 2 SA_I2C_SCL 8 COM_1 7 IN_7 NC_1 1 CF_I2C_SCL SA_I2C_SDA SA_I2C_ENAB 4 3 COM_7 IN_2 NC_2 GND 5 6 CI_I2C_SDA AAAF A8750-01 7.1.4 Pull-Ups and Pull-Downs The I 2 C Bus Specification, available from Philips Corporation, states: The external pull-up devices connected to the bus lines must be adapted to accommodate the shorter maximum permissible rise time for the Fast-mode I 2 C-bus. For bus loads up to 200 pF, the pull-up device for each bus line can be a resistor; for bus loads between 200 pF and 400 pF, the pull-up device can be a current source (3 mA max.) or a switched resistor circuit. The design presented in this guide is not intended for loads larger than 200pF, so the pull-up device is a resistor as shown in Figure 7-3. Figure 7-3. I 2 C Pull-Ups and Pull-Downs DC3P3V SA_I2C_SCL SA_I2C_SDA R4 4.99K R5 4.99K A8751-01 PXA250 and PXA210 Applications Processors Design Guide 7-3
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Intel ® PXA250 and PXA210 Applicat
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Contents Contents 1 Introduction...
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Contents A.1 SA-1110 Hardware Migra
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Contents 2-7 SRAM / ROM / Flash / S
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Introduction 1 Table 1-1. Revision
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Introduction • System memory inte
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Introduction Table 1-3. Signal Pin
Page 15 and 16: Introduction Table 1-3. Signal Pin
Page 17 and 18: Introduction Table 1-3. Signal Pin
Page 19 and 20: Introduction Figure 1-2. PXA250 App
Page 21 and 22: Introduction Table 1-4. PXA250 Appl
Page 23 and 24: Introduction Figure 1-3. PXA210 App
Page 25 and 26: Introduction Table 1-5. PXA210 Appl
Page 27 and 28: System Memory Interface 2 This sect
Page 29 and 30: System Memory Interface Table 2-1.
Page 31 and 32: . System Memory Interface 2.4 SDRAM
Page 39 and 40: System Memory Interface Figure 2-5.
Page 41 and 42: System Memory Interface Figure 2-6.
Page 43 and 44: System Memory Interface 2.7 System
Page 45 and 46: LCD Display Controller 3 This chapt
Page 47 and 48: LCD Display Controller Figure 3-1.
Page 49 and 50: LCD Display Controller Figure 3-5.
Page 51 and 52: LCD Display Controller Note: This e
Page 53 and 54: LCD Display Controller However, typ
Page 55 and 56: USB Interface 4 4.1 Self Powered De
Page 57 and 58: MultiMediaCard (MMC) 5 The MultiMed
Page 59 and 60: MultiMediaCard (MMC) Figure 5-1. Ap
Page 61 and 62: MultiMediaCard (MMC) Warning: Conne
Page 63 and 64: AC97 6 The AC97 controller unit (AC
Page 65: I 2 C 7 The Inter-Integrated Circui
Page 69 and 70: Power and Clocking 8 8.1 Operating
Page 71 and 72: Power and Clocking Since few system
Page 73 and 74: Power and Clocking Table 8-4. 32.76
Page 75 and 76: Power and Clocking Table 8-6. PXA25
Page 81 and 82: Power and Clocking Figure 8-2. Hard
Page 83 and 84: Power and Clocking Table 8-10. Slee
Page 85 and 86: Power and Clocking Table 8-14. Sync
Page 87 and 88: Power and Clocking Table 8-16. Vari
Page 89 and 90: Power and Clocking • Provide powe
Page 91 and 92: Power and Clocking 8.7.4 I/O 3.3 V
Page 93 and 94: JTAG/Debug Port 9 9.1 Description T
Page 95 and 96: SA-1110/Applications Processor Migr
Page 105 and 106: Example Form Factor Reference Desig
Page 107 and 108: 8 1 7 6 5 4 3 2 Copyright 2002 Inte
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8 IN_PWR {10,15} D10 1 Pg. 12 7 6 5
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8 C C 1 7 6 5 4 3 2 Copyright 2002
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8 B B A A PXA250 Processor Referenc
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BBPXA2xx Development Baseboard Sche
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BBPXA2xx Development Baseboard Sche
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DCPXA250 Processor Card 32-bit vers
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DCPXA210 Processor Card 4 CONNECTOR
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Intel PXA250 and PXA210 Applications Processors

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