Intel PXA250 and PXA210 Applications Processors

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MultiMediaCard (MMC) 5.1.4 Pull-up and Pull-down Table 5-4 and Table 5-5 show the pull-up and pull-down resistors required for SDCard and MMC devices according to their respective specifications. Table 5-4. SDCard Pull-up and Pull-down Resistors Signal Pull-up or Pull-down Min Max Remark CMD pull-up 10kΩ 100kΩ Prevents bus floating DAT0-DAT3 pull-up 10kΩ 100kΩ Prevents bus floating WP 1 pull-up — — Any value sufficient to prevent bus floating NOTE: 1. This resistor is shown in the specification but the value is not specified Table 5-5. MMC Pull-up and Pull-down Resistors Signal Pull-up or Pull-down Min Max Remark CMD pull-up 4.7kΩ 100kΩ Prevents bus floating DAT pull-up 50kΩ 100kΩ Prevents bus floating 5.2 Utilized Features The applications processor MultiMediaCard controller has these features: • Data transfer rates as fast as 20 Mbps • A16 bit response FIFO • Dual receive data FIFOs • Dual transmit FIFOs • Support for two MMCs in either MMC or SPI mode The sample schematics in this section support MMC and SDCard and are configured to use MMC or SPI mode. The applications processor MultiMediaCard controller and the MMC device have the same maximum data rate, 20 Mbps, so their communication rates are compatible. However, because the maximum applications processor MultiMediaCard controller data rate is 20 Mbps and the maximum SDCard data rate is 25 Mbps, SDCard devices are not utilized to their fullest extent. The circuit designs presented in this guide (Figure 5-1 and Figure 5-2) only show support for one SDCard or MMC device, but the applications processor MultiMediaCard controller handles as many as two devices. 5-6 PXA250 and PXA210 Applications Processors Design Guide
AC97 6 The AC97 controller unit (ACUNIT) connects audio chips and codecs to the applications processor. It uses a six-wire interface to transmit and receive data from AC97 2.0 compliant codecs. The AC97 port is a bidirectional, serial PCM digital stream. A maximum of two codecs may be connected to the ACUNIT. 6.1 Schematics The schematics for an AC97 connection are shown in Figure 6-1. The primary codec supplies the 12.288 MHz clock to the AC97. This clock is then driven into the ACUNIT on the applications processor and the AC97 Secondary Codec. Figure 6-1. AC97 connection nACRESET SDATA_OUT PXA250 AC97 Controller SYNC (48KHz) SDATA_IN_0 SDATA_IN_1 BITCLK (12.288MHz) AC97 Primary CODEC AC97 Secondary Codec PXA250 and PXA210 Applications Processors Design Guide 6-1
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Intel ® PXA250 and PXA210 Applicat
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Contents Contents 1 Introduction...
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Contents A.1 SA-1110 Hardware Migra
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Contents 2-7 SRAM / ROM / Flash / S
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Introduction 1 Table 1-1. Revision
Page 11 and 12: Introduction • System memory inte
Page 13 and 14: Introduction Table 1-3. Signal Pin
Page 19 and 20: Introduction Figure 1-2. PXA250 App
Page 21 and 22: Introduction Table 1-4. PXA250 Appl
Page 23 and 24: Introduction Figure 1-3. PXA210 App
Page 25 and 26: Introduction Table 1-5. PXA210 Appl
Page 27 and 28: System Memory Interface 2 This sect
Page 29 and 30: System Memory Interface Table 2-1.
Page 31 and 32: . System Memory Interface 2.4 SDRAM
Page 39 and 40: System Memory Interface Figure 2-5.
Page 41 and 42: System Memory Interface Figure 2-6.
Page 43 and 44: System Memory Interface 2.7 System
Page 45 and 46: LCD Display Controller 3 This chapt
Page 47 and 48: LCD Display Controller Figure 3-1.
Page 49 and 50: LCD Display Controller Figure 3-5.
Page 51 and 52: LCD Display Controller Note: This e
Page 53 and 54: LCD Display Controller However, typ
Page 55 and 56: USB Interface 4 4.1 Self Powered De
Page 57 and 58: MultiMediaCard (MMC) 5 The MultiMed
Page 59 and 60: MultiMediaCard (MMC) Figure 5-1. Ap
Page 61: MultiMediaCard (MMC) Warning: Conne
Page 65 and 66: I 2 C 7 The Inter-Integrated Circui
Page 67 and 68: . I2C Figure 7-2. Using an Analog S
Page 69 and 70: Power and Clocking 8 8.1 Operating
Page 71 and 72: Power and Clocking Since few system
Page 73 and 74: Power and Clocking Table 8-4. 32.76
Page 75 and 76: Power and Clocking Table 8-6. PXA25
Page 81 and 82: Power and Clocking Figure 8-2. Hard
Page 83 and 84: Power and Clocking Table 8-10. Slee
Page 85 and 86: Power and Clocking Table 8-14. Sync
Page 87 and 88: Power and Clocking Table 8-16. Vari
Page 89 and 90: Power and Clocking • Provide powe
Page 91 and 92: Power and Clocking 8.7.4 I/O 3.3 V
Page 93 and 94: JTAG/Debug Port 9 9.1 Description T
Page 95 and 96: SA-1110/Applications Processor Migr
Page 105 and 106: Example Form Factor Reference Desig
Page 107 and 108: 8 1 7 6 5 4 3 2 Copyright 2002 Inte
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8 IN_PWR {10,15} D10 1 Pg. 12 7 6 5
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8 C C 1 7 6 5 4 3 2 Copyright 2002
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8 B B A A PXA250 Processor Referenc
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BBPXA2xx Development Baseboard Sche
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BBPXA2xx Development Baseboard Sche
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DCPXA250 Processor Card 32-bit vers
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DCPXA210 Processor Card 4 CONNECTOR
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Intel PXA250 and PXA210 Applications Processors

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