Intel PXA250 and PXA210 Applications Processors

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MultiMediaCard (MMC) 5.1.2 How to Wire Notice in the example schematic (Figure 5-1, “Applications Processor MMC and SDCard Signal Connections” on page 5-3) an SDCard socket is used. The signals on the socket are defined in Table 5-2. Table 5-2. SDCard Socket Signals Signal Name Pin # DAT3 1 CMD 2 VSS1 3 VDD 4 CLK 5 VSS2 6 DAT0 7 DAT1 8 DAT2 9 As stated previously, the PXA250 MMC controller can be connected to either an MMC device or an SDCard device, but you are limited to which device installs in which socket. Refer to Table 5-3 for information on sockets and device supported by the MMC controller. Table 5-3. MMC Controller Supported Sockets and Devices Sockets Devices Supported SDCard socket MMC socket SDCard device MMC device MMC device Figure 5-1 is a schematic that supports both MMC and SDCard devices. In the schematic, the signals SA_MMCLK, SA_MMCMD, and SA_DAT correspond to the applications processor signals MMCLK, MMCMD, and MMDAT, respectively. These three signals are also directly connected to the socket. 5-2 PXA250 and PXA210 Applications Processors Design Guide
MultiMediaCard (MMC) Figure 5-1. Applications Processor MMC and SDCard Signal Connections J10 DC3P3V CHECK II Bottom Mount DAT2 0 CD_DAT3 1 CMD 2 VSS1 3 VDD 4 CLK 5 VSS2 6 DAT0 7 DAT1 8 WP COMM CD 10 11 12 R229 100K DC3P3V MMC_WP MMC_C50 R147 SA_MMCCLK SA_MMDAT R150 47.5K DC3P3V 10K R226 C91 0K SA_MMCMD 0.1uF R225 0K DNI IF SD CARD Selection Resistors and Values Resistors SDCard MMC R226 R227 R225 R228 DNI DNI 0 100K 0 100K DNI DNI DNI IF MMC R227 R228 DC3P3V 100K 100K MMC_PWR DNI IF SD nMMC_DETECT DNI IF MMC U27 MMC_ON DC5P5V 1 2 3 MIC5207- 3.38M5 3.3V LDO REG 180ns VIN GND EN LE33 VOUT BYP 5 4 4.7uF 1 C92 MMC_PWR 2 A8698-01 MMC_CS0, which corresponds to the applications processor MMCCS0 signal, is connected to the socket at pin 1. This connection is the SPI mode chip select and is available on both MMC and SDCard. This pin is also labeled DAT3. DAT3 is only used with an SDCard in SDCard mode and not available on the applications processor MMC controller. The signals DAT1 and DAT2 are not connected because these are specific to SDCard operation in SDCard mode. PXA250 and PXA210 Applications Processors Design Guide 5-3
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Intel ® PXA250 and PXA210 Applicat
Page 3 and 4:
Contents Contents 1 Introduction...
Page 5 and 6:
Contents A.1 SA-1110 Hardware Migra
Page 7 and 8: Contents 2-7 SRAM / ROM / Flash / S
Page 9 and 10: Introduction 1 Table 1-1. Revision
Page 11 and 12: Introduction • System memory inte
Page 13 and 14: Introduction Table 1-3. Signal Pin
Page 19 and 20: Introduction Figure 1-2. PXA250 App
Page 21 and 22: Introduction Table 1-4. PXA250 Appl
Page 23 and 24: Introduction Figure 1-3. PXA210 App
Page 25 and 26: Introduction Table 1-5. PXA210 Appl
Page 27 and 28: System Memory Interface 2 This sect
Page 29 and 30: System Memory Interface Table 2-1.
Page 31 and 32: . System Memory Interface 2.4 SDRAM
Page 39 and 40: System Memory Interface Figure 2-5.
Page 41 and 42: System Memory Interface Figure 2-6.
Page 43 and 44: System Memory Interface 2.7 System
Page 45 and 46: LCD Display Controller 3 This chapt
Page 47 and 48: LCD Display Controller Figure 3-1.
Page 49 and 50: LCD Display Controller Figure 3-5.
Page 51 and 52: LCD Display Controller Note: This e
Page 53 and 54: LCD Display Controller However, typ
Page 55 and 56: USB Interface 4 4.1 Self Powered De
Page 57: MultiMediaCard (MMC) 5 The MultiMed
Page 61 and 62: MultiMediaCard (MMC) Warning: Conne
Page 63 and 64: AC97 6 The AC97 controller unit (AC
Page 65 and 66: I 2 C 7 The Inter-Integrated Circui
Page 67 and 68: . I2C Figure 7-2. Using an Analog S
Page 69 and 70: Power and Clocking 8 8.1 Operating
Page 71 and 72: Power and Clocking Since few system
Page 73 and 74: Power and Clocking Table 8-4. 32.76
Page 75 and 76: Power and Clocking Table 8-6. PXA25
Page 81 and 82: Power and Clocking Figure 8-2. Hard
Page 83 and 84: Power and Clocking Table 8-10. Slee
Page 85 and 86: Power and Clocking Table 8-14. Sync
Page 87 and 88: Power and Clocking Table 8-16. Vari
Page 89 and 90: Power and Clocking • Provide powe
Page 91 and 92: Power and Clocking 8.7.4 I/O 3.3 V
Page 93 and 94: JTAG/Debug Port 9 9.1 Description T
Page 95 and 96: SA-1110/Applications Processor Migr
Page 105 and 106: Example Form Factor Reference Desig
Page 107 and 108: 8 1 7 6 5 4 3 2 Copyright 2002 Inte
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8 1 Sheet 4 of 16 1 7 6 5 4 3 2 Cop
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8 1 Sheet 6 of 16 1 7 6 5 4 3 2 Cop
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8 1 Sheet 8 of 16 1 7 6 5 4 3 2 Cop
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8 1 Sheet 10 of 16 1 7 6 5 4 3 2 Co
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8 IN_PWR {10,15} D10 1 Pg. 12 7 6 5
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8 C C 1 7 6 5 4 3 2 Copyright 2002
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8 B B A A PXA250 Processor Referenc
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BBPXA2xx Development Baseboard Sche
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BBPXA2xx Development Baseboard Sche
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DCPXA250 Processor Card 32-bit vers
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DCPXA210 Processor Card 4 CONNECTOR
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Intel PXA250 and PXA210 Applications Processors

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