Intel PXA250 and PXA210 Applications Processors
Intel PXA250 and PXA210 Applications Processors Intel PXA250 and PXA210 Applications Processors
LCD Display Controller 3-10 PXA250 and PXA210 Applications Processor Design Guide
USB Interface 4 4.1 Self Powered Device Figure 4-1 shows the USB interface connection for a self-powered device. The 0 ohm resistors are optional, and if not used, then connect USB UDC+ directly to the device UDC+ and connect USB UDC- directly to device UDC-. The device UDC+ and UDC- pins match the impedance of a USB cable, 90 ohms, without the use of external series resistors. You may install 0 ohm resistors on your board to compensate for minor differences between the USB cable and your board trace impedance. The 5 to 3.3 voltage divider is required since the device GPIO pins cannot exceed 3.3 V. This voltage divider can be implemented in a number of ways. The most robust and expensive solution is to use a MAX6348 Power-On-Reset device. This solution produces a very clean signal edge and minimizes signal bounce. The more inexpensive solution is to use a 3.3 V line buffer with 5 V tolerant inputs. This solution does not reduce signal bounce, so software must compensate by reading the GPIO signal after it stabilizes. A third solution is to implement a signal bounce minimization circuit that is 5 V tolerant, but produces a 3.3 V signal to the GPIO pin. Note: If GPIOn and GPIOx are the same pin, never put the device to sleep while the USB cable is connected to the device. During sleep, the USB controller is in reset and will not respond to the host; after sleep, the device will not respond to its host-assigned address. Figure 4-1. Self Powered Device USB 5V 5V to 3.3V GPIOn USB UDC+ USB GND 470K 1.5K 0 ohm (optional) 0 ohm (optional) USB UDC- GPIOx UDC+ UDC- Board GND 4.1.1 Operation if GPIOn and GPIOx are Different Pins Any GPIO pins can be defined as GPIOn and GPIOx. GPIOn should be a GPIO which can bring the device out of sleep. Out of reset, configure GPIOx as an input that causes the UDC+ line to float. GPIOn is configured as an input that causes an interrupt whenever a rising or falling edge is PXA250 and PXA210 Applications Processors Design Guide 4-1
- Page 3 and 4: Contents Contents 1 Introduction...
- Page 5 and 6: Contents A.1 SA-1110 Hardware Migra
- Page 7 and 8: Contents 2-7 SRAM / ROM / Flash / S
- Page 9 and 10: Introduction 1 Table 1-1. Revision
- Page 11 and 12: Introduction • System memory inte
- Page 13 and 14: Introduction Table 1-3. Signal Pin
- Page 15 and 16: Introduction Table 1-3. Signal Pin
- Page 17 and 18: Introduction Table 1-3. Signal Pin
- Page 19 and 20: Introduction Figure 1-2. PXA250 App
- Page 21 and 22: Introduction Table 1-4. PXA250 Appl
- Page 23 and 24: Introduction Figure 1-3. PXA210 App
- Page 25 and 26: Introduction Table 1-5. PXA210 Appl
- Page 27 and 28: System Memory Interface 2 This sect
- Page 29 and 30: System Memory Interface Table 2-1.
- Page 31 and 32: . System Memory Interface 2.4 SDRAM
- Page 33 and 34: System Memory Interface Table 2-4.
- Page 35 and 36: System Memory Interface Table 2-6.
- Page 37 and 38: System Memory Interface Table 2-8.
- Page 39 and 40: System Memory Interface Figure 2-5.
- Page 41 and 42: System Memory Interface Figure 2-6.
- Page 43 and 44: System Memory Interface 2.7 System
- Page 45 and 46: LCD Display Controller 3 This chapt
- Page 47 and 48: LCD Display Controller Figure 3-1.
- Page 49 and 50: LCD Display Controller Figure 3-5.
- Page 51 and 52: LCD Display Controller Note: This e
- Page 53: LCD Display Controller However, typ
- Page 57 and 58: MultiMediaCard (MMC) 5 The MultiMed
- Page 59 and 60: MultiMediaCard (MMC) Figure 5-1. Ap
- Page 61 and 62: MultiMediaCard (MMC) Warning: Conne
- Page 63 and 64: AC97 6 The AC97 controller unit (AC
- Page 65 and 66: I 2 C 7 The Inter-Integrated Circui
- Page 67 and 68: . I2C Figure 7-2. Using an Analog S
- Page 69 and 70: Power and Clocking 8 8.1 Operating
- Page 71 and 72: Power and Clocking Since few system
- Page 73 and 74: Power and Clocking Table 8-4. 32.76
- Page 75 and 76: Power and Clocking Table 8-6. PXA25
- Page 77 and 78: Power and Clocking Table 8-6. PXA25
- Page 79 and 80: Power and Clocking Table 8-6. PXA25
- Page 81 and 82: Power and Clocking Figure 8-2. Hard
- Page 83 and 84: Power and Clocking Table 8-10. Slee
- Page 85 and 86: Power and Clocking Table 8-14. Sync
- Page 87 and 88: Power and Clocking Table 8-16. Vari
- Page 89 and 90: Power and Clocking • Provide powe
- Page 91 and 92: Power and Clocking 8.7.4 I/O 3.3 V
- Page 93 and 94: JTAG/Debug Port 9 9.1 Description T
- Page 95 and 96: SA-1110/Applications Processor Migr
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USB Interface 4<br />
4.1 Self Powered Device<br />
Figure 4-1 shows the USB interface connection for a self-powered device. The 0 ohm resistors are<br />
optional, <strong>and</strong> if not used, then connect USB UDC+ directly to the device UDC+ <strong>and</strong> connect USB<br />
UDC- directly to device UDC-. The device UDC+ <strong>and</strong> UDC- pins match the impedance of a USB<br />
cable, 90 ohms, without the use of external series resistors. You may install 0 ohm resistors on your<br />
board to compensate for minor differences between the USB cable <strong>and</strong> your board trace<br />
impedance.<br />
The 5 to 3.3 voltage divider is required since the device GPIO pins cannot exceed 3.3 V. This<br />
voltage divider can be implemented in a number of ways. The most robust <strong>and</strong> expensive solution<br />
is to use a MAX6348 Power-On-Reset device. This solution produces a very clean signal edge <strong>and</strong><br />
minimizes signal bounce. The more inexpensive solution is to use a 3.3 V line buffer with 5 V<br />
tolerant inputs. This solution does not reduce signal bounce, so software must compensate by<br />
reading the GPIO signal after it stabilizes. A third solution is to implement a signal bounce<br />
minimization circuit that is 5 V tolerant, but produces a 3.3 V signal to the GPIO pin.<br />
Note:<br />
If GPIOn <strong>and</strong> GPIOx are the same pin, never put the device to sleep while the USB cable is<br />
connected to the device. During sleep, the USB controller is in reset <strong>and</strong> will not respond to the<br />
host; after sleep, the device will not respond to its host-assigned address.<br />
Figure 4-1. Self Powered Device<br />
USB 5V<br />
5V to 3.3V<br />
GPIOn<br />
USB UDC+<br />
USB GND<br />
470K<br />
1.5K<br />
0 ohm<br />
(optional)<br />
0 ohm<br />
(optional)<br />
USB UDC-<br />
GPIOx<br />
UDC+<br />
UDC-<br />
Board GND<br />
4.1.1 Operation if GPIOn <strong>and</strong> GPIOx are Different Pins<br />
Any GPIO pins can be defined as GPIOn <strong>and</strong> GPIOx. GPIOn should be a GPIO which can bring<br />
the device out of sleep. Out of reset, configure GPIOx as an input that causes the UDC+ line to<br />
float. GPIOn is configured as an input that causes an interrupt whenever a rising or falling edge is<br />
<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide 4-1
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