Intel PXA250 and PXA210 Applications Processors

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LCD Display Controller Table 3-3. Active Display Pins Required PXA250 Pin LCD Panel Pin PIn Type 1 Definition L_DD R,G, B Output L_PCLK Clock Output L_LCLK Horizontal Sync Output L_FCLK Vertical Sync Output L_BIAS DE (Data Enable) Output N/A Vcon 2 N/A Data lines used to transmit the 16 bit data values to the LCD display. Pixel Clock - used by the LCD display to clock the pixel data into the line shift register. In active mode this clock transitions constantly. Line Clock - used by the LCD display to signal the end of a line of pixels that transfers the line data from the shift register to the screen and increment the line pointers. Also signals the panel to start a new line. Frame Clock - used by the LCD displays to signal the start of a new frame of pixels that resets the line pointers to the top of the screen. AC biases used in active mode as a data enable signal when data should be latched by the pixel clock from the data lines. Contrast Voltage - Adjustable voltage input to LCD panel - external voltage circuitry is required (no pin available on the PXA250 applications processor). NOTES: 1. In reference to the PXA250 applications processor. Therefore, outputs are pins that drive a signal from the PXA250 applications processor to another device. 2. Vcon is a signal external to the PXA250 applications processor. Please refer to Section 3.5.1, “Contrast Voltage” on page 8. 3.3.1 Typical connections for Active Panel Displays Figure 3-6, “Active Color Display Typical Connection” on page 7 shows a typical connection for an active panel display and should serve as a guide for designing systems which contain active LCD displays. The MSB of each color is indicated. The panel is 18-bit, with the LSB of red and blue tied to ground. 3-6 PXA250 and PXA210 Applications Processor Design Guide
LCD Display Controller Note: This example shows 6 red, 6 green and 6 blue bits on the LCD panel. However, different active display panels might have more or different data lines. Consult the LCD panel manufacturer’s datasheet for the actual data lines. Figure 3-6. Active Color Display Typical Connection PXA250 Processor L_DD0 L_DD1 L_DD2 L_DD3 L_DD4 - MSB of Blue L_DD5 L_DD6 L_DD7 L_DD8 L_DD9 L_DD10 - MSB of Green L_DD11 L_DD12 L_DD13 L_DD14 L_DD15 - MSB of Red B0 B1 B2 B3 B4 B5 G0 G1 G2 G3 G4 G5 R0 R1 R2 R3 R4 R5 LCD Panel L_PCLK L_LCLK L_FCLK L_BIAS Clock Horizontal Sync Vertical Sync Data Enable 3.4 PXA250 Pinout Table 3-4 describes the ball positions for the LCD controller on the PXA250 applications processor. Table 3-4. PXA250 LCD Controller Ball Positions (Sheet 1 of 2) Pin Name L_DD0 L_DD1 L_DD2 L_DD3 L_DD4 L_DD5 L_DD6 L_DD7 L_DD8 L_DD9 L_DD10 L_DD11 Ball Position E7 D7 C7 B7 E6 D6 E5 A6 C5 A5 D5 A4 PXA250 and PXA210 Applications Processor Design Guide 3-7
Page 1 and 2: Intel ® PXA250 and PXA210 Applicat
Page 3 and 4: Contents Contents 1 Introduction...
Page 5 and 6: Contents A.1 SA-1110 Hardware Migra
Page 7 and 8: Contents 2-7 SRAM / ROM / Flash / S
Page 9 and 10: Introduction 1 Table 1-1. Revision
Page 11 and 12: Introduction • System memory inte
Page 13 and 14: Introduction Table 1-3. Signal Pin
Page 19 and 20: Introduction Figure 1-2. PXA250 App
Page 21 and 22: Introduction Table 1-4. PXA250 Appl
Page 23 and 24: Introduction Figure 1-3. PXA210 App
Page 25 and 26: Introduction Table 1-5. PXA210 Appl
Page 27 and 28: System Memory Interface 2 This sect
Page 29 and 30: System Memory Interface Table 2-1.
Page 31 and 32: . System Memory Interface 2.4 SDRAM
Page 39 and 40: System Memory Interface Figure 2-5.
Page 41 and 42: System Memory Interface Figure 2-6.
Page 43 and 44: System Memory Interface 2.7 System
Page 45 and 46: LCD Display Controller 3 This chapt
Page 47 and 48: LCD Display Controller Figure 3-1.
Page 49: LCD Display Controller Figure 3-5.
Page 53 and 54: LCD Display Controller However, typ
Page 55 and 56: USB Interface 4 4.1 Self Powered De
Page 57 and 58: MultiMediaCard (MMC) 5 The MultiMed
Page 59 and 60: MultiMediaCard (MMC) Figure 5-1. Ap
Page 61 and 62: MultiMediaCard (MMC) Warning: Conne
Page 63 and 64: AC97 6 The AC97 controller unit (AC
Page 65 and 66: I 2 C 7 The Inter-Integrated Circui
Page 67 and 68: . I2C Figure 7-2. Using an Analog S
Page 69 and 70: Power and Clocking 8 8.1 Operating
Page 71 and 72: Power and Clocking Since few system
Page 73 and 74: Power and Clocking Table 8-4. 32.76
Page 75 and 76: Power and Clocking Table 8-6. PXA25
Page 81 and 82: Power and Clocking Figure 8-2. Hard
Page 83 and 84: Power and Clocking Table 8-10. Slee
Page 85 and 86: Power and Clocking Table 8-14. Sync
Page 87 and 88: Power and Clocking Table 8-16. Vari
Page 89 and 90: Power and Clocking • Provide powe
Page 91 and 92: Power and Clocking 8.7.4 I/O 3.3 V
Page 93 and 94: JTAG/Debug Port 9 9.1 Description T
Page 95 and 96: SA-1110/Applications Processor Migr
Page 101 and 102:
SA-1110/Applications Processor Migr
Page 103 and 104:
SA-1110/Applications Processor Migr
Page 105 and 106:
Example Form Factor Reference Desig
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8 1 7 6 5 4 3 2 Copyright 2002 Inte
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8 1 Sheet 4 of 16 1 7 6 5 4 3 2 Cop
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8 1 Sheet 6 of 16 1 7 6 5 4 3 2 Cop
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8 1 Sheet 8 of 16 1 7 6 5 4 3 2 Cop
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8 1 Sheet 10 of 16 1 7 6 5 4 3 2 Co
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8 IN_PWR {10,15} D10 1 Pg. 12 7 6 5
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8 C C 1 7 6 5 4 3 2 Copyright 2002
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8 B B A A PXA250 Processor Referenc
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BBPXA2xx Development Baseboard Sche
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BBPXA2xx Development Baseboard Sche
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DCPXA250 Processor Card 32-bit vers
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DCPXA210 Processor Card 4 CONNECTOR
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Intel PXA250 and PXA210 Applications Processors

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