Intel PXA250 and PXA210 Applications Processors

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LCD Display Controller Figure 3-3. Passive Monochrome Dual Panel Displays Typical Connection L_DD0 - Top left for upper panel L_DD1 L_DD2 L_DD3 DU_0 DU_1 DU_2 DU_3 Upper Panel PXA250 Processor L_PCLK L_LCLK L_FCLK L_BIAS Pixel_Clock Line_Clock Frame_Clock Bias LCD Display L_DD4 - Top left for lower panel L_DD5 L_DD6 L_DD7 DL_0 DL_1 DL_2 DL_3 Lower Panel 3.2.1.4 Passive Color Single Panel Displays Figure 3-4 is a typical single-panel-color passive display connection. Figure 3-4. Passive Color Single Panel Displays Typical Connection PXA250 Processor L_DD0 L_DD1 L_DD2 L_DD3 L_DD4 L_DD5 - Top left Blue L_DD6 - Top left Green L_DD7 - Top left Red D0 D1 D2 D3 D4 D5 D6 D7 LCD Display L_PCLK L_LCLK L_FCLK L_BIAS Pixel_Clock Line_Clock Frame_Clock Bias 3.2.1.5 Passive Color Dual Panel Displays Figure 3-5 is a typical dual-panel-color passive display connection. 3-4 PXA250 and PXA210 Applications Processor Design Guide
LCD Display Controller Figure 3-5. Passive Color Dual Panel Displays Typical Connection PXA250 Processor L_DD0 L_DD1 L_DD2 L_DD3 L_DD4 L_DD5 - Top left Blue for upper panel L_DD6 - Top left Green for upper panel L_DD7 - Top left Red for upper panel L_PCLK L_LCLK L_FCLK L_BIAS DU_0 DU_1 DU_2 DU_3 DU_4 DU_5 DU_6 DU_7 Pixel_Clock Line_Clock Frame_Clock Bias Upper Panel LCD Display L_DD8 L_DD9 L_DD10 L_DD11 L_DD12 L_DD13 - Top left Blue for lower panel L_DD14 - Top left Green for lower panel L_DD15 - Top left Red for lower panel DL_0 DL_1 DL_2 DL_3 DL_4 DL_5 DL_6 DL_7 Lower Panel 3.3 Active (TFT) Displays Because data is sent to the panel as raw 16-bit pixel data, active displays require16 data pins in order to transfer the pixel data from the controller. All 16 data lines are also required to drive one pixel value. The 16 bits of data describe the intensity level of the red, green and blue for each pixel. Typically, this is formatted as 5 bits for red, 6 bits for green and 5 bits for blue, but this can vary by display and is controlled by the software writing to the frame buffer. Refer to the display datasheet to ensure that the correct the PXA250 applications processor LCD data lines are connected to the correct LCD panel data lines. Many active displays actually have more than 16 data lines - usually 18 (6 of each color). For these panels it is recommended that the most significant lines of the panel lines are connected to the data lines from the PXA250 applications processor. This maintains the panel’s full range of colors but increases the granularity of the color spectrum with an insufficient number of data lines. All unused panel data lines can be tied either high or low. Other options include tying the LSB of red and blue to the next bit, R1 or B1. For active displays, connect the pins described in Table 3-3 between the PXA250 applications processor and the LCD panel. PXA250 and PXA210 Applications Processor Design Guide 3-5
Page 1 and 2: Intel ® PXA250 and PXA210 Applicat
Page 3 and 4: Contents Contents 1 Introduction...
Page 5 and 6: Contents A.1 SA-1110 Hardware Migra
Page 7 and 8: Contents 2-7 SRAM / ROM / Flash / S
Page 9 and 10: Introduction 1 Table 1-1. Revision
Page 11 and 12: Introduction • System memory inte
Page 13 and 14: Introduction Table 1-3. Signal Pin
Page 19 and 20: Introduction Figure 1-2. PXA250 App
Page 21 and 22: Introduction Table 1-4. PXA250 Appl
Page 23 and 24: Introduction Figure 1-3. PXA210 App
Page 25 and 26: Introduction Table 1-5. PXA210 Appl
Page 27 and 28: System Memory Interface 2 This sect
Page 29 and 30: System Memory Interface Table 2-1.
Page 31 and 32: . System Memory Interface 2.4 SDRAM
Page 39 and 40: System Memory Interface Figure 2-5.
Page 41 and 42: System Memory Interface Figure 2-6.
Page 43 and 44: System Memory Interface 2.7 System
Page 45 and 46: LCD Display Controller 3 This chapt
Page 47: LCD Display Controller Figure 3-1.
Page 51 and 52: LCD Display Controller Note: This e
Page 53 and 54: LCD Display Controller However, typ
Page 55 and 56: USB Interface 4 4.1 Self Powered De
Page 57 and 58: MultiMediaCard (MMC) 5 The MultiMed
Page 59 and 60: MultiMediaCard (MMC) Figure 5-1. Ap
Page 61 and 62: MultiMediaCard (MMC) Warning: Conne
Page 63 and 64: AC97 6 The AC97 controller unit (AC
Page 65 and 66: I 2 C 7 The Inter-Integrated Circui
Page 67 and 68: . I2C Figure 7-2. Using an Analog S
Page 69 and 70: Power and Clocking 8 8.1 Operating
Page 71 and 72: Power and Clocking Since few system
Page 73 and 74: Power and Clocking Table 8-4. 32.76
Page 75 and 76: Power and Clocking Table 8-6. PXA25
Page 81 and 82: Power and Clocking Figure 8-2. Hard
Page 83 and 84: Power and Clocking Table 8-10. Slee
Page 85 and 86: Power and Clocking Table 8-14. Sync
Page 87 and 88: Power and Clocking Table 8-16. Vari
Page 89 and 90: Power and Clocking • Provide powe
Page 91 and 92: Power and Clocking 8.7.4 I/O 3.3 V
Page 93 and 94: JTAG/Debug Port 9 9.1 Description T
Page 95 and 96: SA-1110/Applications Processor Migr
Page 97 and 98: SA-1110/Applications Processor Migr
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SA-1110/Applications Processor Migr
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Page 105 and 106:
Example Form Factor Reference Desig
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8 1 7 6 5 4 3 2 Copyright 2002 Inte
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8 1 Sheet 4 of 16 1 7 6 5 4 3 2 Cop
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8 1 Sheet 10 of 16 1 7 6 5 4 3 2 Co
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8 IN_PWR {10,15} D10 1 Pg. 12 7 6 5
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8 C C 1 7 6 5 4 3 2 Copyright 2002
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8 B B A A PXA250 Processor Referenc
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BBPXA2xx Development Baseboard Sche
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BBPXA2xx Development Baseboard Sche
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DCPXA250 Processor Card 32-bit vers
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DCPXA210 Processor Card 4 CONNECTOR
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Intel PXA250 and PXA210 Applications Processors

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