Intel PXA250 and PXA210 Applications Processors

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LCD Display Controller Table 3-1. LCD Controller Data Pin Utilization (Sheet 2 of 2) Color/ Monochrome Panel Single/ Dual Panel Double-Pixel Mode Screen Portion Pins Color Dual N/A NOTE: 1. Double pixel data mode (DPD)=1. Top Bottom L_DD L_DD For passive displays, the pins described in Table 3-2 are required connections between the PXA250 applications processor and your LCD panel. Table 3-2. Passive Display Pins Required PXA250 Pin LCD Panel Pin PIn Type 1 Definition L_DD DU_x, DL_x Output Data lines used to transmit either four or eight data values at a time to the LCD display. For monochrome displays, each pin value represents a single pixel; for passive color, groupings of three pin values represent one pixel (red, green, and blue data values). Either the bottom four pins (L_DD), the bottom 8 pins (L_DD) or all 16 pixel data pins (L_DD)will be used as shown in Table 3-1 L_PCLK Pixel_Clock Output L_LCLK Line_Clock Output L_FCLK Frame_Clock Output L_BIAS Bias Output N/A Vcon 2 N/A Pixel Clock - used by the LCD display to clock the pixel data into the line shift register. Line Clock - used by the LCD display to signal the end of a line of pixels that transfers the line data from the shift register to the screen and increment the line pointers. Frame Clock - used by the LCD displays to signal the start of a new frame of pixels that resets the line pointers to the top of the screen. AC bias used to signal the LCD display to switch the polarity of the power supplies to the row and column axis of the screen to counteract DC offset. Contrast Voltage - Adjustable voltage input to LCD panel - external voltage circuitry is required (no pin available on PXA250). NOTES: 1. “Pin Type” is in reference to the PXA250 applications processor. Therefore, outputs are pins that drive a signal from the processor to another device. 2. Vcon is a signal external to the PXA250 applications processor. Please refer to “Contrast Voltage” on page 8 3.2.1 Typical Connections for Passive Panel Displays The following diagrams are typical connections and serve a guide for designing systems which contain passive LCD displays. Panels differ on which is the panel’s lest significant bit (Refer to the LCD panel reference documentation for the lest significant bit.) Each figure indicates the top-left pixel (1,1) bit. While dual panels indicates the top-left pixel (1,n/2) of the upper and lower panels and color passive panels show the top-left-pixel color bits. 3.2.1.1 Passive Monochrome Single Panel Displays Figure 3-1 is a typical single-panel-monochrome passive display connection. 3-2 PXA250 and PXA210 Applications Processor Design Guide
LCD Display Controller Figure 3-1. Single Panel Monochrome Passive Display Typical Connection L_DD0 - Top left L_DD1 L_DD2 L_DD3 D0 D1 D2 D3 PXA250 Processor LCD Display L_PCLK L_LCLK L_FCLK L_BIAS Pixel_Clock Line_Clock Frame_Clock Bias 3.2.1.2 Passive Monochrome Single Panel Displays, Double-Pixel Data Figure 3-2 shows typical connections for a single-panel-monochrome passive display using double-pixel data mode. Figure 3-2. Passive Monochrome Single Panel Displays, Double-Pixel Data Typical Connection PXA250 Processor L_DD0 - Top left L_DD1 L_DD2 L_DD3 L_DD4 L_DD5 L_DD6 L_DD7 D0 D1 D2 D3 D4 D5 D6 D7 LCD Display L_PCLK L_LCLK L_FCLK L_BIAS Pixel_Clock Line_Clock Frame_Clock Bias 3.2.1.3 Passive Monochrome Dual Panel Displays Figure 3-3 is a typical dual-panel-monochrome passive display connection. PXA250 and PXA210 Applications Processor Design Guide 3-3
Page 1 and 2: Intel ® PXA250 and PXA210 Applicat
Page 3 and 4: Contents Contents 1 Introduction...
Page 5 and 6: Contents A.1 SA-1110 Hardware Migra
Page 7 and 8: Contents 2-7 SRAM / ROM / Flash / S
Page 9 and 10: Introduction 1 Table 1-1. Revision
Page 11 and 12: Introduction • System memory inte
Page 13 and 14: Introduction Table 1-3. Signal Pin
Page 19 and 20: Introduction Figure 1-2. PXA250 App
Page 21 and 22: Introduction Table 1-4. PXA250 Appl
Page 23 and 24: Introduction Figure 1-3. PXA210 App
Page 25 and 26: Introduction Table 1-5. PXA210 Appl
Page 27 and 28: System Memory Interface 2 This sect
Page 29 and 30: System Memory Interface Table 2-1.
Page 31 and 32: . System Memory Interface 2.4 SDRAM
Page 39 and 40: System Memory Interface Figure 2-5.
Page 41 and 42: System Memory Interface Figure 2-6.
Page 43 and 44: System Memory Interface 2.7 System
Page 45: LCD Display Controller 3 This chapt
Page 49 and 50: LCD Display Controller Figure 3-5.
Page 51 and 52: LCD Display Controller Note: This e
Page 53 and 54: LCD Display Controller However, typ
Page 55 and 56: USB Interface 4 4.1 Self Powered De
Page 57 and 58: MultiMediaCard (MMC) 5 The MultiMed
Page 59 and 60: MultiMediaCard (MMC) Figure 5-1. Ap
Page 61 and 62: MultiMediaCard (MMC) Warning: Conne
Page 63 and 64: AC97 6 The AC97 controller unit (AC
Page 65 and 66: I 2 C 7 The Inter-Integrated Circui
Page 67 and 68: . I2C Figure 7-2. Using an Analog S
Page 69 and 70: Power and Clocking 8 8.1 Operating
Page 71 and 72: Power and Clocking Since few system
Page 73 and 74: Power and Clocking Table 8-4. 32.76
Page 75 and 76: Power and Clocking Table 8-6. PXA25
Page 81 and 82: Power and Clocking Figure 8-2. Hard
Page 83 and 84: Power and Clocking Table 8-10. Slee
Page 85 and 86: Power and Clocking Table 8-14. Sync
Page 87 and 88: Power and Clocking Table 8-16. Vari
Page 89 and 90: Power and Clocking • Provide powe
Page 91 and 92: Power and Clocking 8.7.4 I/O 3.3 V
Page 93 and 94: JTAG/Debug Port 9 9.1 Description T
Page 95 and 96: SA-1110/Applications Processor Migr
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SA-1110/Applications Processor Migr
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Example Form Factor Reference Desig
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8 1 7 6 5 4 3 2 Copyright 2002 Inte
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8 1 Sheet 4 of 16 1 7 6 5 4 3 2 Cop
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8 IN_PWR {10,15} D10 1 Pg. 12 7 6 5
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8 C C 1 7 6 5 4 3 2 Copyright 2002
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8 B B A A PXA250 Processor Referenc
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BBPXA2xx Development Baseboard Sche
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BBPXA2xx Development Baseboard Sche
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DCPXA250 Processor Card 32-bit vers
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DCPXA210 Processor Card 4 CONNECTOR
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Intel PXA250 and PXA210 Applications Processors

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