Intel PXA250 and PXA210 Applications Processors
Intel PXA250 and PXA210 Applications Processors Intel PXA250 and PXA210 Applications Processors
System Memory Interface Figure 2-11. MD maximum loading topology SDRAM SDRAM MD AUX AUX AUX AUX 2.7.2 System Memory Recommended Trace Lengths Table 2-10 details the minimum and maximum trace lengths that were simulated for the applications processor. These trace lengths are not the absolute trace lengths that will work given the loading conditions. The trace lengths in Table 2-10 are measured from the applications processor to the individual component pins. The board impedance for the simulations was 60ohm +/- 10%. Table 2-10. Minimum and Maximum Trace Lengths for the SDRAM Signals Signal Min Trace Length Max Trace Length CS, CKE, DQM 0.75 in 4.5 in CLK 1.0 in 4.25 in MA 1.0 in 4.5 in MD 1.0 in 4.25 in 2-18 PXA250 and PXA210 Applications Processors Design Guide
LCD Display Controller 3 This chapter describes sample hardware connections from the PXA250 applications processor to various types of LCD controllers. Active (TFT) as well as passive (DSTN) displays are discussed as well as single and dual panel displays. These should not be considered the only possible ways to connect an LCD panel to the PXA250 applications processor, but should serve as a reference to assist with hardware design considerations. Other panels, for example panels without L_FCLK or L_LCLK, have been successfully connected to the PXA250. 3.1 LCD Display Overview The PXA250 applications processor supports both active and passive LCD displays. Active displays generally produce better looking images, but at a higher cost. Passive displays are generally less expensive, but their displays are inferior to active displays. However, recent advances in dithering technology are closing the quality gap between passive and active displays. Note: Names used for “LCD Panel Pin” are representative names and may not match those on all LCD panels. Refer to the LCD panel reference documentation for the actual name. 3.2 Passive (DSTN) Displays Several different types of passive displays are available in both color and monochrome. These maybe single or dual panel displays. Additionally, some monochrome displays use double-pixel data mode (twice the number of pixels as a normal monochrome display). With the exception of the number of data pins required, all of these choices affect the software configuration and support, not the system hardware design. In fact, most passive displays use a single interconnection scheme. For information on the software changes and performance considerations of the various display options, refer to the PXA250 and PXA210 Applications Processors Developer’s Manual. Passive displays drive dithered data to the LCD panel - which means that for each pixel clock cycle a single data line drives an ON/OFF signal for one color of a single pixel. Table 3-1 describes the number of L_DD pins required for the various types of passive displays, as well as which LCD data pins are used for which panel (upper or lower). Table 3-1. LCD Controller Data Pin Utilization (Sheet 1 of 2) Color/ Monochrome Panel Single/ Dual Panel Double-Pixel Mode Screen Portion Pins Monochrome Single No Whole L_DD Monochrome Single Yes Whole L_DD 1 Top L_DD Monochrome Dual No Bottom L_DD Color Single N/A Whole L_DD PXA250 and PXA210 Applications Processor Design Guide 3-1
- Page 1 and 2: Intel ® PXA250 and PXA210 Applicat
- Page 3 and 4: Contents Contents 1 Introduction...
- Page 5 and 6: Contents A.1 SA-1110 Hardware Migra
- Page 7 and 8: Contents 2-7 SRAM / ROM / Flash / S
- Page 9 and 10: Introduction 1 Table 1-1. Revision
- Page 11 and 12: Introduction • System memory inte
- Page 13 and 14: Introduction Table 1-3. Signal Pin
- Page 15 and 16: Introduction Table 1-3. Signal Pin
- Page 17 and 18: Introduction Table 1-3. Signal Pin
- Page 19 and 20: Introduction Figure 1-2. PXA250 App
- Page 21 and 22: Introduction Table 1-4. PXA250 Appl
- Page 23 and 24: Introduction Figure 1-3. PXA210 App
- Page 25 and 26: Introduction Table 1-5. PXA210 Appl
- Page 27 and 28: System Memory Interface 2 This sect
- Page 29 and 30: System Memory Interface Table 2-1.
- Page 31 and 32: . System Memory Interface 2.4 SDRAM
- Page 33 and 34: System Memory Interface Table 2-4.
- Page 35 and 36: System Memory Interface Table 2-6.
- Page 37 and 38: System Memory Interface Table 2-8.
- Page 39 and 40: System Memory Interface Figure 2-5.
- Page 41 and 42: System Memory Interface Figure 2-6.
- Page 43: System Memory Interface 2.7 System
- Page 47 and 48: LCD Display Controller Figure 3-1.
- Page 49 and 50: LCD Display Controller Figure 3-5.
- Page 51 and 52: LCD Display Controller Note: This e
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- Page 55 and 56: USB Interface 4 4.1 Self Powered De
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- Page 63 and 64: AC97 6 The AC97 controller unit (AC
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- Page 67 and 68: . I2C Figure 7-2. Using an Analog S
- Page 69 and 70: Power and Clocking 8 8.1 Operating
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- Page 79 and 80: Power and Clocking Table 8-6. PXA25
- Page 81 and 82: Power and Clocking Figure 8-2. Hard
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LCD Display Controller 3<br />
This chapter describes sample hardware connections from the <strong>PXA250</strong> applications processor to<br />
various types of LCD controllers. Active (TFT) as well as passive (DSTN) displays are discussed<br />
as well as single <strong>and</strong> dual panel displays. These should not be considered the only possible ways to<br />
connect an LCD panel to the <strong>PXA250</strong> applications processor, but should serve as a reference to<br />
assist with hardware design considerations. Other panels, for example panels without L_FCLK or<br />
L_LCLK, have been successfully connected to the <strong>PXA250</strong>.<br />
3.1 LCD Display Overview<br />
The <strong>PXA250</strong> applications processor supports both active <strong>and</strong> passive LCD displays. Active<br />
displays generally produce better looking images, but at a higher cost. Passive displays are<br />
generally less expensive, but their displays are inferior to active displays. However, recent<br />
advances in dithering technology are closing the quality gap between passive <strong>and</strong> active displays.<br />
Note:<br />
Names used for “LCD Panel Pin” are representative names <strong>and</strong> may not match those on all LCD<br />
panels. Refer to the LCD panel reference documentation for the actual name.<br />
3.2 Passive (DSTN) Displays<br />
Several different types of passive displays are available in both color <strong>and</strong> monochrome. These<br />
maybe single or dual panel displays. Additionally, some monochrome displays use double-pixel<br />
data mode (twice the number of pixels as a normal monochrome display). With the exception of the<br />
number of data pins required, all of these choices affect the software configuration <strong>and</strong> support, not<br />
the system hardware design. In fact, most passive displays use a single interconnection scheme. For<br />
information on the software changes <strong>and</strong> performance considerations of the various display<br />
options, refer to the <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Developer’s Manual.<br />
Passive displays drive dithered data to the LCD panel - which means that for each pixel clock cycle<br />
a single data line drives an ON/OFF signal for one color of a single pixel.<br />
Table 3-1 describes the number of L_DD pins required for the various types of passive displays, as<br />
well as which LCD data pins are used for which panel (upper or lower).<br />
Table 3-1. LCD Controller Data Pin Utilization (Sheet 1 of 2)<br />
Color/<br />
Monochrome<br />
Panel<br />
Single/<br />
Dual Panel<br />
Double-Pixel<br />
Mode<br />
Screen Portion<br />
Pins<br />
Monochrome Single No Whole L_DD<br />
Monochrome Single Yes Whole L_DD 1<br />
Top<br />
L_DD<br />
Monochrome Dual No<br />
Bottom<br />
L_DD<br />
Color Single N/A Whole L_DD<br />
<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> Processor Design Guide 3-1
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