Intel PXA250 and PXA210 Applications Processors

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System Memory Interface data has been latched, the address may change on the next rising edge of MEMCLK or any cycles thereafter. The nOE or nPWE signal de-asserts one MEMCLK after data is latched. Before a subsequent data beat, nOE or nPWE remains deasserted for RDN+1 memory cycles. The chip select and byte selects, DQM[3:0], remain asserted for one memory cycle after the burst’s final nOE or nPWE deassertion. Refer to Figure 2-3 for 32-Bit Variable Latency I/O read timing and Figure 2-8 for Variable Latency I/O Interface AC Specifications Figure 2-3. 32-Bit Variable Latency I/O Read Timing (Burst-of-Four, One Wait Cycle Per Beat) 0ns 100ns 200ns 300ns memlk nCS[0] MA[25:2] MA[1:0] tAS 0 1 2 3 "00" nOE tASRW0 tCES tAH RDN+1 tASWN RDF+1+Waits tCEH RRR+1 nPWE RDnWR RDY MD[31:0] DQM[3:0] "0000" nCS[1] A8867-01 Table 2-8. Variable Latency I/O Interface AC Specifications (Sheet 1 of 2) Symbol Description MEMCKLK 99.5 118.0 132.7 147.5 165.9 Units Notes Variable Latency IO Interface (VLIO) (Asynchronous) tvlioAS MA(25:0) setup to nCS asserted 10 8.5 7.5 6.8 6 ns, 1 tvlioASRW MA(25:0) setup to nOE or nPWE asserted 10 8.5 7.5 6.8 6 ns, 1 tvlioAH MA(25:0) hold after nOE or nPWE deasserted 10 8.5 7.5 6.8 6 ns, 1 tvlioCES nCS setup to nOE or nPWE asserted 20 17 15 13.6 12 ns, 2 tvlioCEH nCS hold after nOE or nPWE deasserted 10 8.5 7.5 6.8 6 ns, 1 2-10 PXA250 and PXA210 Applications Processors Design Guide
System Memory Interface Table 2-8. Variable Latency I/O Interface AC Specifications (Sheet 2 of 2) Symbol Description MEMCKLK 99.5 118.0 132.7 147.5 165.9 Units Notes tvlioDSW tvlioDSWH tvlioDHW tvlioDHR tvlioRDYH MD(31:0), DQM(3:0) write data setup to nPWE asserted MD(31:0), DQM(3:0) write data setup to nPWE de-asserted MD(31:0), DQM(3:0) hold after nPWE de-asserted MD(31:0) read data hold after nOE deasserted RDY hold after nOE, nPWE deasserted nPWE, nOE high time between beats of tvlioNPWE write or read data NOTES: 1. This number represents 1 MEMCLK period 2. This number represents 2 MEMCLK periods 10 8.5 7.5 6.8 6 ns, 1 20 17 15 13.6 12 ns, 2 10 8.5 7.5 6.8 6 ns, 1 0 0 0 0 0 ns 0 0 0 0 0 ns 20 17 15 13.6 12 ns, 2 2.6.5 External Logic for PCMCIA Implementation The PXA250 applications processor requires external glue logic to complete the PCMCIA socket interface. Figure 2-4, “Expansion Card External Logic for a Two-Socket Configuration” on page 2- 12 and Figure 2-5, “Expansion Card External Logic for a One-Socket Configuration” on page 2-13 show general solutions for one and two socket configurations. Use GPIO or memory-mapped external registers to control the PCMCIA interface’s reset, power selection (V CC and V PP ), and drive enables. These diagrams show the logical connections necessary to support hot insertion capability. For dual-voltage support, level shifting buffers are required for all the applications processor input signals. Hot insertion capability requires each socket be electrically isolated from the other and from the remainder of the memory system. If one or both of these features are not required, you may eliminate some of the logic shown in these diagrams. The applications processor allows either 1-socket or 2-socket solutions. In the 1-socket solution, only minimal glue logic is required (typically for the data transceivers, address buffers, and level shifting buffers.) To achieve this some of the signals are routed through dual-duty GPIO pins. The nOE of the transceivers is driven through the PSKTSEL pin, which is not needed in the one-socket solution. The DIR pin of the transceiver is driven through the RDnWR pin. A GPIO is used for the three-state signal of the address and nPWE lines. These signals are used for memories other than the card interface and must be three-stated. Note: Note: For 2.5 V VCCN, 5 V to 2.5 V level shifters are required. PCMCIA is only implemented on the PXA250 applications processor. In the 2-socket solution, all pins assume their normal duties and glue logic is necessary for proper operation of the system. The pull-ups shown are included for compliance with PC Card Standard - Volume 2 - Electrical Specification. Remove power from these pull-ups during sleep to avoid unnecessary power consumption. Refer to Table 2-9 for the PCMCIA or compact Flash card interface AC specifications. PXA250 and PXA210 Applications Processors Design Guide 2-11
Page 1 and 2: Intel ® PXA250 and PXA210 Applicat
Page 3 and 4: Contents Contents 1 Introduction...
Page 5 and 6: Contents A.1 SA-1110 Hardware Migra
Page 7 and 8: Contents 2-7 SRAM / ROM / Flash / S
Page 9 and 10: Introduction 1 Table 1-1. Revision
Page 11 and 12: Introduction • System memory inte
Page 13 and 14: Introduction Table 1-3. Signal Pin
Page 19 and 20: Introduction Figure 1-2. PXA250 App
Page 21 and 22: Introduction Table 1-4. PXA250 Appl
Page 23 and 24: Introduction Figure 1-3. PXA210 App
Page 25 and 26: Introduction Table 1-5. PXA210 Appl
Page 27 and 28: System Memory Interface 2 This sect
Page 29 and 30: System Memory Interface Table 2-1.
Page 31 and 32: . System Memory Interface 2.4 SDRAM
Page 33 and 34: System Memory Interface Table 2-4.
Page 35: System Memory Interface Table 2-6.
Page 39 and 40: System Memory Interface Figure 2-5.
Page 41 and 42: System Memory Interface Figure 2-6.
Page 43 and 44: System Memory Interface 2.7 System
Page 45 and 46: LCD Display Controller 3 This chapt
Page 47 and 48: LCD Display Controller Figure 3-1.
Page 49 and 50: LCD Display Controller Figure 3-5.
Page 51 and 52: LCD Display Controller Note: This e
Page 53 and 54: LCD Display Controller However, typ
Page 55 and 56: USB Interface 4 4.1 Self Powered De
Page 57 and 58: MultiMediaCard (MMC) 5 The MultiMed
Page 59 and 60: MultiMediaCard (MMC) Figure 5-1. Ap
Page 61 and 62: MultiMediaCard (MMC) Warning: Conne
Page 63 and 64: AC97 6 The AC97 controller unit (AC
Page 65 and 66: I 2 C 7 The Inter-Integrated Circui
Page 67 and 68: . I2C Figure 7-2. Using an Analog S
Page 69 and 70: Power and Clocking 8 8.1 Operating
Page 71 and 72: Power and Clocking Since few system
Page 73 and 74: Power and Clocking Table 8-4. 32.76
Page 75 and 76: Power and Clocking Table 8-6. PXA25
Page 81 and 82: Power and Clocking Figure 8-2. Hard
Page 83 and 84: Power and Clocking Table 8-10. Slee
Page 85 and 86: Power and Clocking Table 8-14. Sync
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Power and Clocking Table 8-16. Vari
Page 89 and 90:
Power and Clocking • Provide powe
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Power and Clocking 8.7.4 I/O 3.3 V
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JTAG/Debug Port 9 9.1 Description T
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SA-1110/Applications Processor Migr
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Example Form Factor Reference Desig
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8 1 7 6 5 4 3 2 Copyright 2002 Inte
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8 IN_PWR {10,15} D10 1 Pg. 12 7 6 5
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8 C C 1 7 6 5 4 3 2 Copyright 2002
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8 B B A A PXA250 Processor Referenc
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BBPXA2xx Development Baseboard Sche
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BBPXA2xx Development Baseboard Sche
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DCPXA250 Processor Card 32-bit vers
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DCPXA210 Processor Card 4 CONNECTOR
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Intel PXA250 and PXA210 Applications Processors

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