Intel PXA250 and PXA210 Applications Processors
Intel PXA250 and PXA210 Applications Processors Intel PXA250 and PXA210 Applications Processors
System Memory Interface Figure 2-1. General Memory Interface Configuration nSDCS nSDCS SDCLK, SDCKE nSDCS nSDCS SDCLK, SDCKE SDRAM Partition 0 SDRAM Partition 1 SDRAM Partition 2 SDRAM Partition 3 SDRAM Memory Interface Up to 4 partitions of SDRAM memory (16- or 32-bit wide) DQM nSDRAS, nSDCAS PXA250 Memory Controller Interface MD MA Card Control Buffers and Transceivers Card Memory Interface Up to 2-socket support. Requires some external buffering. nCS nCS nCS SDCLK, SDCKE Static Bank 0 Static Bank 1 Static Bank 2 Static Memory or Variable Latency I/O Interface Up to 6 banks of ROM, Flash, SRAM, Variable Latency I/O, (16- or 32-bit wide) NOTE: Static Bank 0 must be populated by “bootable” memory nCS nCS nCS RDY Static Bank 3 Static Bank 4 Static Bank 5 Synchronous Static Memory Interface Up to 4 banks of synchronous static memory (nCS). (16- or 32-bit wide) NOTE: Static Bank 0 must be populated by “bootable” memory 2-2 PXA250 and PXA210 Applications Processors Design Guide
System Memory Interface Table 2-1. Memory Address Map 0x6000 0000 Reserved Address Space 0x5C00 0000 Reserved Address Space 0x5800 0000 Reserved Address Space 0x5400 0000 Reserved Address Space 0x5000 0000 Reserved Address Space 0x4C00 0000 Reserved Address Space 0x4800 0000 Memory Mapped Registers (Memory Ctl) 0x4400 0000 Memory Mapped Registers (LCD) 0x4000 0000 Memory Mapped Registers (Peripherals) 0x3000 0000 PCMCIA/CF – Slot 1 0x2000 0000 PCMCIA/CF – Slot 0 0x1C00 0000 Reserved Address Space 0x1800 0000 Reserved Address Space 0x1400 0000 Static Chip Select 5 0x1000 0000 Static Chip Select 4 0x0C00 0000 Static Chip Select 3 0x0800 0000 Static Chip Select 2 0x0400 0000 Static Chip Select 1 0x0000 0000 Static Chip Select 0 2.2 SDRAM Interface The applications processor supports an SDRAM interface at a maximum frequency of 100 MHz. The SDRAM Interface supports four 16-bit or 32-bit wide partitions of SDRAM. Each partition is allocated 64 MBytes of the internal memory map. However, the actual size of each partition is dependent on the particular SDRAM configuration used. The four partitions are divided into two partition pairs: the 0/1 pair and the 2/3 pair. Both partitions within a pair (for example, partition 0 and partition 1) must be identical in size and configuration; however, the two pairs can be different. For example, the 0/1 pair can be 100 MHz SDRAM on a 32-bit data bus, while the 2/3 pair can be 50 MHz SDRAM on a 16-bit data bus. Note: For proper SDRAM operation above 50 MHz, 22 ohm series resistors must be placed on the memory address lines. 2.3 SDRAM memory wiring diagram Figure 2-2, “SDRAM Memory System Example” on page 2-4 is a wiring diagram example that shows a system using 1Mword x 16-bit x 4-bank SDRAM devices for a total of 48 Mbytes. Refer to Section 2.5, “SDRAM Address Mapping” on page 2-6 to determine the individual SDRAM component address. PXA250 and PXA210 Applications Processors Design Guide 2-3
- Page 1 and 2: Intel ® PXA250 and PXA210 Applicat
- Page 3 and 4: Contents Contents 1 Introduction...
- Page 5 and 6: Contents A.1 SA-1110 Hardware Migra
- Page 7 and 8: Contents 2-7 SRAM / ROM / Flash / S
- Page 9 and 10: Introduction 1 Table 1-1. Revision
- Page 11 and 12: Introduction • System memory inte
- Page 13 and 14: Introduction Table 1-3. Signal Pin
- Page 15 and 16: Introduction Table 1-3. Signal Pin
- Page 17 and 18: Introduction Table 1-3. Signal Pin
- Page 19 and 20: Introduction Figure 1-2. PXA250 App
- Page 21 and 22: Introduction Table 1-4. PXA250 Appl
- Page 23 and 24: Introduction Figure 1-3. PXA210 App
- Page 25 and 26: Introduction Table 1-5. PXA210 Appl
- Page 27: System Memory Interface 2 This sect
- Page 31 and 32: . System Memory Interface 2.4 SDRAM
- Page 33 and 34: System Memory Interface Table 2-4.
- Page 35 and 36: System Memory Interface Table 2-6.
- Page 37 and 38: System Memory Interface Table 2-8.
- Page 39 and 40: System Memory Interface Figure 2-5.
- Page 41 and 42: System Memory Interface Figure 2-6.
- Page 43 and 44: System Memory Interface 2.7 System
- Page 45 and 46: LCD Display Controller 3 This chapt
- Page 47 and 48: LCD Display Controller Figure 3-1.
- Page 49 and 50: LCD Display Controller Figure 3-5.
- Page 51 and 52: LCD Display Controller Note: This e
- Page 53 and 54: LCD Display Controller However, typ
- Page 55 and 56: USB Interface 4 4.1 Self Powered De
- Page 57 and 58: MultiMediaCard (MMC) 5 The MultiMed
- Page 59 and 60: MultiMediaCard (MMC) Figure 5-1. Ap
- Page 61 and 62: MultiMediaCard (MMC) Warning: Conne
- Page 63 and 64: AC97 6 The AC97 controller unit (AC
- Page 65 and 66: I 2 C 7 The Inter-Integrated Circui
- Page 67 and 68: . I2C Figure 7-2. Using an Analog S
- Page 69 and 70: Power and Clocking 8 8.1 Operating
- Page 71 and 72: Power and Clocking Since few system
- Page 73 and 74: Power and Clocking Table 8-4. 32.76
- Page 75 and 76: Power and Clocking Table 8-6. PXA25
- Page 77 and 78: Power and Clocking Table 8-6. PXA25
System Memory Interface<br />
Table 2-1. Memory Address Map<br />
0x6000 0000 Reserved Address Space<br />
0x5C00 0000 Reserved Address Space<br />
0x5800 0000 Reserved Address Space<br />
0x5400 0000 Reserved Address Space<br />
0x5000 0000 Reserved Address Space<br />
0x4C00 0000 Reserved Address Space<br />
0x4800 0000 Memory Mapped Registers (Memory Ctl)<br />
0x4400 0000 Memory Mapped Registers (LCD)<br />
0x4000 0000 Memory Mapped Registers (Peripherals)<br />
0x3000 0000 PCMCIA/CF – Slot 1<br />
0x2000 0000 PCMCIA/CF – Slot 0<br />
0x1C00 0000 Reserved Address Space<br />
0x1800 0000 Reserved Address Space<br />
0x1400 0000 Static Chip Select 5<br />
0x1000 0000 Static Chip Select 4<br />
0x0C00 0000 Static Chip Select 3<br />
0x0800 0000 Static Chip Select 2<br />
0x0400 0000 Static Chip Select 1<br />
0x0000 0000 Static Chip Select 0<br />
2.2 SDRAM Interface<br />
The applications processor supports an SDRAM interface at a maximum frequency of 100 MHz.<br />
The SDRAM Interface supports four 16-bit or 32-bit wide partitions of SDRAM. Each partition is<br />
allocated 64 MBytes of the internal memory map. However, the actual size of each partition is<br />
dependent on the particular SDRAM configuration used. The four partitions are divided into two<br />
partition pairs: the 0/1 pair <strong>and</strong> the 2/3 pair. Both partitions within a pair (for example, partition 0<br />
<strong>and</strong> partition 1) must be identical in size <strong>and</strong> configuration; however, the two pairs can be different.<br />
For example, the 0/1 pair can be 100 MHz SDRAM on a 32-bit data bus, while the 2/3 pair can be<br />
50 MHz SDRAM on a 16-bit data bus.<br />
Note:<br />
For proper SDRAM operation above 50 MHz, 22 ohm series resistors must be placed on the<br />
memory address lines.<br />
2.3 SDRAM memory wiring diagram<br />
Figure 2-2, “SDRAM Memory System Example” on page 2-4 is a wiring diagram example that<br />
shows a system using 1Mword x 16-bit x 4-bank SDRAM devices for a total of 48 Mbytes. Refer<br />
to Section 2.5, “SDRAM Address Mapping” on page 2-6 to determine the individual SDRAM<br />
component address.<br />
<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide 2-3
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