Intel PXA250 and PXA210 Applications Processors
Intel PXA250 and PXA210 Applications Processors
Intel PXA250 and PXA210 Applications Processors
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System Memory Interface 2<br />
This section is the design guidelines for the system memory interface.<br />
2.1 Overview<br />
The external memory bus interface for the applications processor supports:<br />
• 100 MHz SDRAM at 3.3 V<br />
• 100 MHz SDRAM at 2.5 V<br />
• Synchronous <strong>and</strong> asynchronous Burst mode <strong>and</strong> Page mode Flash<br />
• Synchronous Mask ROM (SMROM)<br />
• Page Mode ROM<br />
• SRAM<br />
• SRAM-like Variable Latency I/O (VLIO)<br />
• PCMCIA expansion memory<br />
• Compact Flash<br />
Use the memory interface configuration registers to program the memory types. Refer to<br />
Figure 1-1, “<strong>Applications</strong> Processor Block Diagram” on page 1-2 for the block diagram of the<br />
Memory Controller configuration. Refer to Figure 2-1, “Memory Address Map” on page 2-3 for<br />
the applications processor memory map. Refer to Table 2-3, “Normal Mode Memory Address<br />
Mapping” on page 2-6 for alternate mode address mapping.<br />
<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide 2-1