Intel PXA250 and PXA210 Applications Processors

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Information in this document is provided in connection with Intel ® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The PXA250 and PXA210 applications processors may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. MPEG is an international standard for video compression/decompression promoted by ISO. Implementations of MPEG CODECs, or MPEG enabled platforms may require licenses from various entities, including Intel Corporation. This document and the software described in it are furnished under license and may only be used or copied in accordance with the terms of the license. The information in this document is furnished for informational use only, is subject to change without notice, and should not be construed as a commitment by Intel Corporation. Intel Corporation assumes no responsibility or liability for any errors or inaccuracies that may appear in this document or any software that may be provided in association with this document. Except as permitted by such license, no part of this document may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. Copyright © Intel Corporation, 2002 AlertVIEW, i960, AnyPoint, AppChoice, BoardWatch, BunnyPeople, CablePort, Celeron, Chips, Commerce Cart, CT Connect, CT Media, Dialogic, DM3, EtherExpress, ETOX, FlashFile, GatherRound, i386, i486, iCat, iCOMP, Insight960, InstantIP, Intel, Intel logo, Intel386, Intel486, Intel740, IntelDX2, IntelDX4, IntelSX2, Intel ChatPad, Intel Create&Share, Intel Dot.Station, Intel GigaBlade, Intel InBusiness, Intel Inside, Intel Inside logo, Intel NetBurst, Intel NetStructure, Intel Play, Intel Play logo, Intel Pocket Concert, Intel SingleDriver, Intel SpeedStep, Intel StrataFlash, Intel TeamStation, Intel WebOutfitter, Intel Xeon, Intel XScale, Itanium, JobAnalyst, LANDesk, LanRover, MCS, MMX, MMX logo, NetPort, NetportExpress, Optimizer logo, OverDrive, Paragon, PC Dads, PC Parents, Pentium, Pentium II Xeon, Pentium III Xeon, Performance at Your Command, ProShare, RemoteExpress, Screamline, Shiva, SmartDie, Solutions960, Sound Mark, StorageExpress, The Computer Inside, The Journey Inside, This Way In, TokenExpress, Trillium, Vivonic, and VTune are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. ii PXA250 and PXA210 Applications Processors Design Guide
Contents Contents 1 Introduction.................................................................................................................................1-1 1.1 Functional Overview ..........................................................................................................1-1 1.2 Package Information..........................................................................................................1-2 1.2.1 Package Introduction ............................................................................................1-2 1.2.2 Signal Pin Descriptions.........................................................................................1-4 2 System Memory Interface ..........................................................................................................2-1 2.1 Overview............................................................................................................................2-1 2.2 SDRAM Interface...............................................................................................................2-3 2.3 SDRAM memory wiring diagram .......................................................................................2-3 2.4 SDRAM Support ................................................................................................................2-5 2.5 SDRAM Address Mapping.................................................................................................2-6 2.6 Static Memory....................................................................................................................2-7 2.6.1 Overview...............................................................................................................2-7 2.6.2 Boot Time Defaults ...............................................................................................2-8 2.6.3 SRAM / ROM / Flash / Synchronous Fast Flash Memory Options .......................2-9 2.6.4 Variable Latency I/O Interface Overview ..............................................................2-9 2.6.5 External Logic for PCMCIA Implementation .......................................................2-11 2.6.6 DMA / Companion Chip Interface .......................................................................2-14 2.7 System Memory Layout Guidelines .................................................................................2-17 2.7.1 System Memory Topologies (Min and Max Simulated Loading).........................2-17 2.7.2 System Memory Recommended Trace Lengths.................................................2-18 3 LCD Display Controller ..............................................................................................................3-1 3.1 LCD Display Overview.......................................................................................................3-1 3.2 Passive (DSTN) Displays ..................................................................................................3-1 3.2.1 Typical Connections for Passive Panel Displays..................................................3-2 3.2.1.1 Passive Monochrome Single Panel Displays........................................3-2 3.2.1.2 Passive Monochrome Single Panel Displays, Double-Pixel Data.........3-3 3.2.1.3 Passive Monochrome Dual Panel Displays ..........................................3-3 3.2.1.4 Passive Color Single Panel Displays ....................................................3-4 3.2.1.5 Passive Color Dual Panel Displays.......................................................3-4 3.3 Active (TFT) Displays ........................................................................................................3-5 3.3.1 Typical connections for Active Panel Displays......................................................3-6 3.4 PXA250 Pinout ..................................................................................................................3-7 3.5 Additional Design Considerations......................................................................................3-8 3.5.1 Contrast Voltage ...................................................................................................3-8 3.5.2 Backlight Inverter ..................................................................................................3-8 3.5.3 Signal Routing and Buffering ................................................................................3-8 3.5.4 Panel Connector ...................................................................................................3-9 4 USB Interface ..............................................................................................................................4-1 4.1 Self Powered Device .........................................................................................................4-1 4.1.1 Operation if GPIOn and GPIOx are Different Pins................................................4-1 4.1.2 Operation if GPIOn and GPIOx are the Same Pin................................................4-2 4.2 Bus Powered Device .........................................................................................................4-2 PXA250 and PXA210 Applications Processors Design Guide iii
Page 1: Intel ® PXA250 and PXA210 Applicat
Page 5 and 6: Contents A.1 SA-1110 Hardware Migra
Page 7 and 8: Contents 2-7 SRAM / ROM / Flash / S
Page 9 and 10: Introduction 1 Table 1-1. Revision
Page 11 and 12: Introduction • System memory inte
Page 13 and 14: Introduction Table 1-3. Signal Pin
Page 19 and 20: Introduction Figure 1-2. PXA250 App
Page 21 and 22: Introduction Table 1-4. PXA250 Appl
Page 23 and 24: Introduction Figure 1-3. PXA210 App
Page 25 and 26: Introduction Table 1-5. PXA210 Appl
Page 27 and 28: System Memory Interface 2 This sect
Page 29 and 30: System Memory Interface Table 2-1.
Page 31 and 32: . System Memory Interface 2.4 SDRAM
Page 39 and 40: System Memory Interface Figure 2-5.
Page 41 and 42: System Memory Interface Figure 2-6.
Page 43 and 44: System Memory Interface 2.7 System
Page 45 and 46: LCD Display Controller 3 This chapt
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LCD Display Controller However, typ
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USB Interface 4 4.1 Self Powered De
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MultiMediaCard (MMC) 5 The MultiMed
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MultiMediaCard (MMC) Figure 5-1. Ap
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MultiMediaCard (MMC) Warning: Conne
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AC97 6 The AC97 controller unit (AC
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I 2 C 7 The Inter-Integrated Circui
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. I2C Figure 7-2. Using an Analog S
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Power and Clocking 8 8.1 Operating
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Power and Clocking Since few system
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Power and Clocking Table 8-4. 32.76
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Power and Clocking Table 8-6. PXA25
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Power and Clocking Figure 8-2. Hard
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Power and Clocking Table 8-10. Slee
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Power and Clocking Table 8-14. Sync
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Power and Clocking Table 8-16. Vari
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Power and Clocking • Provide powe
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Power and Clocking 8.7.4 I/O 3.3 V
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JTAG/Debug Port 9 9.1 Description T
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SA-1110/Applications Processor Migr
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Example Form Factor Reference Desig
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8 C C 1 7 6 5 4 3 2 Copyright 2002
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8 B B A A PXA250 Processor Referenc
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BBPXA2xx Development Baseboard Sche
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BBPXA2xx Development Baseboard Sche
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DCPXA250 Processor Card 32-bit vers
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DCPXA210 Processor Card 4 CONNECTOR
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Intel PXA250 and PXA210 Applications Processors

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