Intel PXA250 and PXA210 Applications Processors

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Introduction Table 1-3. Signal Pin Descriptions (Sheet 3 of 7) Name Type Description nPREG/ GPIO[55] LCD Controller Pins L_DD(15:0)/ GPIO[73:58] L_FCLK/ GPIO[74] L_LCLK/ GPIO[75] L_PCLK/ GPIO[76] L_BIAS/ GPIO[77] ICOCZ ICOCZ ICOCZ ICOCZ ICOCZ ICOCZ PCMCIA register select. Output signal that indicates the target address is attribute space, on a memory transaction. This signal has the same timing as address. See Note [2] LCD Controller display data See Note [2] LCD Frame clock See Note [2] LCD Line clock See Note [2] LCD pixel clock See Note [2] AC Bias Drive See Note [2] Full Function UART Pins FFRXD/ GPIO[34] FFTXD/ GPIO[39] FFCTS/ GPIO[35] FFDCD/ GPIO[36] FFDSR/ GPIO[37] FFRI/ GPIO[38] FFDTR/ GPIO[40] FFRTS/ GPIO[41] Bluetooth UART Pins BTRXD/ GPIO[42] BTTXD/ GPIO[43] BTCTS/ GPIO[44] BTRTS/ GPIO[45] MMC Controller Pins ICOCZ ICOCZ ICOCZ ICOCZ ICOCZ ICOCZ ICOCZ ICOCZ ICOCZ ICOCZ ICOCZ ICOCZ Full Function UART Receive pin See Note [2] Full Function UART Transmit pin See Note [2] Full Function UART Clear-to-Send pin See Note [2] Full Function UART Data-Carrier-Detect Pin See Note [2] Full Function UART Data-Set-Ready Pin: See Note [2] Full Function UART Ring Indicator Pin See Note [2] Full Function UART Data-Terminal-Ready pin See Note [2] Full Function UART Ready-to-Send pin See Note [2] Bluetooth UART Receive pin See Note [2] Bluetooth UART Transmit pin See Note [2] Bluetooth UART Clear-to-Send pin See Note [2] Bluetooth UART Data-Terminal-Ready pin See Note [2] MMCMD ICOCZ Multimedia Card Command pin (I/O) 1-6 PXA250 and PXA210 Applications Processors Design Guide
Introduction Table 1-3. Signal Pin Descriptions (Sheet 4 of 7) Name Type Description MMDAT ICOCZ Multimedia Card Data Pin (I/O) MMCCLK/GP[6] ICOCZ MMC clock. (output) Clock signal for the MMC Controller. MMCCS0/GP[8] ICOCZ MMC chip select 0. (output) Chip select 0 for the MMC Controller. MMCCS1/GP[9] ICOCZ MMC chip select 1. (output) Chip select 1 for the MMC Controller. SSP Pins SSPSCLK/ GPIO[23] SSPSFRM/ GPIO[24] SSPTXD/ GPIO[25] SSPRXD/ GPIO[26] SSPEXTCLK/ GPIO[27] USB Client Pins ICOCZ ICOCZ ICOCZ ICOCZ ICOCZ Synchronous Serial Port Clock (output) See Note [2] Synchronous serial port Frame Signal (output) See Note [2] Synchronous serial port transmit (output) See Note [2] Synchronous serial port receive (input) See Note [2] Synchronous Serial port external clock (input) See Note [2] USB_P IAOA USB Client port positive Pin of differential pair. USB_N IAOA USB Client port negative Pin of differential pair. AC97 Controller Pins BITCLK/ GPIO[28] SDATA_IN0/ GPIO[29] SDATA_IN1/ GPIO[32] SDATA_OUT/ GPIO[30] SYNC/ GPIO[31] nACRESET ICOCZ ICOCZ ICOCZ ICOCZ ICOCZ OC AC97 Audio Port bit clock (output) See Note [2] AC97 Audio Port data in (input) See Note [2] AC97 Audio Port data in (input) See Note [2] AC97 Audio Port data out (output) See Note [2] AC97 Audio Port sync signal (output) See Note [2] AC97 Audio Port reset signal (output) This pin is a dedicated output. Standard UART and ICP Pins IRRXD/ GPIO[46] IRTXD/ GPIO[47] I 2 C Controller Pins SCL ICOCZ ICOCZ ICOCZ IrDA Receive signal (input). See Note [2] IrDA Transmit signal (output). Transmit pin for both the SIR and FIR functions. See Note [2] I2C clock (Bidirectional) Bidirectional signal. When it is driving, it functions as an open collector device and requires a pull up resistor. As an input, it expects standard CMOS levels. PXA250 and PXA210 Applications Processors Design Guide 1-7
Page 1 and 2: Intel ® PXA250 and PXA210 Applicat
Page 3 and 4: Contents Contents 1 Introduction...
Page 5 and 6: Contents A.1 SA-1110 Hardware Migra
Page 7 and 8: Contents 2-7 SRAM / ROM / Flash / S
Page 9 and 10: Introduction 1 Table 1-1. Revision
Page 11 and 12: Introduction • System memory inte
Page 13: Introduction Table 1-3. Signal Pin
Page 17 and 18: Introduction Table 1-3. Signal Pin
Page 19 and 20: Introduction Figure 1-2. PXA250 App
Page 21 and 22: Introduction Table 1-4. PXA250 Appl
Page 23 and 24: Introduction Figure 1-3. PXA210 App
Page 25 and 26: Introduction Table 1-5. PXA210 Appl
Page 27 and 28: System Memory Interface 2 This sect
Page 29 and 30: System Memory Interface Table 2-1.
Page 31 and 32: . System Memory Interface 2.4 SDRAM
Page 39 and 40: System Memory Interface Figure 2-5.
Page 41 and 42: System Memory Interface Figure 2-6.
Page 43 and 44: System Memory Interface 2.7 System
Page 45 and 46: LCD Display Controller 3 This chapt
Page 47 and 48: LCD Display Controller Figure 3-1.
Page 49 and 50: LCD Display Controller Figure 3-5.
Page 51 and 52: LCD Display Controller Note: This e
Page 53 and 54: LCD Display Controller However, typ
Page 55 and 56: USB Interface 4 4.1 Self Powered De
Page 57 and 58: MultiMediaCard (MMC) 5 The MultiMed
Page 59 and 60: MultiMediaCard (MMC) Figure 5-1. Ap
Page 61 and 62: MultiMediaCard (MMC) Warning: Conne
Page 63 and 64: AC97 6 The AC97 controller unit (AC
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I 2 C 7 The Inter-Integrated Circui
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. I2C Figure 7-2. Using an Analog S
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Power and Clocking 8 8.1 Operating
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Power and Clocking Since few system
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Power and Clocking Table 8-4. 32.76
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Power and Clocking Table 8-6. PXA25
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Power and Clocking Figure 8-2. Hard
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Power and Clocking Table 8-10. Slee
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Power and Clocking Table 8-14. Sync
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Power and Clocking Table 8-16. Vari
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Power and Clocking • Provide powe
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Power and Clocking 8.7.4 I/O 3.3 V
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JTAG/Debug Port 9 9.1 Description T
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SA-1110/Applications Processor Migr
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Example Form Factor Reference Desig
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8 1 7 6 5 4 3 2 Copyright 2002 Inte
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8 1 Sheet 4 of 16 1 7 6 5 4 3 2 Cop
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8 IN_PWR {10,15} D10 1 Pg. 12 7 6 5
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8 C C 1 7 6 5 4 3 2 Copyright 2002
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8 B B A A PXA250 Processor Referenc
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BBPXA2xx Development Baseboard Sche
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BBPXA2xx Development Baseboard Sche
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DCPXA250 Processor Card 32-bit vers
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DCPXA210 Processor Card 4 CONNECTOR
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Intel PXA250 and PXA210 Applications Processors

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