Intel PXA250 and PXA210 Applications Processors

8
1
7
6
5
4
3
2
Copyright 2002 Intel Corporation
J15
RCPT AMP
J16
RCPT AMP
2
1
2
1
Pg. 15
4
{6,10} VX_A0
C1
3
VX_A1 {6,10}
4
{6,10} VX_A0
C1
3
VX_A1
C2
C1
C2
C1
{6,10}
6
{6,10} VX_A2
C2
5
VX_A3 {6,10}
6
VX_A5 {7,10}
{6,10} VX_A2
C2
5
VX_A3
8
7
8
7
{6,10}
{7,10} VX_A4
{7,10} VX_A4
VX_A5
10
{7,10}
{7,10} VX_A6
C3
9
VX_A7 {7,10}
10
{7,10} VX_A6
C3
9
VX_A7
C4
C3
C4
C3
{7,10}
12
{7,10} VX_A8
C4
11
VX_A9 {7,10}
12
VX_A11 {7}
{7,10} VX_A8
C4
11
VX_A9
14
13
14
13
{7,10}
{7,10} VX_A10
D {7} VX_A12
VX_A13 {7}
{7,10} VX_A10
VX_A11
16
15
16
15
{7}
VX_A13 D
DC3P3V
{7} VX_A12
18
17
{7} VX_A14
VX_A15 {7}
DC3P3V
18
17
{7}
VX_A15 {7} DC3P3V
{7} VX_A16
VX_A17 {7}
{7} VX_A14
20
19
DC3P3V
20
19
VX_A19 {7}
{7} VX_A16
VX_A17
22
21
22
21
{7}
{7} VX_A18
{7} VX_A20
VX_A21 {7}
{7} VX_A18
VX_A19
24
{7}
C5
23
24
{7} VX_A20
C5
23
VX_A21
C6
C5
C6
C5
{7}
26
{7} VX_A22
C6
25
VX_A23 {7}
26
{7} VX_A24
VX_A25 {7}
{7} VX_A22
C6
25
VX_A23
28
27
28
27
{7}
{7} VX_A24
VX_A25
30
{7}
C7
29
30
C7
29
C8
C7
C8
C7
{7} VX_nSDCS_0
32
C8
31
VX_nSDCS_2 {6}
{7} VX_nSDCS_0
32
C8
31
VX_nSDCS_2
{7}
34
33
VX_nSDCAS
VX_DQM_3 {7}
34
33
{6}
{7} VX_nSDCAS
VX_DQM_3 {7} VX_nSDRAS 36
35
VX_DQM_2 {7}
36
35
{7}
VX_DQM_1 {7}
{7} VX_nSDRAS
VX_DQM_2
38
37
38
37
{7}
{3} BOOT_SEL_0
{2} SA_SDCKE_0
VX_DQM_0 {7}
{3} BOOT_SEL_0
VX_DQM_1
40
39
40
39
{7}
{2} SA_SDCKE_0
VX_DQM_0 {7}
{3} BOOT_SEL_1
42
41
{3} BOOT_SEL_1
42
41
{6} VX_SDCKE_1
44
C9
43
SA_SDCLK_0 {2,5}
{6} VX_SDCKE_1
44
C9
43
SA_SDCLK_0
C10
C9
C10
C9
{2,5}
46
C10
45
46
C10
45
48
47
{7} VX_SDCLK_1
VX_SDCLK_2 {6}
48
47
{7} VX_SDCLK_1
VX_SDCLK_2
50
{6}
C11
49
50
C11
49
C12
C11
C12
C11
{2,6} SA_RD_nWR
52
C12
51
MBREQ_CF_DETECT {3,13}
{2,6} SA_RD_nWR
52
C12
51
MBREQ_CF_DETECT {3,13}
{4,13}
54
53
nGFX_PRESENT
MBGNT_CF_IRQ {3,6}
{4,13}
54
53
nGFX_PRESENT
MBGNT_CF_IRQ {3,6}
C 56
55
{6,10} CF_IRQ_LVL2OE
DREQ_1 {11}
56
55
C
nJTAG_TRST
VX_D1 {7,10}
{6,10} CF_IRQ_LVL2OE
DREQ_1
58
57
58
57
{11}
VX_D1
LCD_DC5V
nJTAG_TRST
60
59
{7,10}
{7,10} VX_D0
VX_D3 {7,10} LCD_DC5V
60
59
{7,10} VX_D2
VX_D5 {7,10}
{7,10} VX_D0
VX_D3 {7,10} LCD_DC5V
62
61
{7,10} VX_D2
62
61
VX_D5
{7,10} VX_D4
64
{7,10}
C13
63
VX_D7 {7,10}
{7,10} VX_D4
64
C13
63
VX_D7
C14
C13
LCD_DC5V
C14
C13
{7,10}
{7,10} VX_D6
66
C14
65
VX_D9 {7,10}
{7,10} VX_D6
66
C14
65
VX_D9
68
67
{7,10}
{7,10} VX_D8
VX_D11 {7,10}
68
67
VX_D11 {7,10} DC3P3V
{7,10} VX_D10
VX_D13 {7,10}
{7,10} VX_D8
70
DC3P3V
C15
69
70
{7,10} VX_D10
C15
69
VX_D13
C16
C15
C16
C15
{7,10}
72
{7,10} VX_D12
C16
71
VX_D15 {7,10}
72
{7,10} VX_D12
C16
71
VX_D15 {7,10}
{7,10} VX_D14
74
73
{7,10} VX_D14
74
73
76
75
{7} VX_D16
VX_D17 {7}
76
75
{7} VX_D18
VX_D19 {7}
{7} VX_D16
VX_D17
78
77
78
77
{7}
VX_D19 {7}
{7} VX_D20
VX_D21 {7}
{7} VX_D18
80
79
80
79
VX_D21 {7}
{7} VX_D22
VX_D23 {7}
{7} VX_D20
82
81
82
81
VX_D23 {7}
{7} VX_D24
VX_D25 {7}
{7} VX_D22
84
C17
83
{7} VX_D24
84
C17
83
VX_D25
C18
C17
C18
C17
{7}
86
{7} VX_D26
C18
85
VX_D27 {7}
{7}
86
{7} VX_D28
VX_D29 {7}
VX_D26
C18
85
VX_D27
88
87
88
87
{7}
{7} VX_D30
VX_D31 {7}
{7} VX_D28
VX_D29
90
{7}
C19
89
90
{7} VX_D30
C19
89
VX_D31
C20
C19
C20
C19
{7}
{4,13} nNEP_PRESENT
92
C20
91
IN_PWR {10,12}
{4,13} nNEP_PRESENT
92
C20
91
IN_PWR
94
93
{10,12}
{2} SA_RDY
SA_nCS_5 {2,6} DC3P3V
94
93
SA_nCS_5 {2,6}
B B
{7} VX_nWE
SA_nCS_4 {2,6}
{7} {2}
VX_nWE
SA_RDY
96
95
96
95
SA_nCS_4
DC3P3V
{2,6}
{6,7} VX_nOE
98
97
SA_nCS_3 {2,6}
DC3P3V
{6,7} VX_nOE
98
97
SA_nCS_3 {2,6} DC3P3V
{13,14}
100
99
DC_15V
nNEP_REG_CS {6,10}
{13,14} DC_15V
100
99
nNEP_REG_CS {6,10}
{3,10,11}
102
101
nRESET_IN
nNEP_FLASH_CS {6}
{3,10,11} nRESET_IN
102
101
nNEP_FLASH_CS {6}
{3,6,11,13} nRESET_OUT
104
C21
103
SA_nCS_0 {2,6}
{3,6,11,13} nRESET_OUT
104
C21
103
SA_nCS_0 {2,6}
C22
C21
C22
C21
{6,10} CF_GFX_RESET
106
C22
105
{6,10} CF_GFX_RESET
106
C22
105
{3,10} GFX_IRQ_CF_BVD2
108
107
SYSCLK {8,13} {3,10} GFX_IRQ_CF_BVD2
108
107
SYSCLK {8,13}
110
110
{13} VDD_FAULT C23
109
{13} VDD_FAULT C23
109
C24
C23
C24
C23
112
{3,10} SA1111_IRQ_CF_BVD1
C24
111
SA_nPOE {2,6}
112
{10,12} IN_PWR
SA_nPWE {2,6}
{3,10} SA1111_IRQ_CF_BVD1
C24
111
SA_nPOE
114
113
114
113
{2,6}
{2,6} SA_nIOIS16
SA_nPIOW {2,6}
{10,12} IN_PWR
SA_nPWE
116
115
116
115
{2,6}
{2,6} SA_nIOIS16
SA_nPIOW
118
117
{2,6}
{2,6} SA_nPWAIT
SA_nPIOR {2,6}
118
117
{2,6} SA_nPWAIT
SA_nPIOR
120
119
{2,6}
{2} SA_PSKTSEL
SA_nPCE_1 {2,6}
120
119
{2} SA_PSKTSEL
SA_nPCE_1 {2,6}
{2,6} SA_nPREG
122
121
SA_nPCE_2 {2,6}
{2,6} SA_nPREG
122
121
SA_nPCE_2 {2,6}
124
C25
123
124
C25
123
C26
C25
C26
C25
126
{11} DVAL_1
C26
125
SA_BT_RXD {2,11}
126
SA_BT_RXD {2,11}
{11} DVAL_0
SA_BT_TXD {2,11}
{11} DVAL_1
C26
125
128
127
128
127
{11} DVAL_0
SA_BT_TXD {2,11}
130
{11} DREQ_0
C27
129
SWAP_FLASH {6}
130
{11} DREQ_0
C27
129
SWAP_FLASH
C28
C27
C28
C27
{6}
{3,10} GPIO_0
132
C28
131
SA_FF_TXD {2,10}
{3,10} GPIO_0
132
C28
131
SA_FF_TXD
134
133
{2,10}
A {3,9} USB_WAKE
SA_FF_RXD {2,10}
134
133
{3,9} USB_WAKE
SA_FF_RXD
136
135
136
135
{2,10}
A
{2,10,12} SA_I2C_SDA
138
137
{2,10,12} SA_I2C_SCL
nVBATT_LOW_IRQ {3,12}
{2,10,12} SA_I2C_SDA
138
137
{2,10,12} SA_I2C_SCL
nVBATT_LOW_IRQ
140
139
140
139
{3,12}
536279-6
536279-6
PXA250 Processor Reference Design
8
Expansion
Header 1
7
6
5
4
Expansion
Header 2
3
Size Rev
B
2.07
Date:
Tuesday, February 05, 2002
Sheet 15 of 16
2
1