Intel PXA250 and PXA210 Applications Processors

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8 1 Pg. 11 Sheet 11 of 16 1 7 6 5 4 3 2 Copyright 2002 Intel Corporation SD Socket DC3P3V J10 R147 10K D D Bottom Mount MMC_CS0 {2} RADIO_DSR {2} DC3P3V DAT2 9 SA_MMCMD {2} LAYOUT NOTE: Place close to Battery Header and Codec UCB CD_DAT3 1 1400 2 CMD 3 Radio VSS1 C132 4 MMC_PWR Baseband VDD {8} LINE_OUT_L 5 DNI IF MMC Connector SA_MMCCLK {2} 0.1UF J20 CLK C140 VSS2 6 R225 {8} LINE_OUT_R 1 2 0 DAT0 7 SA_MMDAT {2} DC3P3V 0.1UF 3 4 R226 DNI 0 MMC MMC_WP {2} 19 20 R227 DNI 100K {9} RADIO_MICP DAT1 8 DC3P3V DNI 5 {2} RADIO_DTR {2} 6 SA_BT_CTS R150 IF {2} SA_BT_RTS 7 8 SD DNI SA_BT_RXD {2,15} IF {2,15} SA_BT_TXD 9 10 RADIO_RI {2} C C SD 47.5K {6} RADIO_PWR_ON 11 12 RADIO_RXD_C {2} nMMC_DETECT {2,13} DC3P3V 13 {6} RADIO_WAKE 14 nRESET_IN {3,10,15} CARD Selection Resistors 15 16 RADIO_SPKRN and Values DNI {2} RADIO_DCD RES SD MMC IF {8,9} 17 MICGND 18 RADIO_SPKRP {8} R225 0 DNI 21 22 {3,6,13,15} nRESET_OUT R228 100K DNI DC5P5V 23 24 {3,8,10,12,13,14} VBATT AC97_GPIO_0 {8} DC5P5V {3,8,10,12,13,14} VBATT 25 26 AC97_GPIO_1 {8} U27 R198 27 28 AC97_GPIO_2 {8} MIC5207-3.3BM5 0 3.3V LDO REG 29 30 MMC_PWR {8} AC97_GPIO_4 AC97_GPIO_3 {8} 1 VIN 180ma VOUT 5 2 GND + B B {13} 3 MMC_ON EN BYP 4 LE33 R226 0 DC3P3V DC3P3V JTAG ICE Connector DNI R236 DVAL_1 {15} DREQ_1 {15} DREQ_0 {15} J19 {2,10} GPIO_22 R221 1 2 {3,6,10,13} 0 R219 JTAG_TMS 0 {15} R233 0 {3} JTAG_nTRST 3 4 {2,10} GPIO_21 {6,10} 5 6 CPLD1_TDI {6,10} 0 R218 CPLD1_TDI DVAL_0 {15} DNI {3,6,10,13} JTAG_TMS 7 8 {2,10} R234 0 GPIO_19 0 R232 {3,6,10,13} 9 10 JTAG_TCK {3,6,10,13} JTAG_TCK 11 12 {2,10} R235 0 GPIO_20 {3,10} R223 SA_TDO 13 14 {3,10} 0 R231 SA_TDO 0 A A 75 R224 {3,10,15} nRESET_IN 15 16 0 17 18 R222 100K R270 10K 2 4.7UF C92 1 R229 100K R228 100K 10 11 12 R227 100K WP COMM CD CHECK !! C91 0.1UF 19 20 PXA250 Processor Reference Design Size Rev B 2.07 8 7 6 5 4 3 Date: Tuesday, February 05, 2002 2
8 IN_PWR {10,15} D10 1 Pg. 12 7 6 5 4 3 2 Copyright 2002 Intel Corporation 5.5 Volt Supply D3 DC5P5V Processor Core Voltage Supply U28 L1 11-TM104-NP 4.7uH LTC1878 Battery Connector VBATT + 8 {3,8,10,11,13,14} LPF 1 D and Jumper Post {3,13} SA_PWR_EN RUN + D U29 7 {3,8,10,11,13,14} VBATT J18 SYNC-MODE 2 DC_CORE DC3P3V Ith 1 + LT1308A {3,8,10,11,13,14} VBATT 6 BATTERY VIN 6 VIN SW 5 2 3 FB L2 4 2 J17 4 5 1 2 GND FB GND SW LTNX R159 1 10uH 3 BATT_IN_POS {3,13} SA_PWR_EN nVBATT_LOW_IRQ {3,15} 2 + SHDN 8 LBO 0 3 BATT_IN_NEG LTC1878EMS8 R158 4 SA_I2C_SDA 1 7 5 {2,10,15} VC LBI 6 47.5K 7 SA_SMB_MODE 1308A 8 nBATT_PRESENT R162 R163 9 BATT_TEMP {3,8,10,11,13} VBATT 10 976K 61.9K DC3P3V U30 53261-1090 LTC1663 C 4 VCC C VOUT 3 1 {2,10,15} SA_I2C_SDA SDA GND 2 5 {2,10,15} SA_I2C_SCL SCL C100 0.1UF SA_I2C_SCL {2,10,15} DC_PLL {3} Battery Charger 3.3 Volt Supply DC3P3V DC5P5V U31 B B MIC5207-BM5 + ADJ LDO REG 1 180ma 5 D7 U43 VIN VOUT GRN D8 2 RED GND PLL Voltage Supply 3 DC_CORE nCHRG SENSE 9 3 4 EN BYP R211 10 Q1 LEAA DC3P3V {2,3} nCHRGR_PRESENT nACPR 0 7 4 U42 DRV 4 TIMER DC3P3V MIC5207-BM5 6 1 BATTERY ADJ LDO REG PROG BAT 1 180ma 5 U32 VIN VOUT 2 GND DNI LTC1732 {3,8,10,11,13,14} VBATT ADP3335 3 4 {3,13} SA_PWR_EN BYP + 7 5 LEAA IN_1 NR + 8 A IN_2 OUT_1 1 PLL_SENSE {3} A 6 SHUTDOWN 22UF C103 2 OUT_2 C104 0.1UF R169 200K 5 2 C137 2 1 0.33F 0.1UF R276 20K GND SEL R168 160K 2 1 2 1 Vcc 8 R165 887K R164 487K R161 100K 2 C99 22pF R160 196K 1 220pF C98 R155 100K 22UF C97 2 C94 0.1UF C95 100UF 1 DNI R170 8 100K C139 470PF R203 4.99K 33uF C138 R95 0 R201 357K C142 R206 5 6 7 8 0 3 2 1 R209 C144 1uF 1K C102 100PF D4 2 1 RED C101 R166 100UF 1K R157 150K R156 100K LTEP LTC1663CS5 R274 1 C143 4.7uF R167 100K R210 1K R275 0.1 12 22UF C96 R220 100K R154 357K 4 GND OUT_3 3 LFE ADP3335ARM-3.3 7 6 DNI 5 4 3 PXA250 Processor Reference Design Size Rev B 2.07 Date: Tuesday, February 05, 2002 Sheet 12 of 16 2 1
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Intel ® PXA250 and PXA210 Applicat
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Contents Contents 1 Introduction...
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Contents A.1 SA-1110 Hardware Migra
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Contents 2-7 SRAM / ROM / Flash / S
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Introduction 1 Table 1-1. Revision
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Introduction • System memory inte
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Introduction Table 1-3. Signal Pin
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Introduction Figure 1-2. PXA250 App
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Introduction Table 1-4. PXA250 Appl
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Introduction Figure 1-3. PXA210 App
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Introduction Table 1-5. PXA210 Appl
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System Memory Interface 2 This sect
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System Memory Interface Table 2-1.
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. System Memory Interface 2.4 SDRAM
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System Memory Interface Figure 2-5.
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System Memory Interface Figure 2-6.
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System Memory Interface 2.7 System
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LCD Display Controller 3 This chapt
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LCD Display Controller Figure 3-1.
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LCD Display Controller Figure 3-5.
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LCD Display Controller Note: This e
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LCD Display Controller However, typ
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USB Interface 4 4.1 Self Powered De
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MultiMediaCard (MMC) 5 The MultiMed
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MultiMediaCard (MMC) Figure 5-1. Ap
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MultiMediaCard (MMC) Warning: Conne
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AC97 6 The AC97 controller unit (AC
Page 65 and 66: I 2 C 7 The Inter-Integrated Circui
Page 67 and 68: . I2C Figure 7-2. Using an Analog S
Page 69 and 70: Power and Clocking 8 8.1 Operating
Page 71 and 72: Power and Clocking Since few system
Page 73 and 74: Power and Clocking Table 8-4. 32.76
Page 75 and 76: Power and Clocking Table 8-6. PXA25
Page 81 and 82: Power and Clocking Figure 8-2. Hard
Page 83 and 84: Power and Clocking Table 8-10. Slee
Page 85 and 86: Power and Clocking Table 8-14. Sync
Page 87 and 88: Power and Clocking Table 8-16. Vari
Page 89 and 90: Power and Clocking • Provide powe
Page 91 and 92: Power and Clocking 8.7.4 I/O 3.3 V
Page 93 and 94: JTAG/Debug Port 9 9.1 Description T
Page 95 and 96: SA-1110/Applications Processor Migr
Page 105 and 106: Example Form Factor Reference Desig
Page 107 and 108: 8 1 7 6 5 4 3 2 Copyright 2002 Inte
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Page 119 and 120: 8 C C 1 7 6 5 4 3 2 Copyright 2002
Page 121 and 122: 8 B B A A PXA250 Processor Referenc
Page 123 and 124: BBPXA2xx Development Baseboard Sche
Page 162 and 163: BBPXA2xx Development Baseboard Sche
Page 164: DCPXA250 Processor Card 32-bit vers
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DCPXA210 Processor Card 4 CONNECTOR
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Intel PXA250 and PXA210 Applications Processors

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