Intel PXA250 and PXA210 Applications Processors
Intel PXA250 and PXA210 Applications Processors Intel PXA250 and PXA210 Applications Processors
8 PXA250 Processor Reference Design 1 2 3 4 5 1 1 J7 12-54819-78 USB_WAKE {3,15} Sheet 9 of 16 1 7 6 5 4 3 2 Copyright 2002 Intel Corporation R105 {8} AUDIO3P3V 10 MIC_PWR Headset Jack Stereo Headphone Jack IrDA Transceiver 1 0.1UF VCC J4 AGND 2 1 3 D R_OUT {8} 3 FIR_SEL IRDA_FSEL {6} D MD_0 4 IRDA_MD0 11 {6} GND MD_1 5 IRDA_MD1 Microphone {6} L_OUT_B NC 6 2 GND 7 RXD 8 IR_RXD 1 {2} GND TXD 9 IR_TXD Speaker {2} DC3P3V LEDA 10 4 SHA 5 L_OUT_B STEREO HDSL-3600 # 007 SHB R107 J5 JACK 2 TIP 10 3 RING L_OUT_A {8} 3.5mm 4 R108 MICGND {8,11} HEADSET J6 10 JACK R109 2.5mm 10 MICIN {8} C79 R111 1 2 USB_5V 10 C R112 C 4.7UF {2} SA_UDCN R149 0 Mini USB Jack RADIO_MICP {11} 0 DC3P3V + J3 2 1 U19 DC3P3V C76 Pg. 9 DNI {2} R115 SA_UDCP 0 {8} AUDIO3P3V Dual Axis Acelerometer DNI B B U20 DC3P3V DC3P3V R123 100K XFILT {8} USB_5V 3 U21 MAX6348 RESET VIN 2 R120 YFILT {8} 100K A + + MAX6348XR40-T A 1uF C3 1uF C4 R117 1 2 237K C81 0.01UF C82 0.01UF C80 0.1UF R113 475K C78 0.1UF ADXL202E Dual Axis Accelerometer 8 VDD XCAP 7 1 ST YCAP 6 2 T2 XOUT 5 3 COM YOUT LCC8 4 R121 1K C84 0.1UF R118 10K R119 100K R116 475K R110 0 2 1 C77 0.1UF R106 1.5K R114 1.5K GND 1 Size Rev B 2.07 8 7 6 5 4 3 Date: Tuesday, February 05, 2002 2
8 1 Sheet 10 of 16 1 7 6 5 4 3 2 Copyright 2002 Intel Corporation J8 DC5P5V Momentary Switches CF_TYPE_II MIC5219BM5 Compact Flash Type II Socket 50 GND2 ADJ LDO REG 25 nCD2 1 DC3P3V S2 {13} CF_nCD2 D10 VIN 500ma VOUT 5 49 {7,15} VX_D10 24 nIOIS16 2 1 S 2 {6} CF_nIOIS16 GPIO_0 D09 GND 48 4 3 {3,15} {7,15} VX_D9 23 D02 3 4 D {7,15} VX_D2 D D08 {13} CF_PWR EN 47 ADJ {7,15} VX_D8 22 D01 LGAA R129 {7,15} VX_D1 46 BVD1 DC3P3V S3 {3,15} SA1111_IRQ_CF_BVD1 21 D00 U24 R130 10K {7,15} VX_D0 {3,15} GFX_IRQ_CF_BVD2 45 BVD2 1 S 2 GPIO_32 20 A00 MIC5219-3.3BM5 {3} 10K 4 3 {6,15} VX_A0 44 nREG 3.3V LDO REG {6} CF_nPREG 19 A01 1 CF_VDD {6,15} VX_A1 {3,8,11,12,13,14} VBATT 500ma 5 nINPACK VIN VOUT 43 CF_I2C_SDA A02 DC3P3V S4 {6,15} VX_A2 18 2 nWAIT GND 42 + {6} CF_nPWAIT 17 A03 3 4 {6,15} VX_A3 GPIO_17 RESET EN 41 BYP 1 S 2 R132 4 3 {3} {6,15} CF_GFX_RESET 16 A04 LG33 1K {7,15} VX_A4 CF_I2C_SCL 40 nVS2 15 A05 {7,15} VX_A5 39 nCSE DC3P3V S5 {6,15} nNEP_REG_CS 14 A06 {7,15} VX_A6 VCC2 R15 38 1 S 2 CF_VDD GPIO_22 13 VCC1 J9 4 3 0 Base Station Connector {2,11} 37 IREQ {6,15} CF_IRQ_LVL2OE 12 A07 {7,15} VX_A7 36 nWE {6} CF_nPWE C 11 A08 DC3P3V {7,15} VX_A8 C 35 nIOWR {6} CF_nPIOW 10 A09 DC3P3V {7,15} VX_A9 34 nIORD 20 Three Position Switch {6} CF_nPIOR 9 nOE 19 {6} CF_nPOE 33 nVS1 18 {8} CF_AUD 8 A10 17 R135 {7,15} VX_A10 32 nCE2 R138 {13} CF_nCD1 {6} CF_nPCE_2 nCE1 {2,14} GPIO_21 {6} CF_nPCE_1 7 100K 31 D15 RS_RI 100K 16 15 {7,15} VX_D15 6 D07 R136 {7,15} VX_D7 R140 D14 RS_DCD {13} CF_nCD2 {7,15} VX_D14 30 14 13 SA_nWE 5 D06 {2,4,5,6,7} 100K {7,15} VX_D6 1.5K 29 D13 12 11 DC3P3V {7,15} VX_D13 D05 {3,6,11,13} JTAG_TCK 4 R139 {7,15} VX_D5 28 D12 RS_TX 10 9 RS_RX {6} CF_nIOIS16 {7,15} VX_D12 D04 {7,15} VX_D4 3 S6 100K 27 D11 RS_RTS 8 7 {7,15} VX_D11 2 D03 CCW R141 {7,15} VX_D3 26 nCD1 RS_CTS R142 6 5 {6} CF_nPWAIT {13} CF_nCD1 nRESET_IN 1 GND1 0 {3,11,15} 100K RS_DTR 4 3 DNI PUSH RS_DSR 2 1 B B JTAG_TMS {3,6,11,13} CW 22 CPLD1_TDI {6,11} U25 R144 C86 21 {12,15} IN_PWR SA_TDO C87 {3,11} 75 MAX3244ECAI 0.1UF 0.1UF RS-232 XCVR 28 27 C88 C1+ V+ 24 3 C89 C1- V- DC3P3V {2,14} GPIO_20 1 0.1UF C2+ 2 0.1UF C2- {2,14} GPIO_19 14 RS_TX {2,15} SA_FF_TXD T1 IN T1OUT 9 13 RS_RTS U26 DC3P3V {2} SA_FF_RTS T2 IN T2OUT 10 RS_DTR {2} SA_FF_DTR 12 T3 IN T3OUT 11 19 RS_RX MAX4542 {2,15} SA_FF_RXD R1OUT R1 IN 4 18 RS_DCD 2 {2} SA_FF_DCD R2OUT R2 IN 5 RS_DSR V+ 17 {2} SA_FF_DSR R3OUT R3 IN 6 RS_RI {2} SA_FF_RI 16 R4OUT R4 IN 7 RS_CTS {2,12,15} SA_I2C_SCL 8 COM_1 15 8 A {2} SA_FF_CTS R5OUT R5 IN 7 1 A IN_1 NC_1 CF_I2C_SCL 20 R2OUTB INVLD 21 RS232_VALID {3} {6} RS232_ON 22 FORCEOFF VCC 26 {2,12,15} SA_I2C_SDA 4 COM_2 NC_2 5 CF_I2C_SDA 23 GND 25 FORCEON 3 PXA250 Processor Reference Design {3} SA_I2C_ENAB IN_2 6 GND Size Rev AAAF B 2.07 C90 0.1UF R145 100K R146 100K R153 0 R17 0 1 2 3 R122 0 U23 4 5 6 R16 0 R134 100K 2 R133 100K 4.7UF C85 1 R131 100K R128 1.5K R127 100K R126 953 Pg. 10 8 7 6 5 4 3 Date: Tuesday, February 05, 2002 2
- Page 63 and 64: AC97 6 The AC97 controller unit (AC
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- Page 67 and 68: . I2C Figure 7-2. Using an Analog S
- Page 69 and 70: Power and Clocking 8 8.1 Operating
- Page 71 and 72: Power and Clocking Since few system
- Page 73 and 74: Power and Clocking Table 8-4. 32.76
- Page 75 and 76: Power and Clocking Table 8-6. PXA25
- Page 77 and 78: Power and Clocking Table 8-6. PXA25
- Page 79 and 80: Power and Clocking Table 8-6. PXA25
- Page 81 and 82: Power and Clocking Figure 8-2. Hard
- Page 83 and 84: Power and Clocking Table 8-10. Slee
- Page 85 and 86: Power and Clocking Table 8-14. Sync
- Page 87 and 88: Power and Clocking Table 8-16. Vari
- Page 89 and 90: Power and Clocking • Provide powe
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8<br />
1<br />
Sheet 10 of 16<br />
1<br />
7<br />
6<br />
5<br />
4<br />
3<br />
2<br />
Copyright 2002 <strong>Intel</strong> Corporation<br />
J8<br />
DC5P5V<br />
Momentary Switches<br />
CF_TYPE_II<br />
MIC5219BM5<br />
Compact Flash Type II Socket<br />
50 GND2<br />
ADJ LDO REG<br />
25 nCD2<br />
1<br />
DC3P3V<br />
S2<br />
{13} CF_nCD2<br />
D10<br />
VIN 500ma VOUT<br />
5<br />
49<br />
{7,15} VX_D10<br />
24 nIOIS16<br />
2<br />
1 S 2<br />
{6} CF_nIOIS16<br />
GPIO_0<br />
D09<br />
GND<br />
48<br />
4 3<br />
{3,15}<br />
{7,15} VX_D9<br />
23 D02<br />
3 4<br />
D {7,15} VX_D2<br />
D<br />
D08<br />
{13} CF_PWR EN<br />
47<br />
ADJ<br />
{7,15} VX_D8<br />
22 D01<br />
LGAA<br />
R129 {7,15} VX_D1<br />
46 BVD1<br />
DC3P3V<br />
S3<br />
{3,15} SA1111_IRQ_CF_BVD1<br />
21 D00<br />
U24<br />
R130<br />
10K {7,15} VX_D0<br />
{3,15} GFX_IRQ_CF_BVD2<br />
45 BVD2<br />
1 S 2<br />
GPIO_32<br />
20 A00<br />
MIC5219-3.3BM5<br />
{3}<br />
10K<br />
4 3<br />
{6,15} VX_A0<br />
44 nREG<br />
3.3V LDO REG<br />
{6} CF_nPREG<br />
19 A01<br />
1<br />
CF_VDD<br />
{6,15} VX_A1<br />
{3,8,11,12,13,14} VBATT<br />
500ma<br />
5<br />
nINPACK<br />
VIN VOUT<br />
43<br />
CF_I2C_SDA<br />
A02<br />
DC3P3V<br />
S4<br />
{6,15} VX_A2<br />
18<br />
2<br />
nWAIT<br />
GND<br />
42<br />
+<br />
{6} CF_nPWAIT<br />
17 A03<br />
3 4<br />
{6,15} VX_A3<br />
GPIO_17<br />
RESET<br />
EN<br />
41<br />
BYP<br />
1 S 2<br />
R132<br />
4 3<br />
{3}<br />
{6,15} CF_GFX_RESET<br />
16 A04<br />
LG33<br />
1K {7,15} VX_A4<br />
CF_I2C_SCL<br />
40 nVS2<br />
15 A05<br />
{7,15} VX_A5<br />
39 nCSE<br />
DC3P3V<br />
S5<br />
{6,15} nNEP_REG_CS<br />
14 A06<br />
{7,15} VX_A6<br />
VCC2<br />
R15<br />
38<br />
1 S 2<br />
CF_VDD<br />
GPIO_22<br />
13 VCC1<br />
J9<br />
4 3 0<br />
Base Station Connector<br />
{2,11}<br />
37 IREQ<br />
{6,15} CF_IRQ_LVL2OE<br />
12 A07<br />
{7,15} VX_A7<br />
36 nWE<br />
{6} CF_nPWE<br />
C 11 A08<br />
DC3P3V<br />
{7,15} VX_A8<br />
C<br />
35 nIOWR<br />
{6} CF_nPIOW<br />
10 A09<br />
DC3P3V<br />
{7,15} VX_A9<br />
34 nIORD<br />
20<br />
Three Position Switch<br />
{6} CF_nPIOR<br />
9 nOE<br />
19<br />
{6} CF_nPOE<br />
33 nVS1<br />
18<br />
{8} CF_AUD<br />
8 A10<br />
17<br />
R135<br />
{7,15} VX_A10<br />
32 nCE2<br />
R138<br />
{13} CF_nCD1<br />
{6} CF_nPCE_2<br />
nCE1<br />
{2,14} GPIO_21<br />
{6} CF_nPCE_1<br />
7<br />
100K<br />
31 D15<br />
RS_RI<br />
100K<br />
16 15<br />
{7,15} VX_D15<br />
6 D07<br />
R136<br />
{7,15} VX_D7<br />
R140<br />
D14<br />
RS_DCD<br />
{13} CF_nCD2<br />
{7,15} VX_D14<br />
30<br />
14 13<br />
SA_nWE<br />
5 D06<br />
{2,4,5,6,7}<br />
100K<br />
{7,15} VX_D6<br />
1.5K<br />
29 D13<br />
12 11<br />
DC3P3V<br />
{7,15} VX_D13<br />
D05<br />
{3,6,11,13} JTAG_TCK<br />
4<br />
R139<br />
{7,15} VX_D5<br />
28 D12<br />
RS_TX 10<br />
9<br />
RS_RX<br />
{6} CF_nIOIS16<br />
{7,15} VX_D12<br />
D04<br />
{7,15} VX_D4<br />
3<br />
S6<br />
100K<br />
27 D11<br />
RS_RTS 8 7<br />
{7,15} VX_D11<br />
2 D03<br />
CCW<br />
R141<br />
{7,15} VX_D3<br />
26 nCD1<br />
RS_CTS<br />
R142<br />
6 5<br />
{6} CF_nPWAIT<br />
{13} CF_nCD1<br />
nRESET_IN<br />
1 GND1<br />
0<br />
{3,11,15}<br />
100K<br />
RS_DTR 4 3<br />
DNI<br />
PUSH<br />
RS_DSR 2<br />
1<br />
B B<br />
JTAG_TMS {3,6,11,13}<br />
CW<br />
22<br />
CPLD1_TDI {6,11}<br />
U25<br />
R144<br />
C86<br />
21<br />
{12,15} IN_PWR<br />
SA_TDO<br />
C87<br />
{3,11}<br />
75<br />
MAX3244ECAI<br />
0.1UF<br />
0.1UF<br />
RS-232 XCVR<br />
28<br />
27 C88<br />
C1+<br />
V+<br />
24<br />
3<br />
C89<br />
C1-<br />
V-<br />
DC3P3V<br />
{2,14} GPIO_20<br />
1<br />
0.1UF<br />
C2+<br />
2<br />
0.1UF<br />
C2-<br />
{2,14} GPIO_19<br />
14<br />
RS_TX<br />
{2,15} SA_FF_TXD T1 IN T1OUT<br />
9<br />
13<br />
RS_RTS<br />
U26<br />
DC3P3V<br />
{2} SA_FF_RTS T2 IN T2OUT<br />
10<br />
RS_DTR<br />
{2} SA_FF_DTR<br />
12<br />
T3 IN T3OUT<br />
11<br />
19<br />
RS_RX<br />
MAX4542<br />
{2,15} SA_FF_RXD R1OUT R1 IN<br />
4<br />
18<br />
RS_DCD<br />
2<br />
{2} SA_FF_DCD R2OUT R2 IN<br />
5<br />
RS_DSR<br />
V+<br />
17<br />
{2} SA_FF_DSR R3OUT R3 IN<br />
6<br />
RS_RI<br />
{2} SA_FF_RI<br />
16<br />
R4OUT R4 IN<br />
7<br />
RS_CTS<br />
{2,12,15} SA_I2C_SCL<br />
8<br />
COM_1<br />
15<br />
8<br />
A {2} SA_FF_CTS R5OUT R5 IN<br />
7<br />
1<br />
A<br />
IN_1<br />
NC_1<br />
CF_I2C_SCL<br />
20<br />
R2OUTB INVLD<br />
21<br />
RS232_VALID {3}<br />
{6} RS232_ON<br />
22<br />
FORCEOFF VCC<br />
26<br />
{2,12,15} SA_I2C_SDA<br />
4<br />
COM_2 NC_2<br />
5<br />
CF_I2C_SDA<br />
23<br />
GND<br />
25<br />
FORCEON<br />
3<br />
<strong>PXA250</strong> Processor Reference Design<br />
{3} SA_I2C_ENAB<br />
IN_2<br />
6<br />
GND<br />
Size Rev<br />
AAAF<br />
B<br />
2.07<br />
C90<br />
0.1UF<br />
R145<br />
100K<br />
R146<br />
100K<br />
R153<br />
0<br />
R17<br />
0<br />
1<br />
2<br />
3<br />
R122<br />
0<br />
U23<br />
4<br />
5<br />
6<br />
R16<br />
0<br />
R134<br />
100K<br />
2<br />
R133<br />
100K<br />
4.7UF<br />
C85<br />
1<br />
R131<br />
100K<br />
R128<br />
1.5K<br />
R127<br />
100K<br />
R126<br />
953<br />
Pg. 10<br />
8<br />
7<br />
6<br />
5<br />
4<br />
3<br />
Date:<br />
Tuesday, February 05, 2002<br />
2
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