Intel PXA250 and PXA210 Applications Processors
Intel PXA250 and PXA210 Applications Processors Intel PXA250 and PXA210 Applications Processors
8 1 Pg. 7 Sheet 7 of 16 1 7 6 5 4 3 2 Copyright 2002 Intel Corporation DC3P3V Transceivers NOTE: DIR H = A -> B DIR L = A
8 1 Sheet 8 of 16 1 7 6 5 4 3 2 Copyright 2002 Intel Corporation XTAL_IN Audio CODEC XTAL_OUT U15 24.576MHZ + UCB1400 XTAL_IN 2 Modem / Audio XTL_IN ADCSYNC 12 R72 DNI 0 XTAL_OUT 3 34 XTL_OUT VREFDRV D D VREF C46 L_OUT_A {9} 100UF C50 R_OUT {9} 100UF R89 6 AMP5V 1 2 R92 AUDIO3P3V {9} 1 DNI AUDIO3P3V {9} + 27 {13,15} SYSCLK 8 29 DNI {2} SA_SDATA_IN SDATA_IN IRQOUT AC97_IRQ {3} R73 R74 6 37 {2} SA_BITCLK BIT_CLK GPIO_0 AC97_GPIO_0 {11} Audio Amp 47.5 R75 0 5 39 {2} SA_SDATA_OUT SDATA_OUT GPIO_1 AC97_GPIO_1 {11} R76 0 R77 {2} SA_SYNC 10 40 SYNC GPIO_2 AC97_GPIO_2 {11} 20K R78 0 R79 11 41 {2} SA_nAC97_RESET RESET GPIO_3 AC97_GPIO_3 {11} 0 R80 LINE_OUT_L {11} 43 20K C141 GPIO_4 AC97_GPIO_4 {11} {9} MICIN 21 MICP R82 0 R14 2 1 44 U16 {10} CF_AUD R83 GPIO_5 LINE_OUT_R {11} 10K 22 4.7UF {9,11} MICGND MICGND 100K 45 R84 {11} RADIO_SPKRP 0 GPIO_6 LM4881 J1 C45 100K Dual Audio Pwr 2 1 23 46 R86 R81 {9} LINE_IN_L GPIO_7 Amp w/shutdwn C131 100K 2 1 24 47 R87 0.1UF 20K 8 7 LINE_IN_R GPIO_8 C47 IN_A OUT_A 4.7UF J2 48 R124 100K R85 4 GPIO_9 IN_B OUT_B 5 C C R88 100K 20K 20 0.1UF 1 {14} TSPY TSPY BYPASS VDD R90 0 18 35 {14} TSMX LINE_OUT_L 3 TSMX {6} SPKR_OFF SHDN GND R91 0 19 36 {14} TSMY TSMY LINE_OUT_R DC_CORE R93 0 + 17 LM4881MM {14} TSPX TSPX 0 R94 AD_3 13 VBATT {3,10,11,12,13,14} 0 {3,10,11,12,13,14} 14 AD_2 R96 0 15 AD_1 XFILT {9} DC5P5V U17 {9} AUDIO3P3V 16 AD_0 YFILT 1 {9} MIC5207-3.3BM5 DVDD1 9 4 3.3V LDO REG DVDD2 DVSS1 DVSS2 7 1 180ma 5 VIN VOUT 25 AVDD1 32 26 2 AVDD2 GND 38 AVDD3 AVSS2 33 AVSS3 42 3 4 EN BYP B B LE33 R99 28 VADCP 10 C58 0.1UF C55 0.01UF C42 0.1UF Pg. 8 R101 1 R104 2 C71 + 4.7UF C72 1 2 C68 + 4.7UF C67 1 C57 0.1UF + + + MIC5207-4.0BM5 4.0V LDO REG VIN 180ma VOUT GND {6} AUDIO_PWR_ON 3 4 EN BYP LE40 A A 1 1 2 U18 5 C73 270PF C62 0.1UF C59 0.01UF R100 1 C66 0.1UF C53 0.01UF C56 0.01UF 30 TEST VADCN 31 + AMP5V C75 + 4.7UF 1 2 C74 0.1UF 0.1UF R102 0 R103 0 2 C69 4.7UF C70 0.1UF 1 0.1UF R282 0 C63 270PF 2 C64 0.01UF C61 4.7UF 1 C54 0.01UF C52 0.1UF C51 1UF 1 2 2 R71 + 47.5 33PF C43 Y3 2 1 22pF C44 1 10UF C41 PXA250 Processor Reference Design Size Rev B 2.07 8 7 6 5 4 3 Date: Tuesday, February 05, 2002 2
- Page 61 and 62: MultiMediaCard (MMC) Warning: Conne
- Page 63 and 64: AC97 6 The AC97 controller unit (AC
- Page 65 and 66: I 2 C 7 The Inter-Integrated Circui
- Page 67 and 68: . I2C Figure 7-2. Using an Analog S
- Page 69 and 70: Power and Clocking 8 8.1 Operating
- Page 71 and 72: Power and Clocking Since few system
- Page 73 and 74: Power and Clocking Table 8-4. 32.76
- Page 75 and 76: Power and Clocking Table 8-6. PXA25
- Page 77 and 78: Power and Clocking Table 8-6. PXA25
- Page 79 and 80: Power and Clocking Table 8-6. PXA25
- Page 81 and 82: Power and Clocking Figure 8-2. Hard
- Page 83 and 84: Power and Clocking Table 8-10. Slee
- Page 85 and 86: Power and Clocking Table 8-14. Sync
- Page 87 and 88: Power and Clocking Table 8-16. Vari
- Page 89 and 90: Power and Clocking • Provide powe
- Page 91 and 92: Power and Clocking 8.7.4 I/O 3.3 V
- Page 93 and 94: JTAG/Debug Port 9 9.1 Description T
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Copyright 2002 <strong>Intel</strong> Corporation<br />
DC3P3V<br />
Transceivers<br />
NOTE:<br />
DIR H = A -> B<br />
DIR L = A
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