Intel PXA250 and PXA210 Applications Processors
Intel PXA250 and PXA210 Applications Processors
Intel PXA250 and PXA210 Applications Processors
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8<br />
1<br />
Sheet 6 of 16<br />
1<br />
7<br />
6<br />
5<br />
4<br />
3<br />
2<br />
Copyright 2002 <strong>Intel</strong> Corporation<br />
U8<br />
Pg. 6<br />
CF_PWR_ON<br />
Buffer<br />
{13}<br />
16_Bit Buffer/Line<br />
R59<br />
Driver<br />
100K<br />
74LVCH162244A<br />
47<br />
2<br />
{2,15} SA_nPIOW<br />
CF_nPIOW {10}<br />
R60<br />
1A1<br />
1Y1<br />
46<br />
{2,15} SA_nPOE 1A2<br />
1Y2<br />
3<br />
CF_nPOE {10}<br />
D CF_nPWE {10} 100K<br />
44<br />
{2,15} SA_nPWE 1A3<br />
1Y3<br />
5<br />
Board Control<br />
D<br />
43<br />
{2,15} SA_nPIOR 1A4<br />
1Y4<br />
6<br />
CF_nPIOR {10}<br />
CF_GFX_RESET<br />
Register<br />
{10,15}<br />
IRDA_FSEL {9}<br />
{2} SA_nSDCS_2<br />
41<br />
2A1<br />
2Y1<br />
8<br />
VX_nSDCS_2 {15}<br />
IRDA_MD0 {9}<br />
{2,15} SA_nPCE_2<br />
40<br />
CF_nPCE_2 {10}<br />
IRDA_MD1 {9} DC3P3V<br />
2A2<br />
2Y2<br />
9<br />
{2,4} SA_SDCKE_1<br />
38<br />
2A3<br />
2Y3<br />
11<br />
VX_SDCKE_1 {15} CF_nBUS_ON<br />
37<br />
{2} SA_SDCLK_2 2A4<br />
2Y4<br />
12<br />
VX_SDCLK_2 {15}<br />
U9<br />
{10} CF_nPWAIT<br />
36<br />
SA_nPWAIT {2,15}<br />
R61<br />
3A1<br />
3Y1<br />
13<br />
{10} CF_nIOIS16<br />
35<br />
3A2<br />
3Y2<br />
14<br />
SA_nIOIS16 {2,15}<br />
100K<br />
{2,15} SA_nPREG<br />
33<br />
3A3<br />
3Y3<br />
16<br />
CF_nPREG {10} 74LVCH16374A<br />
{2,15} SA_nPCE_1<br />
32<br />
17<br />
CF_nPCE_1 {10}<br />
R62<br />
3A4<br />
3Y4<br />
16-Bit Edge Triggered<br />
{2,5} SA_A3<br />
VX_A3 {10,15}<br />
100K<br />
30<br />
4A1<br />
4Y1<br />
19<br />
D-Type Flip Flop<br />
29<br />
{2,5} SA_A2 4A2<br />
4Y2<br />
20<br />
VX_A2 {10,15} 47<br />
{2,4,5,7} SA_D0 1D1<br />
2<br />
1Q1<br />
AUDIO_PWR_ON<br />
{2} SA_A1<br />
27<br />
{8}<br />
4A3<br />
4Y3<br />
22<br />
VX_A1 {10,15} {2,4,5,7} SA_D1<br />
46<br />
1D2<br />
3<br />
1Q2<br />
26<br />
{2} SA_A0 4A4<br />
4Y4<br />
23<br />
VX_A0 {10,15} 44<br />
{2,4,5,7} SA_D2 1D3<br />
5<br />
1Q3<br />
LIGHT_PWR_ON<br />
43<br />
{13}<br />
{2,4,5,7} SA_D3 1D4<br />
1Q4<br />
6<br />
{7} nVX_CF_OE<br />
1<br />
1nOE VSS_1<br />
4<br />
41<br />
{2,4,5,7} SA_D4 1D5<br />
1Q5<br />
8<br />
48<br />
10<br />
40<br />
9<br />
R63<br />
2nOE VSS_2<br />
{2,4,5,7} SA_D5 1D6<br />
1Q6<br />
25<br />
DC3P3V CF_nBUS_ON<br />
3nOE VSS_3<br />
15<br />
38<br />
{2,4,5,7} SA_D6 1D7<br />
1Q7<br />
11<br />
100K<br />
24<br />
4nOE VSS_4<br />
21<br />
37<br />
{2,4,5,7} SA_D7 1D8<br />
1Q8<br />
12<br />
VSS_5<br />
28<br />
7<br />
VDD_1 VSS_6<br />
34<br />
36<br />
13<br />
{2,4,5,7} SA_D8 2D1<br />
2Q1<br />
LCD_PWR_ON {13,14}<br />
C 18<br />
VDD_2 VSS_7<br />
39<br />
35<br />
14<br />
{2,4,5,7} SA_D9 2D2<br />
2Q2<br />
C<br />
31<br />
VDD_3 VSS_8<br />
45<br />
33<br />
16<br />
{2,4,5,7} SA_D10 2D3<br />
2Q3<br />
42<br />
32<br />
17<br />
R64<br />
VDD_4<br />
{2,4,5,7} SA_D11 2D4<br />
2Q4<br />
{2,4,5,7} SA_D12<br />
30<br />
2D5<br />
2Q5<br />
19<br />
100K<br />
{2,4,5,7} SA_D13<br />
29<br />
2D6<br />
2Q6<br />
20<br />
{2,4,5,7} SA_D14<br />
27<br />
2Q7<br />
22<br />
RS232_ON<br />
74LVCH162244APF<br />
2D7<br />
{10}<br />
{2,4,5,7} SA_D15<br />
26<br />
2D8<br />
2Q8<br />
23<br />
nBCR_OE<br />
1<br />
R65<br />
nBCR_WR<br />
1nOE<br />
48<br />
1CLK<br />
100K<br />
4<br />
DC3P3V<br />
VSS_1<br />
24<br />
10<br />
2nOE VSS_2<br />
25<br />
15<br />
2CLK VSS_3<br />
RADIO_PWR_ON<br />
21<br />
{11}<br />
VSS_4<br />
7<br />
VDD_1 VSS_5<br />
28<br />
18<br />
VDD_2 VSS_6<br />
34<br />
R66<br />
31<br />
VDD_3 VSS_7<br />
39<br />
100K<br />
42<br />
VDD_4 VSS_8 45<br />
RADIO_WAKE {11}<br />
U10<br />
74LVCH16374A<br />
DC3P3V<br />
CPLD<br />
nRED_LED<br />
B XCR3032XL-10VQ44C<br />
B<br />
Xilinx CPLD<br />
{2} SA_SDCLK_2<br />
42<br />
35<br />
CF_nBUS_ON<br />
D1<br />
A0_CLK<br />
B0<br />
R67<br />
{15} nNEP_FLASH_CS<br />
43<br />
A1<br />
B1<br />
34<br />
nXCV_ADD_OE {7,13}<br />
2 1<br />
{7}<br />
44<br />
XCV_DATA_DIR A2<br />
B2<br />
33<br />
SA_nCS_5 {2,15}<br />
{10,11} CPLD1_TDI<br />
CPLD1_TDO {11,13}<br />
1.5K<br />
1<br />
RED<br />
DC3P3V<br />
A3_TDI<br />
B3_TDO<br />
32<br />
2<br />
nGREEN_LED<br />
{3,15} MBGNT_CF_IRQ<br />
nBCR_OE<br />
A4<br />
B4<br />
31<br />
SA_nCS_4<br />
3<br />
{2,15}<br />
nBCR_WR<br />
A5<br />
B5<br />
30<br />
SA_nCS_3<br />
5<br />
{2,15}<br />
SA_nCS_2 {2}<br />
D2<br />
A6<br />
B6<br />
28<br />
{7} nVX_CF_OE<br />
SA_nCS_1 {2}<br />
R68<br />
6<br />
A7<br />
B7<br />
27<br />
2 1<br />
7<br />
{3,10,11,13} JTAG_TMS<br />
A8_TMS<br />
B8_TCK<br />
26<br />
JTAG_TCK {3,10,11,13}<br />
GRN<br />
{10,15} nNEP_REG_CS<br />
SA_nCS_0 {2,15} 1.5K<br />
8<br />
A9<br />
B9<br />
25<br />
10<br />
{2,4,5,7,10} SA_nWE<br />
A10<br />
B10<br />
23<br />
SA_A25 {2,7}<br />
{7} nXCV_DATA_OE<br />
11<br />
A11<br />
B11<br />
22<br />
VX_nOE {7,15}<br />
SPKR_OFF<br />
12<br />
{8} DC3P3V<br />
{7} XCV_ADD_DIR A12<br />
B12<br />
21<br />
13<br />
{10,15} CF_IRQ_LVL2OE<br />
A13<br />
B13<br />
20<br />
SA_nPCE_2<br />
14<br />
19<br />
{2,15}<br />
{3,11,13,15} nRESET_OUT<br />
SA_nPCE_1 {2,15} DC3P3V<br />
A14<br />
B14<br />
R69<br />
{5} nFLASH_BOOT_CS<br />
15<br />
A15<br />
B15<br />
18<br />
SA_RD_nWR {2,15}<br />
100K<br />
VDD_1<br />
9<br />
VDD_2<br />
17<br />
VDD_3<br />
29<br />
{15} SWAP_FLASH<br />
37<br />
IN0<br />
41<br />
VDD_4<br />
R70<br />
39<br />
A {2,4,7} SA_nSDRAS IN1<br />
MMC_PWR_ON {13}<br />
38<br />
4<br />
A<br />
{2} SA_nSDCS_2 IN2<br />
VSS_1<br />
0<br />
40<br />
16<br />
{2,4,5,7} SA_nSDCAS<br />
IN3<br />
VSS_2<br />
VSS_3<br />
24<br />
VSS_4<br />
36<br />
C29<br />
0.1UF<br />
C30<br />
0.1UF<br />
C31<br />
0.1UF<br />
C32<br />
0.1UF<br />
C27<br />
0.1UF<br />
C28<br />
0.1UF<br />
C25<br />
0.1UF<br />
C26<br />
0.1UF<br />
<strong>PXA250</strong> Processor Reference Design<br />
XCR3032XL<br />
Size Rev<br />
B<br />
2.07<br />
8<br />
7<br />
6<br />
5<br />
4<br />
3<br />
Date:<br />
Tuesday, February 05, 2002<br />
2
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