Intel PXA250 and PXA210 Applications Processors

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8 1 Sheet 5 of 16 1 7 6 5 4 3 2 Copyright 2002 Intel Corporation U6 Flash Memory Intel StrataFlash 16M x 16 G2 F2 A0 DQ0 SA_D0 A1 E2 {2,4,6,7} {2,6} SA_A2 A1 DQ1 SA_D1 B1 G3 {2,4,6,7} {2,6} SA_A3 A2 DQ2 SA_D2 C1 E4 {2,4,6,7} {2,7} SA_A4 A3 DQ3 SA_D3 D1 E5 {2,4,6,7} {2,7} SA_A5 A4 DQ4 SA_D4 D2 G5 {2,4,6,7} {2,7} SA_A6 A5 DQ5 SA_D5 A2 {2,4,6,7} D {2,7} SA_A7 A6 DQ6 G6 SA_D6 Resistor StrataFlash Synchronous D C2 {2,4,6,7} {2,7} SA_A8 A7 DQ7 H7 SA_D7 A3 {2,4,6,7} StrataFlash {2,7} SA_A9 A8 DQ8 E1 SA_D8 B3 {2,4,6,7} {2,4,7} SA_A10 A9 DQ9 E3 SA_D9 C3 {2,4,6,7} {2,4,7} SA_A11 A10 DQ10 F3 SA_D10 {2,4,6,7} R52 DNI IN {2,4,7} SA_A12 D3 A11 DQ11 F4 SA_D11 C4 {2,4,6,7} {2,4,7} SA_A13 A12 DQ12 F5 SA_D12 {2,4,6,7} R53 IN DNI A5 {2,4,7} SA_A14 A13 DQ13 H5 SA_D13 B5 {2,4,6,7} {2,4,7} SA_A15 A14 DQ14 G7 SA_D14 {2,4,6,7} R54 DNI IN C5 E7 {2,4,7} SA_A16 SA_D15 DC3P3V A15 DQ15 {2,4,6,7} {2,4,7} SA_A17 D7 A16 R56 DNI IN D8 DNI {2,4,7} SA_A18 A17 E8 STS A7 DC3P3V {2,4,7} SA_A19 A18 R212 R57 DNI IN B7 {2,4,7} SA_A20 A19 B6 DU1 / NC C7 C6 {2,4,7} SA_A21 A20 DU2 / nWP 0 R52 R212 DNI IN {2,4,7} SA_A22 C8 D5 A21 DU3 / VDDQ A8 D6 {2,4,7} SA_A23 A22 DU4 / VDDQ 0 G1 {2,4,7} SA_A24 A23 H8 A24 DC3P3V H2 DNI DU8 / VSSQ D4 {13} FLASH_nRP nRP F1 R54 nBYTE E6 G4 {2,15} SA_SDCLK_0 DU5 / CLK V_DDQ R55 C 0 F6 DU6 / ADV A4 V_PEN C F7 DU7 / WAIT 0 A6 R56 VDD_1 F8 H3 {2,4,6,7} SA_nSDCAS {2,7} SA_nOE nOE VDD_2 0 G8 {2,4,6,7,10} SA_nWE nWE B2 VSS_1 {6} nFLASH_BOOT_CS B4 H4 nCE_0 VSS_2 B8 H6 CS_AWS nCE_1 VSS_3 H1 nCE_2 BGA Pg. 5 DNI R58 10K C2 0.1UF U7 Intel StrataFlash 16M x 16 G2 F2 A0 DQ0 SA_D16 A1 E2 {2,4,7} {2,6} SA_A2 A1 DQ1 SA_D17 B1 G3 {2,4,7} {2,6} SA_A3 A2 DQ2 SA_D18 C1 E4 {2,4,7} {2,7} SA_A4 A3 DQ3 SA_D19 {2,7} SA_A5 D1 E5 {2,4,7} A4 DQ4 SA_D20 D2 G5 {2,4,7} {2,7} SA_A6 A5 DQ5 SA_D21 A2 {2,4,7} {2,7} SA_A7 A6 DQ6 G6 SA_D22 {2,4,7} B C2 B {2,7} SA_A8 A7 DQ7 H7 SA_D23 A3 {2,4,7} {2,7} SA_A9 A8 DQ8 E1 SA_D24 B3 {2,4,7} {2,4,7} SA_A10 A9 DQ9 E3 SA_D25 C3 {2,4,7} {2,4,7} SA_A11 A10 DQ10 F3 SA_D26 D3 {2,4,7} {2,4,7} SA_A12 A11 DQ11 F4 SA_D27 C4 F5 {2,4,7} {2,4,7} SA_A13 A12 DQ12 SA_D28 A5 H5 {2,4,7} {2,4,7} SA_A14 A13 DQ13 SA_D29 B5 G7 {2,4,7} {2,4,7} SA_A15 A14 DQ14 SA_D30 C5 E7 {2,4,7} {2,4,7} SA_A16 A15 DQ15 SA_D31 D7 {2,4,7} {2,4,7} SA_A17 A16 D8 E8 {2,4,7} SA_A18 A17 STS A7 {2,4,7} SA_A19 A18 B7 B6 {2,4,7} SA_A20 A19 DU1 / NC C7 C6 {2,4,7} SA_A21 A20 DU2 / nWP C8 D5 {2,4,7} SA_A22 A21 DU3 / VDDQ A8 D6 {2,4,7} SA_A23 A22 DU4 / VDDQ G1 {2,4,7} SA_A24 A23 H8 A24 H2 DU8 / VSSQ D4 nRP F1 DC3P3V nBYTE E6 DU5 / CLK G4 V_DDQ F6 A4 A DU6 / ADV V_PEN F7 A DU7 / WAIT A6 VDD_1 VDD_2 H3 F8 G8 nOE nWE B4 nCE_0 B8 nCE_1 H1 nCE_2 VSS_1 VSS_2 VSS_3 BGA B2 H4 H6 C23 0.1UF C24 0.1UF R57 0 C21 0.1UF C22 0.1UF C1 0.1UF R53 0 PXA250 Processor Reference Design Size Rev B 2.07 8 7 6 5 4 3 Date: Tuesday, February 05, 2002 2
8 1 Sheet 6 of 16 1 7 6 5 4 3 2 Copyright 2002 Intel Corporation U8 Pg. 6 CF_PWR_ON Buffer {13} 16_Bit Buffer/Line R59 Driver 100K 74LVCH162244A 47 2 {2,15} SA_nPIOW CF_nPIOW {10} R60 1A1 1Y1 46 {2,15} SA_nPOE 1A2 1Y2 3 CF_nPOE {10} D CF_nPWE {10} 100K 44 {2,15} SA_nPWE 1A3 1Y3 5 Board Control D 43 {2,15} SA_nPIOR 1A4 1Y4 6 CF_nPIOR {10} CF_GFX_RESET Register {10,15} IRDA_FSEL {9} {2} SA_nSDCS_2 41 2A1 2Y1 8 VX_nSDCS_2 {15} IRDA_MD0 {9} {2,15} SA_nPCE_2 40 CF_nPCE_2 {10} IRDA_MD1 {9} DC3P3V 2A2 2Y2 9 {2,4} SA_SDCKE_1 38 2A3 2Y3 11 VX_SDCKE_1 {15} CF_nBUS_ON 37 {2} SA_SDCLK_2 2A4 2Y4 12 VX_SDCLK_2 {15} U9 {10} CF_nPWAIT 36 SA_nPWAIT {2,15} R61 3A1 3Y1 13 {10} CF_nIOIS16 35 3A2 3Y2 14 SA_nIOIS16 {2,15} 100K {2,15} SA_nPREG 33 3A3 3Y3 16 CF_nPREG {10} 74LVCH16374A {2,15} SA_nPCE_1 32 17 CF_nPCE_1 {10} R62 3A4 3Y4 16-Bit Edge Triggered {2,5} SA_A3 VX_A3 {10,15} 100K 30 4A1 4Y1 19 D-Type Flip Flop 29 {2,5} SA_A2 4A2 4Y2 20 VX_A2 {10,15} 47 {2,4,5,7} SA_D0 1D1 2 1Q1 AUDIO_PWR_ON {2} SA_A1 27 {8} 4A3 4Y3 22 VX_A1 {10,15} {2,4,5,7} SA_D1 46 1D2 3 1Q2 26 {2} SA_A0 4A4 4Y4 23 VX_A0 {10,15} 44 {2,4,5,7} SA_D2 1D3 5 1Q3 LIGHT_PWR_ON 43 {13} {2,4,5,7} SA_D3 1D4 1Q4 6 {7} nVX_CF_OE 1 1nOE VSS_1 4 41 {2,4,5,7} SA_D4 1D5 1Q5 8 48 10 40 9 R63 2nOE VSS_2 {2,4,5,7} SA_D5 1D6 1Q6 25 DC3P3V CF_nBUS_ON 3nOE VSS_3 15 38 {2,4,5,7} SA_D6 1D7 1Q7 11 100K 24 4nOE VSS_4 21 37 {2,4,5,7} SA_D7 1D8 1Q8 12 VSS_5 28 7 VDD_1 VSS_6 34 36 13 {2,4,5,7} SA_D8 2D1 2Q1 LCD_PWR_ON {13,14} C 18 VDD_2 VSS_7 39 35 14 {2,4,5,7} SA_D9 2D2 2Q2 C 31 VDD_3 VSS_8 45 33 16 {2,4,5,7} SA_D10 2D3 2Q3 42 32 17 R64 VDD_4 {2,4,5,7} SA_D11 2D4 2Q4 {2,4,5,7} SA_D12 30 2D5 2Q5 19 100K {2,4,5,7} SA_D13 29 2D6 2Q6 20 {2,4,5,7} SA_D14 27 2Q7 22 RS232_ON 74LVCH162244APF 2D7 {10} {2,4,5,7} SA_D15 26 2D8 2Q8 23 nBCR_OE 1 R65 nBCR_WR 1nOE 48 1CLK 100K 4 DC3P3V VSS_1 24 10 2nOE VSS_2 25 15 2CLK VSS_3 RADIO_PWR_ON 21 {11} VSS_4 7 VDD_1 VSS_5 28 18 VDD_2 VSS_6 34 R66 31 VDD_3 VSS_7 39 100K 42 VDD_4 VSS_8 45 RADIO_WAKE {11} U10 74LVCH16374A DC3P3V CPLD nRED_LED B XCR3032XL-10VQ44C B Xilinx CPLD {2} SA_SDCLK_2 42 35 CF_nBUS_ON D1 A0_CLK B0 R67 {15} nNEP_FLASH_CS 43 A1 B1 34 nXCV_ADD_OE {7,13} 2 1 {7} 44 XCV_DATA_DIR A2 B2 33 SA_nCS_5 {2,15} {10,11} CPLD1_TDI CPLD1_TDO {11,13} 1.5K 1 RED DC3P3V A3_TDI B3_TDO 32 2 nGREEN_LED {3,15} MBGNT_CF_IRQ nBCR_OE A4 B4 31 SA_nCS_4 3 {2,15} nBCR_WR A5 B5 30 SA_nCS_3 5 {2,15} SA_nCS_2 {2} D2 A6 B6 28 {7} nVX_CF_OE SA_nCS_1 {2} R68 6 A7 B7 27 2 1 7 {3,10,11,13} JTAG_TMS A8_TMS B8_TCK 26 JTAG_TCK {3,10,11,13} GRN {10,15} nNEP_REG_CS SA_nCS_0 {2,15} 1.5K 8 A9 B9 25 10 {2,4,5,7,10} SA_nWE A10 B10 23 SA_A25 {2,7} {7} nXCV_DATA_OE 11 A11 B11 22 VX_nOE {7,15} SPKR_OFF 12 {8} DC3P3V {7} XCV_ADD_DIR A12 B12 21 13 {10,15} CF_IRQ_LVL2OE A13 B13 20 SA_nPCE_2 14 19 {2,15} {3,11,13,15} nRESET_OUT SA_nPCE_1 {2,15} DC3P3V A14 B14 R69 {5} nFLASH_BOOT_CS 15 A15 B15 18 SA_RD_nWR {2,15} 100K VDD_1 9 VDD_2 17 VDD_3 29 {15} SWAP_FLASH 37 IN0 41 VDD_4 R70 39 A {2,4,7} SA_nSDRAS IN1 MMC_PWR_ON {13} 38 4 A {2} SA_nSDCS_2 IN2 VSS_1 0 40 16 {2,4,5,7} SA_nSDCAS IN3 VSS_2 VSS_3 24 VSS_4 36 C29 0.1UF C30 0.1UF C31 0.1UF C32 0.1UF C27 0.1UF C28 0.1UF C25 0.1UF C26 0.1UF PXA250 Processor Reference Design XCR3032XL Size Rev B 2.07 8 7 6 5 4 3 Date: Tuesday, February 05, 2002 2
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Intel ® PXA250 and PXA210 Applicat
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Contents Contents 1 Introduction...
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Contents A.1 SA-1110 Hardware Migra
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Contents 2-7 SRAM / ROM / Flash / S
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Introduction 1 Table 1-1. Revision
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Introduction • System memory inte
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Introduction Table 1-3. Signal Pin
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Introduction Figure 1-2. PXA250 App
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Introduction Table 1-4. PXA250 Appl
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Introduction Figure 1-3. PXA210 App
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Introduction Table 1-5. PXA210 Appl
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System Memory Interface 2 This sect
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System Memory Interface Table 2-1.
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. System Memory Interface 2.4 SDRAM
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System Memory Interface Figure 2-5.
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System Memory Interface Figure 2-6.
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System Memory Interface 2.7 System
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LCD Display Controller 3 This chapt
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LCD Display Controller Figure 3-1.
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LCD Display Controller Figure 3-5.
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LCD Display Controller Note: This e
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LCD Display Controller However, typ
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USB Interface 4 4.1 Self Powered De
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MultiMediaCard (MMC) 5 The MultiMed
Page 59 and 60: MultiMediaCard (MMC) Figure 5-1. Ap
Page 61 and 62: MultiMediaCard (MMC) Warning: Conne
Page 63 and 64: AC97 6 The AC97 controller unit (AC
Page 65 and 66: I 2 C 7 The Inter-Integrated Circui
Page 67 and 68: . I2C Figure 7-2. Using an Analog S
Page 69 and 70: Power and Clocking 8 8.1 Operating
Page 71 and 72: Power and Clocking Since few system
Page 73 and 74: Power and Clocking Table 8-4. 32.76
Page 75 and 76: Power and Clocking Table 8-6. PXA25
Page 81 and 82: Power and Clocking Figure 8-2. Hard
Page 83 and 84: Power and Clocking Table 8-10. Slee
Page 85 and 86: Power and Clocking Table 8-14. Sync
Page 87 and 88: Power and Clocking Table 8-16. Vari
Page 89 and 90: Power and Clocking • Provide powe
Page 91 and 92: Power and Clocking 8.7.4 I/O 3.3 V
Page 93 and 94: JTAG/Debug Port 9 9.1 Description T
Page 95 and 96: SA-1110/Applications Processor Migr
Page 105 and 106: Example Form Factor Reference Desig
Page 107 and 108: 8 1 7 6 5 4 3 2 Copyright 2002 Inte
Page 109: 8 1 Sheet 4 of 16 1 7 6 5 4 3 2 Cop
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Page 115 and 116: 8 1 Sheet 10 of 16 1 7 6 5 4 3 2 Co
Page 117 and 118: 8 IN_PWR {10,15} D10 1 Pg. 12 7 6 5
Page 119 and 120: 8 C C 1 7 6 5 4 3 2 Copyright 2002
Page 121 and 122: 8 B B A A PXA250 Processor Referenc
Page 123 and 124: BBPXA2xx Development Baseboard Sche
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BBPXA2xx Development Baseboard Sche
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DCPXA250 Processor Card 32-bit vers
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DCPXA210 Processor Card 4 CONNECTOR
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Intel PXA250 and PXA210 Applications Processors

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