Intel PXA250 and PXA210 Applications Processors

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8 1 Pg.3 Sheet 3 of 16 1 7 6 5 4 3 2 Copyright 2002 Intel Corporation U1B Intel PXA250 Processor DC3P3V DC3P3V DC3P3V L_DD_0_GPIO58 E7 L_DD_0 L10 {13} {10,15} GPIO_0 L_DD_1_GPIO59 D7 L_DD_1 {13} {9,15} L12 USB_WAKE GPIO_1 L_DD_2_GPIO60 C7 L_DD_2 L13 {13} {10} SA_I2C_ENAB GPIO_2 L_DD_3_GPIO61 B7 L_DD_3 K14 {13} {10,15} GFX_IRQ_CF_BVD2 GPIO_3 L_DD_4_GPIO62 E6 L_DD_4 D {10} RS232_VALID J12 {13} GPIO_4 L_DD_5_GPIO63 D6 L_DD_5 D J11 {13} DNI DNI DNI {2,12} nCHRGR_PRESENT GPIO_5 L_DD_6_GPIO64 E5 L_DD_6 G15 {13} {8} AC97_IRQ GPIO_7 L_DD_7_GPIO65 A6 L_DD_7 F12 {13} {10,15} SA1111_IRQ_CF_BVD1 GPIO_9 L_DD_8_GPIO66 C5 L_DD_8 F7 {4,13} {12,15} nVBATT_LOW_IRQ GPIO_10 L_DD_9_GPIO67 A5 L_DD_9 {4,13} {13} A7 GPIO_11 L_DD_10_GPIO68 D5 L_DD_10 {6,15} MBGNT_CF_IRQ B5 {4,13} GPIO_13 L_DD_11_GPIO69 A4 L_DD_11 B4 {4,13} {13,15} MBREQ_CF_DETECT GPIO_14 L_DD_12_GPIO70 A3 L_DD_12 {4,13} {10} D12 GPIO_17 L_DD_13_GPIO71 A2 L_DD_13 {4,13} {15} BOOT_SEL_0 {15} BOOT_SEL_1 BOOT_SEL_2 {10} A16 GPIO_32 L_DD_14_GPIO72 C3 L_DD_14 {4,13} L_DD_15_GPIO73 B3 L_DD_15 {4,13} LCD Port L_FCLK_GPIO74 E8 L_FCLK {13} L_LCLK_GPIO75 D8 L_LCLK B8 {13} L_PCLK GPIO Port L_PCLK_GPIO76 A8 {13} L_BIAS_GPIO77 L_BIAS {13} H12 LAYOUT: Keep Close in DC3P3V {6,10,11,13} JTAG_TCK TCK H15 {13} CPLD2_TDO TDI a Matrix and in an H16 JTAG Y4 DNI {10,11} SA_TDO Accessible location. {6,10,11,13} JTAG_TMS H13 TMS 1 4 {11} JTAG_nTRST H11 Y1 Add Silk screen Box. R271 2 3 2 1 J13 K11 {10,11,15} nRESET_IN nRESET_OUT nRESET_OUT {6,11,13,15} C 681 C 3.6864Mhz 3.6864MHZ G16 {15} BOOT_SEL_0 G13 {15} BOOT_SEL_1 F13 DC3P3V BOOT_SEL_2 BOOT_SEL_2 nRESET_IN {10,11,15} {12} DC_PLL DC3P3V C15 0.1UF C16 0.1UF DC3P3V DC_CORE C123 0.1UF R277 0 R200 0 R21 100K R22 100K Y2 2 1 32.768KHZ K15 K16 L16 L15 L11 {12,13} SA_PWR_EN K12 nBATT_FAULT K13 nVDD_FAULT 3.6Mhz 32Khz {13} nVDD_FAULT {8,10,11,12,13,14} VBATT F11 DC_CORE VDD_1 VSS_1 C16 G7 VDD_2 VSS_2 H8 G9 H9 U2 VDD_3 VSS_3 H10 VDD_4 VSS_4 J8 J7 VDD_5 VSS_5 J9 MAX6328 K8 VDD_6 VSS_6 T1 1 K10 GND VDD_7 L6 VDD_8 VSSN_1 C2 L9 E2 VDD_9 3 DC3P3V VIN Capacitors for Core DC3P3V B B 2 RESET U3 DC3P3V MAX6328XR27-T-SC MAX811TEUS-T 4 VCC {12} PLL_SENSE A1 D4 F4 H4 K4 M4 M14 N5 N7 N9 N11 N13 P3 T16 PXTAL PEXTAL TXTAL TEXTAL VDDN_1 VDDN_2 VDDN_3 VDDN_4 VDDN_5 VDDN_6 VDDN_7 VDDN_8 VDDN_9 VDDN_10 VDDN_11 VDDN_12 VDDN_13 VDDN_14 S1 VSSQ_3 J15 PLL_VCC VSSQ_4 C14 J16 PLL_SENSE VSSQ_5 F6 RESET T2 VCCKP VSSQ_6 G8 D15 ADC_VCC VSSQ_7 G10 M11 BATT_VCC VSSQ_8 H7 J10 A DC3P3V VSSQ_9 C6 J14 Capacitors for VDDX A VDDQ_1 VSSQ_10 C10 VDDQ_2 VSSQ_11 K7 C13 VDDQ_3 VSSQ_12 K9 E14 VDDQ_4 VSSQ_13 L14 G14 VDDQ_5 BALL 12-11-00 PXA250 Processor Reference Design R262 0 TESTCLK TEST VSSN_2 VSSN_3 VSSN_4 VSSN_5 VSSN_6 VSSN_7 VSSN_8 VSSN_9 VSSN_10 VSSN_11 VSSN_12 VSSN_13 VSSN_14 VSSN_15 G11 G12 G2 J2 L2 N2 R2 R4 R6 R8 R10 R12 R14 M15 P15 VSSQ_1 C4 VSSQ_2 C8 C11 R48 0 R51 0 C125 0.1UF 4 B 1 2 Top 7A C7 0.1UF C8 0.1UF 3 3 MR RESET GND 2 1 R26 1_Ohm C6 0.1UF C9 0.1UF R27 1_Ohm C10 0.1UF C11 0.1UF C12 0.1UF C13 0.1UF C14 0.1UF R23 10K R24 10K R25 10K R18 100K R19 100K R20 100K PXA250_MBGA256 Size Rev B 2.07 8 7 6 5 4 3 Date: Tuesday, February 05, 2002 2
8 1 Sheet 4 of 16 1 7 6 5 4 3 2 Copyright 2002 Intel Corporation C17 0.1UF U4 SDRAM SYSTEM CONFIGURATION REGISTER 23 {2,5,7} SA_A10 A0 24 {2,5,7} SA_A11 A1 25 4M x 4 x 16 DC3P3V {2,5,7} SA_A12 A2 26 SDRAM {2,5,7} SA_A13 A3 29 SDRAM Bank Addressing: {2,5,7} SA_A14 A4 30 {2,5,7} SA_A15 A5 31 D {2,5,7} SA_A16 A6 SDRAM Address Bus wired for D 32 {2,5,7} SA_A17 A7 33 SA1110 legacy compatibility mode DNI {2,5,7} SA_A18 A8 34 {2,5,7} SA_A19 A9 for SDRAM Bank Addressing. 22 {2,5,7} SA_A20 A10 SD_SZ_0 {2,5,7} SA_A21 35 40 R29 A11 NC {3,13} L_DD_8 {2,5,7} SA_A24 36 A12 SA_D0 {2,5,6,7} 100K 2 DC3P3V D0 D1 4 SA_D1 {2,7} 19 5 {2,5,6,7} SA_nSDCS_0 nCS D2 SA_D2 {2,5,6,7,10} SA_nWE 16 {2,5,6,7} D3 7 SA_D3 17 {2,5,6,7} {2,5,6,7} SA_nSDCAS nCAS D4 8 SA_D4 18 {2,5,6,7} DNI {2,6,7} SA_nSDRAS nRAS D5 10 SA_D5 {2,5,6,7} D6 11 SA_D6 13 {2,5,6,7} SD_SZ_1 SA_D7 {2,5,6,7} R32 D7 {3,13} L_DD_9 {2,7} SA_SDCLK_1 38 42 D8 SA_D8 {2,5,6,7} {2,6} SA_SDCKE_1 SA_D9 {2,5,6,7} DC3P3V 100K 37 D9 44 20 {2,5,7} SA_A23 BS_0 D10 45 SA_D10 21 {2,5,6,7} {2,5,7} SA_A22 BS_1 D11 47 SA_D11 {2,7} SA_DQM_0 15 {2,5,6,7} DC3P3V LDQM D12 48 SA_D12 {2,5,6,7} {2,7} SA_DQM_1 39 UDMQ D13 50 SA_D13 {2,5,6,7} D14 51 SA_D14 {2,5,6,7} DNI D15 53 SA_D15 1 {2,5,6,7} VDD_1 FLASH_SZ_0 C 14 28 R35 VDD_2 VSS_1 {3,13} L_DD_10 C 27 VDD_3 VSS_2 41 100K DC3P3V VSS_3 54 3 VDD_Q1 VSSQ_1 6 9 VDD_Q2 VSSQ_2 12 43 VDD_Q3 VSSQ_3 46 49 VDD_Q4 VSSQ_4 52 DNI R38 FLASH_SZ_1 {3,13} L_DD_11 100K DC3P3V U5 {2,5,7} SA_A10 23 A0 24 {2,5,7} SA_A11 A1 25 4M x 4 x 16 DNI {2,5,7} SA_A12 A2 26 SDRAM {2,5,7} SA_A13 A3 29 R41 FLASH_TYPE {2,5,7} SA_A14 A4 {3,13} L_DD_12 {2,5,7} SA_A15 30 A5 100K 31 DC3P3V {2,5,7} SA_A16 A6 32 {2,5,7} SA_A17 A7 B 33 B {2,5,7} SA_A18 A8 34 {2,5,7} SA_A19 A9 22 {2,5,7} SA_A20 A10 35 40 DNI {2,5,7} SA_A21 A11 NC 36 {2,5,7} SA_A24 A12 2 SA_D16 {2,5,7} R44 D0 {3,13} L_DD_13 LCD_TYPE 4 {13} D1 SA_D17 {2,5,7} {2,7} SA_nSDCS_0 SA_D18 {2,5,7} DC3P3V 100K 19 5 nCS D2 16 {2,5,6,7,10} SA_nWE D3 7 SA_D19 {2,5,7} {2,5,6,7} 17 SA_nSDCAS nCAS D4 8 SA_D20 18 {2,5,7} {2,6,7} SA_nSDRAS nRAS D5 10 SA_D21 {2,5,7} D6 11 SA_D22 {2,5,7} D7 13 SA_D23 {2,5,7} {2,7} SA_SDCLK_1 38 42 CLK D8 SA_D24 37 {2,5,7} {2,6} SA_SDCKE_1 CKE D9 44 SA_D25 20 45 {2,5,7} {2,5,7} SA_A23 SA_D26 {2,5,7} R47 BS_0 D10 {3,13} L_DD_14 nGFX_PRESENT {13,15} 21 47 {2,5,7} SA_A22 BS_1 D11 SA_D27 {2,5,7} {2,7} SA_DQM_2 SA_D28 {2,5,7} 100K 15 48 DC3P3V DC3P3V LDQM D12 39 50 {2,7} SA_DQM_3 UDMQ D13 SA_D29 51 {2,5,7} D14 SA_D30 53 {2,5,7} D15 SA_D31 1 {2,5,7} VDD_1 14 VDD_2 VSS_1 28 27 41 A VDD_3 VSS_2 54 R50 A VSS_3 {3,13} L_DD_15 nNEP_PRESENT {13,15} 3 VDD_Q1 VSSQ_1 6 100K 9 VDD_Q2 VSSQ_2 12 43 VDD_Q3 VSSQ_3 46 49 VDD_Q4 VSSQ_4 52 PXA250 Processor Reference Design C19 0.1UF C20 0.1UF R49 10K R46 10K R45 R42 0 R40 10K R43 R39 R37 R33 0 10K 0 10K 0 10K C18 0.1UF R36 0 R34 10K R31 R30 0 R28 10K Pg. 4 Size Rev B 2.07 8 7 6 5 4 3 Date: Tuesday, February 05, 2002 2
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Intel ® PXA250 and PXA210 Applicat
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Contents Contents 1 Introduction...
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Contents A.1 SA-1110 Hardware Migra
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Contents 2-7 SRAM / ROM / Flash / S
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Introduction 1 Table 1-1. Revision
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Introduction • System memory inte
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Introduction Table 1-3. Signal Pin
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Introduction Figure 1-2. PXA250 App
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Introduction Table 1-4. PXA250 Appl
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Introduction Figure 1-3. PXA210 App
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Introduction Table 1-5. PXA210 Appl
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System Memory Interface 2 This sect
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System Memory Interface Table 2-1.
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. System Memory Interface 2.4 SDRAM
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System Memory Interface Figure 2-5.
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System Memory Interface Figure 2-6.
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System Memory Interface 2.7 System
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LCD Display Controller 3 This chapt
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LCD Display Controller Figure 3-1.
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LCD Display Controller Figure 3-5.
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LCD Display Controller Note: This e
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LCD Display Controller However, typ
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USB Interface 4 4.1 Self Powered De
Page 57 and 58: MultiMediaCard (MMC) 5 The MultiMed
Page 59 and 60: MultiMediaCard (MMC) Figure 5-1. Ap
Page 61 and 62: MultiMediaCard (MMC) Warning: Conne
Page 63 and 64: AC97 6 The AC97 controller unit (AC
Page 65 and 66: I 2 C 7 The Inter-Integrated Circui
Page 67 and 68: . I2C Figure 7-2. Using an Analog S
Page 69 and 70: Power and Clocking 8 8.1 Operating
Page 71 and 72: Power and Clocking Since few system
Page 73 and 74: Power and Clocking Table 8-4. 32.76
Page 75 and 76: Power and Clocking Table 8-6. PXA25
Page 81 and 82: Power and Clocking Figure 8-2. Hard
Page 83 and 84: Power and Clocking Table 8-10. Slee
Page 85 and 86: Power and Clocking Table 8-14. Sync
Page 87 and 88: Power and Clocking Table 8-16. Vari
Page 89 and 90: Power and Clocking • Provide powe
Page 91 and 92: Power and Clocking 8.7.4 I/O 3.3 V
Page 93 and 94: JTAG/Debug Port 9 9.1 Description T
Page 95 and 96: SA-1110/Applications Processor Migr
Page 105 and 106: Example Form Factor Reference Desig
Page 107: 8 1 7 6 5 4 3 2 Copyright 2002 Inte
Page 111 and 112: 8 1 Sheet 6 of 16 1 7 6 5 4 3 2 Cop
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Page 115 and 116: 8 1 Sheet 10 of 16 1 7 6 5 4 3 2 Co
Page 117 and 118: 8 IN_PWR {10,15} D10 1 Pg. 12 7 6 5
Page 119 and 120: 8 C C 1 7 6 5 4 3 2 Copyright 2002
Page 121 and 122: 8 B B A A PXA250 Processor Referenc
Page 123 and 124: BBPXA2xx Development Baseboard Sche
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BBPXA2xx Development Baseboard Sche
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DCPXA250 Processor Card 32-bit vers
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DCPXA210 Processor Card 4 CONNECTOR
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Intel PXA250 and PXA210 Applications Processors

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