Intel PXA250 and PXA210 Applications Processors
Intel PXA250 and PXA210 Applications Processors
Intel PXA250 and PXA210 Applications Processors
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Copyright 2002 <strong>Intel</strong> Corporation<br />
U1B<br />
<strong>Intel</strong> <strong>PXA250</strong> Processor<br />
DC3P3V DC3P3V<br />
DC3P3V<br />
L_DD_0_GPIO58<br />
E7<br />
L_DD_0<br />
L10<br />
{13}<br />
{10,15}<br />
GPIO_0<br />
L_DD_1_GPIO59<br />
D7<br />
L_DD_1 {13}<br />
{9,15}<br />
L12<br />
USB_WAKE<br />
GPIO_1<br />
L_DD_2_GPIO60<br />
C7<br />
L_DD_2<br />
L13<br />
{13}<br />
{10} SA_I2C_ENAB<br />
GPIO_2<br />
L_DD_3_GPIO61<br />
B7<br />
L_DD_3<br />
K14<br />
{13}<br />
{10,15} GFX_IRQ_CF_BVD2<br />
GPIO_3<br />
L_DD_4_GPIO62<br />
E6<br />
L_DD_4<br />
D {10} RS232_VALID<br />
J12<br />
{13}<br />
GPIO_4<br />
L_DD_5_GPIO63<br />
D6<br />
L_DD_5 D<br />
J11<br />
{13}<br />
DNI DNI DNI<br />
{2,12} nCHRGR_PRESENT<br />
GPIO_5<br />
L_DD_6_GPIO64<br />
E5<br />
L_DD_6<br />
G15<br />
{13}<br />
{8} AC97_IRQ<br />
GPIO_7<br />
L_DD_7_GPIO65<br />
A6<br />
L_DD_7<br />
F12<br />
{13}<br />
{10,15} SA1111_IRQ_CF_BVD1<br />
GPIO_9<br />
L_DD_8_GPIO66<br />
C5<br />
L_DD_8<br />
F7<br />
{4,13}<br />
{12,15} nVBATT_LOW_IRQ<br />
GPIO_10<br />
L_DD_9_GPIO67<br />
A5<br />
L_DD_9 {4,13}<br />
{13}<br />
A7<br />
GPIO_11<br />
L_DD_10_GPIO68<br />
D5<br />
L_DD_10<br />
{6,15} MBGNT_CF_IRQ<br />
B5<br />
{4,13}<br />
GPIO_13<br />
L_DD_11_GPIO69<br />
A4<br />
L_DD_11<br />
B4<br />
{4,13}<br />
{13,15} MBREQ_CF_DETECT<br />
GPIO_14<br />
L_DD_12_GPIO70<br />
A3<br />
L_DD_12 {4,13}<br />
{10}<br />
D12<br />
GPIO_17<br />
L_DD_13_GPIO71<br />
A2<br />
L_DD_13 {4,13} {15} BOOT_SEL_0<br />
{15} BOOT_SEL_1<br />
BOOT_SEL_2<br />
{10}<br />
A16<br />
GPIO_32<br />
L_DD_14_GPIO72<br />
C3<br />
L_DD_14 {4,13}<br />
L_DD_15_GPIO73<br />
B3<br />
L_DD_15 {4,13}<br />
LCD Port<br />
L_FCLK_GPIO74<br />
E8<br />
L_FCLK {13}<br />
L_LCLK_GPIO75<br />
D8<br />
L_LCLK<br />
B8<br />
{13}<br />
L_PCLK<br />
GPIO Port<br />
L_PCLK_GPIO76<br />
A8<br />
{13}<br />
L_BIAS_GPIO77<br />
L_BIAS {13}<br />
H12<br />
LAYOUT: Keep Close in<br />
DC3P3V<br />
{6,10,11,13} JTAG_TCK<br />
TCK<br />
H15<br />
{13} CPLD2_TDO<br />
TDI<br />
a Matrix <strong>and</strong> in an<br />
H16<br />
JTAG<br />
Y4<br />
DNI<br />
{10,11} SA_TDO<br />
Accessible location.<br />
{6,10,11,13} JTAG_TMS<br />
H13<br />
TMS<br />
1 4<br />
{11} JTAG_nTRST<br />
H11<br />
Y1<br />
Add Silk screen Box.<br />
R271<br />
2 3<br />
2 1<br />
J13 K11<br />
{10,11,15} nRESET_IN<br />
nRESET_OUT<br />
nRESET_OUT {6,11,13,15}<br />
C 681<br />
C<br />
3.6864Mhz<br />
3.6864MHZ<br />
G16<br />
{15}<br />
BOOT_SEL_0<br />
G13<br />
{15}<br />
BOOT_SEL_1<br />
F13<br />
DC3P3V<br />
BOOT_SEL_2<br />
BOOT_SEL_2<br />
nRESET_IN {10,11,15}<br />
{12}<br />
DC_PLL<br />
DC3P3V<br />
C15<br />
0.1UF<br />
C16<br />
0.1UF<br />
DC3P3V<br />
DC_CORE<br />
C123<br />
0.1UF<br />
R277<br />
0<br />
R200<br />
0<br />
R21<br />
100K<br />
R22<br />
100K<br />
Y2<br />
2 1<br />
32.768KHZ<br />
K15<br />
K16<br />
L16<br />
L15<br />
L11<br />
{12,13} SA_PWR_EN<br />
K12<br />
nBATT_FAULT<br />
K13<br />
nVDD_FAULT<br />
3.6Mhz<br />
32Khz<br />
{13} nVDD_FAULT<br />
{8,10,11,12,13,14} VBATT<br />
F11<br />
DC_CORE<br />
VDD_1<br />
VSS_1<br />
C16<br />
G7<br />
VDD_2<br />
VSS_2<br />
H8<br />
G9<br />
H9<br />
U2<br />
VDD_3<br />
VSS_3<br />
H10<br />
VDD_4<br />
VSS_4<br />
J8<br />
J7<br />
VDD_5<br />
VSS_5<br />
J9<br />
MAX6328<br />
K8<br />
VDD_6<br />
VSS_6<br />
T1<br />
1<br />
K10<br />
GND<br />
VDD_7<br />
L6<br />
VDD_8<br />
VSSN_1<br />
C2<br />
L9<br />
E2<br />
VDD_9<br />
3<br />
DC3P3V<br />
VIN<br />
Capacitors for Core<br />
DC3P3V<br />
B B<br />
2<br />
RESET<br />
U3<br />
DC3P3V<br />
MAX6328XR27-T-SC<br />
MAX811TEUS-T<br />
4<br />
VCC<br />
{12} PLL_SENSE<br />
A1<br />
D4<br />
F4<br />
H4<br />
K4<br />
M4<br />
M14<br />
N5<br />
N7<br />
N9<br />
N11<br />
N13<br />
P3<br />
T16<br />
PXTAL<br />
PEXTAL<br />
TXTAL<br />
TEXTAL<br />
VDDN_1<br />
VDDN_2<br />
VDDN_3<br />
VDDN_4<br />
VDDN_5<br />
VDDN_6<br />
VDDN_7<br />
VDDN_8<br />
VDDN_9<br />
VDDN_10<br />
VDDN_11<br />
VDDN_12<br />
VDDN_13<br />
VDDN_14<br />
S1<br />
VSSQ_3<br />
J15<br />
PLL_VCC<br />
VSSQ_4<br />
C14<br />
J16<br />
PLL_SENSE<br />
VSSQ_5<br />
F6<br />
RESET<br />
T2<br />
VCCKP<br />
VSSQ_6<br />
G8<br />
D15<br />
ADC_VCC<br />
VSSQ_7<br />
G10<br />
M11<br />
BATT_VCC<br />
VSSQ_8<br />
H7<br />
J10<br />
A DC3P3V<br />
VSSQ_9<br />
C6<br />
J14<br />
Capacitors for VDDX<br />
A<br />
VDDQ_1<br />
VSSQ_10<br />
C10<br />
VDDQ_2<br />
VSSQ_11<br />
K7<br />
C13<br />
VDDQ_3<br />
VSSQ_12<br />
K9<br />
E14<br />
VDDQ_4<br />
VSSQ_13<br />
L14<br />
G14<br />
VDDQ_5 BALL 12-11-00<br />
<strong>PXA250</strong> Processor Reference Design<br />
R262<br />
0<br />
TESTCLK<br />
TEST<br />
VSSN_2<br />
VSSN_3<br />
VSSN_4<br />
VSSN_5<br />
VSSN_6<br />
VSSN_7<br />
VSSN_8<br />
VSSN_9<br />
VSSN_10<br />
VSSN_11<br />
VSSN_12<br />
VSSN_13<br />
VSSN_14<br />
VSSN_15<br />
G11<br />
G12<br />
G2<br />
J2<br />
L2<br />
N2<br />
R2<br />
R4<br />
R6<br />
R8<br />
R10<br />
R12<br />
R14<br />
M15<br />
P15<br />
VSSQ_1<br />
C4<br />
VSSQ_2<br />
C8<br />
C11<br />
R48<br />
0<br />
R51<br />
0<br />
C125<br />
0.1UF<br />
4<br />
B<br />
1 2<br />
Top<br />
7A<br />
C7<br />
0.1UF<br />
C8<br />
0.1UF<br />
3<br />
3<br />
MR<br />
RESET<br />
GND<br />
2<br />
1<br />
R26<br />
1_Ohm<br />
C6<br />
0.1UF<br />
C9<br />
0.1UF<br />
R27<br />
1_Ohm<br />
C10<br />
0.1UF<br />
C11<br />
0.1UF<br />
C12<br />
0.1UF<br />
C13<br />
0.1UF<br />
C14<br />
0.1UF<br />
R23<br />
10K<br />
R24<br />
10K<br />
R25<br />
10K<br />
R18<br />
100K<br />
R19<br />
100K<br />
R20<br />
100K<br />
<strong>PXA250</strong>_MBGA256<br />
Size Rev<br />
B<br />
2.07<br />
8<br />
7<br />
6<br />
5<br />
4<br />
3<br />
Date:<br />
Tuesday, February 05, 2002<br />
2
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