Intel PXA250 and PXA210 Applications Processors
Intel PXA250 and PXA210 Applications Processors Intel PXA250 and PXA210 Applications Processors
8 D D A A PXA250 Processor Reference Design Rev 2.07 1 Pg.1 Sheet 1 of 16 1 7 6 5 4 3 2 Copyright 2002 Intel Corporation Example Form Factor Reference Design for PXA250 Page Description C C 1 Cover Sheet 2-3 PXA250 Processor 4 SDRAM, System Configuration Register 5 Intel Flash Memory (BGA) 6 Buffer, CPLD, Board Control Register 7 Transceivers 8 Audio Codec, Audio AMP 9 Headset Jack, Microphone, Stereo Jack, Speaker, Dual Axis Accelerometer, IrDA, USB 10 Basestation Hdr, RS232 Xcvr, CF Socket, Function Switches 11 SD socket, Radio Header, JTAG Port 12 Boost Buck Power , Battery Header, Battery On Jumper 13 LCD CPLD, LCD Power, Back Light Connector 14 LCD Connectors, 9 Channel Buffer, Touch Screen Connector 15 Bus Connectors, 2-140 Pin 16 Schematic Revision Page B B Size Rev B 2.07 8 7 6 5 4 3 Date: Tuesday, February 05, 2002 2
8 1 7 6 5 4 3 2 Copyright 2002 Intel Corporation 22.1 R256 {6,15} SA_nCS_5 C12 {4,5,7} SA_A20 {9} SA_UDCP 10K B12 USB Ch R257 22.1 {9} SA_UDCN nCS_0 N8 SA_nCS_0 {6,15} {4,5,7} SA_A21 nCS_1_GPIO15 T8 SA_nCS_1 C15 P9 {6} {9} IR_TXD SA_nCS_2 {6} R267 22.1 R258 IR_TXD_GPIO47 IrDA Ch nCS_2_GPIO78 {6,15} SA_nPCE_1 {4,5,7} SA_A22 {9} IR_RXD B15 IR_RXD_GPIO46 nCS_3_GPIO79 T9 SA_nCS_3 {6,15} 100K R13 R259 22.1 nCS_4_GPIO80 SA_nCS_4 B14 {6,15} {4,5,7} SA_A23 {11} SA_BT_RTS BT_RTS_GPIO45 nCS_5_GPIO33 T13 SA_nCS_5 A15 {6,15} R268 22.1 R260 {11} SA_BT_CTS BT_CTS_GPIO44 BT Ch {6,15} SA_nPCE_2 D13 {4,5,7} SA_A24 {11,15} SA_BT_TXD BT_TXD_GPIO43 {11,15} SA_BT_RXD SA_DQM_0 {4,7} 100K B13 M8 R261 22.1 BT_RXD_GPIO42 DQM_0 {6,7} SA_A25 DQM_1 B1 SA_DQM_1 B9 B2 {4,7} SA_DQM_2 {4,7} R269 22.1 EXTCLK_GPIO27 DQM_2 {6,15} SA_RD_nWR E9 R10 SFRM_C_GPIO24 DQM_3 L7 SA_DQM_3 {4,7} 100K F9 {11} RADIO_RI SCLK_C_GPIO23 0 R9 D9 TXD_C_GPIO25 F1 SA_nSDCS_0 {4,7} SSP Ch nSDCS_0 A9 G6 R281 {11} RADIO_DTR RXD_C_GPIO26 nSDCS_1 {3,12} nCHRGR_PRESENT R8 0 nSDCS_2 G3 SA_nSDCS_2 {6} 100K D14 F2 {11} RADIO_DSR MMCCMD 0 MMC nSDCS_3 B16 R7 MMCDAT H14 E4 R272 {11} RADIO_DCD MMCCLK_GPIO6 SDCKE_0 SA_SDCKE_0 {15} F14 E3 R6 0 MMCCS0_GPIO8 SDCKE_1 SA_SDCKE_1 {4,6} {3,6,15} MBGNT_CF_IRQ B6 {11} MMC_WP nMMCCD_GPIO12 4.99K 0 SDCLK_0 D2 SA_SDCLK_0 {5,15} B10 F5 {10} SA_FF_RI FF_RI_GPIO38 SA_SDCLK_1 {4,7} A12 FF Ch SDCLK_1 D1 R148 {10} SA_FF_DCD FF_DCD_GPIO36 SDCLK_2 SA_SDCLK_2 {6} B11 {11} RADIO_RXD_C {10} SA_FF_DSR FF_DSR_GPIO37 0 F10 E1 SA_nSDRAS {4,6,7} DNI {10} SA_FF_DTR FF_DTR_GPIO40 nSDRAS F8 F3 {10} SA_FF_RTS FF_RTS_GPIO41 nSDCAS SA_nSDCAS {4,5,6,7} A14 {10} SA_FF_CTS FF_CTS_GPIO35 R11 E13 G5 {10,15} SA_FF_TXD FF_TXD_GPIO39 nOE SA_nOE A13 G4 {5,7} {11} SA_MMCMD {10,15} SA_FF_RXD FF_RXD_GPIO34 nWE SA_nWE {4,5,6,7,10} DC3P3V R205 Pg.2 {6} SA_A0 R237 22.1 U1A {6} SA_A1 R1 22.1 R238 {6,15} SA_nPWAIT {5,6} SA_A2 Intel PXA250 Processor 100K R239 22.1 G1 N4 {5,6} SA_A3 A_0 D_0 SA_D0 H2 M5 {4,5,6,7} SA_D1 {4,5,6,7} R2 22.1 R240 A_1 D_1 {6,15} SA_nIOIS16 H1 {5,7} SA_A4 A_2 D_2 L5 SA_D2 {4,5,6,7} SA_D3 {4,5,6,7} 100K H6 T6 R241 22.1 A_3 D_3 J6 {5,7} SA_A5 A_4 D_4 N6 SA_D4 J5 T7 {4,5,6,7} SA_D5 {4,5,6,7} R3 22.1 R242 A_5 D_5 {15} SA_RDY J3 {5,7} SA_A6 A_6 D_6 M6 SA_D6 {4,5,6,7} SA_D7 {4,5,6,7} 100K J1 Address and Data Buses M7 R243 22.1 A_7 D_7 {5,7} SA_A7 K1 M9 SA_D8 {4,5,6,7} R4 A_8 D_8 K2 T10 22.1 R244 A_9 D_9 SA_D9 {10,12,15} SA_I2C_SCL K5 R9 {4,5,6,7} {5,7} SA_A8 SA_D10 {4,5,6,7} 4.99K A_10 D_10 K6 T11 R245 22.1 A_11 D_11 SA_D11 L1 {4,5,6,7} {5,7} SA_A9 SA_D12 {4,5,6,7} R5 A_12 D_12 P11 L3 N10 22.1 R246 A_13 D_13 SA_D13 {10,12,15} SA_I2C_SDA M1 {4,5,6,7} {4,5,7} SA_A10 A_14 D_14 T12 SA_D14 M3 {4,5,6,7} SA_D15 {4,5,6,7} 4.99K R247 22.1 A_15 D_15 M10 N3 {4,5,7} SA_A11 A_16 D_16 H3 SA_D16 P1 {4,5,7} SA_D17 {4,5,7} R137 22.1 R248 A_17 D_17 H5 {6} SA_nCS_1 {4,5,7} SA_A12 R1 A_18 D_18 J4 SA_D18 {4,5,7} 100K P2 R249 22.1 A_19 D_19 K3 SA_D19 R3 {4,5,7} {4,5,7} SA_A13 A_20 D_20 L4 SA_D20 T4 {4,5,7} SA_D21 {4,5,7} R263 22.1 R250 A_21 D_21 M2 {6} SA_nCS_2 R5 {4,5,7} SA_A14 A_22 D_22 N1 SA_D22 {4,5,7} SA_D23 {4,5,7} 100K P5 R251 22.1 A_23 D_23 T3 T5 {4,5,7} SA_A15 A_24 D_24 P6 SA_D24 P4 R7 {4,5,7} SA_D25 {4,5,7} R264 22.1 R252 A_25 D_25 {6,15} SA_nCS_3 {4,5,7} SA_A16 D_26 P7 SA_D26 {4,5,7} SA_D27 {4,5,7} 100K R253 22.1 D_27 P8 {4,5,7} SA_A17 D_28 L8 SA_D28 {4,5,7} SA_D29 {4,5,7} R265 22.1 R254 D_29 P10 {6,15} SA_nCS_4 {4,5,7} SA_A18 D_30 R11 SA_D30 {4,5,7} 10K D11 R255 22.1 {10,12,15} SA_I2C_SCL SCL SA_D31 I2C D_31 P12 A11 {4,5,7} {4,5,7} SA_A19 {10,12,15} SA_I2C_SDA SDA R266 D D C C B B R12 47.5 P13 D3 {11} SA_MMDAT {6,15} SA_nPOE nPOE_GPIO48 RD_nWR SA_RD_nWR {6,15} 47.5 R13 {6,15} SA_nPWE T14 nPWE_GPIO49 RDY_GPIO18 C1 SA_RDY {15} {11} SA_MMCCLK {6,15} SA_nPIOR T15 nPIOR_GPIO50 R15 N15 47.5 {6,15} SA_nPIOW nPIOW_GPIO51 DVAL_0_GPIO21 GPIO_21 {10,11} {11} MMC_CS0 {6,15} SA_nPCE_1 P14 nPCE_1_GPIO52 DVAL_1_GPIO22 M12 GPIO_22 {10,11} {6,15} SA_nPCE_2 R16 nPCE_2_GPIO53 DREQ_0_GPIO20 N12 GPIO_20 P16 N14 {10,11} {11,13} nMMC_DETECT {15} SA_PSKTSEL PSKTSEL_GPIO54 DREQ_1_GPIO19 GPIO_19 {10,11} {6,15} SA_nPREG M13 nPREG_GPIO55 N16 {6,15} SA_nPWAIT nPWAIT_GPIO56 M16 D10 {6,15} SA_nIOIS16 nI0IS16_GPIO57 SA_nAC97_RESET {8} AC97 nAC97_RESET SYNC_GPIO31 E11 SA_SYNC F15 A10 {8} NC1 SDATA_OUT_GPIO30 SA_SDATA_OUT {8} D16 NC2 SDATA_IN0_GPIO29 E10 SA_SDATA_IN {8} E15 NC3 BITCLK_GPIO28 C9 SA_BITCLK E16 {8} PXA250 Processor Reference Design NC4 F16 NC5 PWM_0_GPIO16 E12 SA_PWM_0 {13} A A 8 7 6 5 4 CARD Interface Memory Control Pulse Width PXA250_MBGA256 3 Size Rev B 2.07 Date: Tuesday, February 05, 2002 2 Sheet 2 of 16 1
- Page 55 and 56: USB Interface 4 4.1 Self Powered De
- Page 57 and 58: MultiMediaCard (MMC) 5 The MultiMed
- Page 59 and 60: MultiMediaCard (MMC) Figure 5-1. Ap
- Page 61 and 62: MultiMediaCard (MMC) Warning: Conne
- Page 63 and 64: AC97 6 The AC97 controller unit (AC
- Page 65 and 66: I 2 C 7 The Inter-Integrated Circui
- Page 67 and 68: . I2C Figure 7-2. Using an Analog S
- Page 69 and 70: Power and Clocking 8 8.1 Operating
- Page 71 and 72: Power and Clocking Since few system
- Page 73 and 74: Power and Clocking Table 8-4. 32.76
- Page 75 and 76: Power and Clocking Table 8-6. PXA25
- Page 77 and 78: Power and Clocking Table 8-6. PXA25
- Page 79 and 80: Power and Clocking Table 8-6. PXA25
- Page 81 and 82: Power and Clocking Figure 8-2. Hard
- Page 83 and 84: Power and Clocking Table 8-10. Slee
- Page 85 and 86: Power and Clocking Table 8-14. Sync
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8<br />
D D<br />
A A<br />
<strong>PXA250</strong> Processor Reference Design<br />
Rev 2.07<br />
1<br />
Pg.1<br />
Sheet 1 of 16<br />
1<br />
7<br />
6<br />
5<br />
4<br />
3<br />
2<br />
Copyright 2002 <strong>Intel</strong> Corporation<br />
Example Form Factor Reference Design for <strong>PXA250</strong><br />
Page Description<br />
C C<br />
1 Cover Sheet<br />
2-3 <strong>PXA250</strong> Processor<br />
4 SDRAM, System Configuration Register<br />
5 <strong>Intel</strong> Flash Memory (BGA)<br />
6 Buffer, CPLD, Board Control Register<br />
7 Transceivers<br />
8 Audio Codec, Audio AMP<br />
9 Headset Jack, Microphone, Stereo Jack, Speaker, Dual Axis Accelerometer, IrDA, USB<br />
10 Basestation Hdr, RS232 Xcvr, CF Socket, Function Switches<br />
11 SD socket, Radio Header, JTAG Port<br />
12 Boost Buck Power , Battery Header, Battery On Jumper<br />
13 LCD CPLD, LCD Power, Back Light Connector<br />
14 LCD Connectors, 9 Channel Buffer, Touch Screen Connector<br />
15 Bus Connectors, 2-140 Pin<br />
16 Schematic Revision Page<br />
B B<br />
Size Rev<br />
B<br />
2.07<br />
8<br />
7<br />
6<br />
5<br />
4<br />
3<br />
Date:<br />
Tuesday, February 05, 2002<br />
2
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