Intel PXA250 and PXA210 Applications Processors
Intel PXA250 and PXA210 Applications Processors
Intel PXA250 and PXA210 Applications Processors
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SA-1110/<strong>Applications</strong> Processor Migration<br />
A.2.1<br />
Software Compatibility<br />
Because the <strong>PXA250</strong> applications processor uses <strong>Intel</strong>® XScale microarchitecture, the <strong>PXA250</strong><br />
applications processor has a different pipeline length relative to the SA-1110. This effects code<br />
performance when migrating between the two devices varies because of the number of clock cycles<br />
needed for execution. Any application that relies on specific cycle counts, or has specific timing<br />
components, will show a difference in performance.<br />
The <strong>PXA250</strong> applications processor features: larger caches, Branch target buffering, <strong>and</strong> faster<br />
multiplication, <strong>and</strong> so many applications run faster than the SA-1110 when running at the same<br />
clock frequency.<br />
A.2.2<br />
Address space<br />
The physical address mapping of gross memory regions is not compatible between the <strong>PXA250</strong><br />
applications processor <strong>and</strong> SA-1110. For example, on the <strong>PXA250</strong> applications processor, Static<br />
chip selects 4 <strong>and</strong> 5 are lower in memory than PCMCIA, on the SA-1110 they are higher in the<br />
memory space.<br />
Changes of this kind could be managed by the Operating System remapping virtual memory pages<br />
to new physical addresses. This assumes that the Operating System has basic support for virtual<br />
memory, but not if this could be managed by initialization code modifications effecting the same<br />
change.<br />
More significantly, memory-mapped registers may have different names, new addresses <strong>and</strong><br />
different functionality. This impacts all device drivers <strong>and</strong> register-level firmware, that at a<br />
minimum, requires re-mapping register address <strong>and</strong> changing the default configuration.<br />
A.2.3<br />
Page Table Changes<br />
There are differences in the virtual memory Page Table Descriptors between the SA-1110 <strong>and</strong> the<br />
<strong>PXA250</strong> applications processors that impact software execution speed. A new bit has been added<br />
to differentiate ARM* compliant operation modes from some features <strong>Intel</strong> includes such as access<br />
to the Mini-Data-Cache.<br />
If any software attempts to explicitly control page table modifications, normally the domain of the<br />
Operating System, then that software may need annotation to allow for the extra opportunities the<br />
<strong>PXA250</strong> applications processor offers.<br />
Any SA-1110 code that explicitly uses the Mini-Data-Cache is executed correctly, but it's ability to<br />
utilize a different cache is lost without a page table bit being changed. The impact here is<br />
performance not functionality.<br />
A.2.4<br />
Configuration registers<br />
There are numerous device configuration changes in the <strong>PXA250</strong> applications processor. You must<br />
now select the configuration options for clock speeds such as Turbo Mode. This requirement is not<br />
found on the SA-1110.<br />
A-6 <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide