Intel PXA250 and PXA210 Applications Processors

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Introduction s Figure 1-1. Applications Processor Block Diagram RTC OS Timer PWM(2) Color or Grayscale LCD Controller Memory Controller General Purpose I/O Int. Controller Clocks & Power Man. I 2 S I 2 C AC97 UART1 UART2 Slow IrDA Fast IrDA Peripheral Bus DMA Controller and Bridge System Bus Megacell Core Variable Latency I/O Control PCMCIA & CF Control Dynamic Memory Control Static Memory Control ASIC XCVR SDRAM/ SMROM 4 banks ROM/ Flash/ SRAM 4 banks Socket 0 Socket 1 SSP USB Client MMC 3.6864 MHz Osc 32.768 KHz Osc A8651-01 The PXA250 applications processor package is: 256 pin, 17x17 mBGA – 32-bit functionality. The PXA210 applications processor package is: 225 pin, 13x13 MMAP – 16-bit functionality, a subset of the PXA250 applications processor feature set. Section 1.2.1, “Package Introduction” contains a breakdown of the features supported by the two different packages. 1.2 Package Information This section describes the package types, pinouts, and signal descriptions. 1.2.1 Package Introduction Package features of the PXA250 applications processor are: • Core frequencies supported - 100 MHz - 400 MHz 1-2 PXA250 and PXA210 Applications Processors Design Guide
Introduction • System memory interface —100MHz SDRAM — 4 MB to 256 MB of SDRAM memory — Support for 16, 64, 128, or 256 Mbit DRAM technologies — 4 Banks of SDRAM, each supporting 64 MB of memory — Clock enable (1 CKE pin is provided to put the entire SDRAM interface into self refresh) — Supports as many as 6 static memory devices (SRAM, Flash, or VLIO) • PCMCIA/Compact Flash card control pins • LCD Controller pins • Full Function UART • Bluetooth UART • MMC Controller pins • SSP Pins • USB Client Pins • AC’97 Controller Pins • Standard UART Pins • I 2 C Controller pins • PWM pins • 15 dedicated GPIOs pins • Integrated JTAG support Package features of the PXA210 applications processor are: • Core frequencies supported – 100 MHz, 133 MHz, 200 MHzSystem memory interface — 100 MHz SDRAM, 16-bit only — 2 MB to 128 MB of SDRAM memory — Support for 16, 64, 128, or 256 Mbit DRAM technologies — 2 Banks of SDRAM, each supporting 64 MB of memory — Supports as many as 6 static memory devices (SRAM, Flash, or VLIO) • Clock enable (1 CKE pin is provided to put the entire SDRAM interface into self refresh) • LCD Controller pins • Bluetooth UART • MMC Controller pins • SSP Pins • USB Client Pins • AC97 Controller Pins • Standard UART Pins PXA250 and PXA210 Applications Processors Design Guide 1-3
Page 1 and 2: Intel ® PXA250 and PXA210 Applicat
Page 3 and 4: Contents Contents 1 Introduction...
Page 5 and 6: Contents A.1 SA-1110 Hardware Migra
Page 7 and 8: Contents 2-7 SRAM / ROM / Flash / S
Page 9: Introduction 1 Table 1-1. Revision
Page 13 and 14: Introduction Table 1-3. Signal Pin
Page 19 and 20: Introduction Figure 1-2. PXA250 App
Page 21 and 22: Introduction Table 1-4. PXA250 Appl
Page 23 and 24: Introduction Figure 1-3. PXA210 App
Page 25 and 26: Introduction Table 1-5. PXA210 Appl
Page 27 and 28: System Memory Interface 2 This sect
Page 29 and 30: System Memory Interface Table 2-1.
Page 31 and 32: . System Memory Interface 2.4 SDRAM
Page 39 and 40: System Memory Interface Figure 2-5.
Page 41 and 42: System Memory Interface Figure 2-6.
Page 43 and 44: System Memory Interface 2.7 System
Page 45 and 46: LCD Display Controller 3 This chapt
Page 47 and 48: LCD Display Controller Figure 3-1.
Page 49 and 50: LCD Display Controller Figure 3-5.
Page 51 and 52: LCD Display Controller Note: This e
Page 53 and 54: LCD Display Controller However, typ
Page 55 and 56: USB Interface 4 4.1 Self Powered De
Page 57 and 58: MultiMediaCard (MMC) 5 The MultiMed
Page 59 and 60: MultiMediaCard (MMC) Figure 5-1. Ap
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MultiMediaCard (MMC) Warning: Conne
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AC97 6 The AC97 controller unit (AC
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I 2 C 7 The Inter-Integrated Circui
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. I2C Figure 7-2. Using an Analog S
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Power and Clocking 8 8.1 Operating
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Power and Clocking Since few system
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Power and Clocking Table 8-4. 32.76
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Power and Clocking Table 8-6. PXA25
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Power and Clocking Figure 8-2. Hard
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Power and Clocking Table 8-10. Slee
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Power and Clocking Table 8-14. Sync
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Power and Clocking Table 8-16. Vari
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Power and Clocking • Provide powe
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Power and Clocking 8.7.4 I/O 3.3 V
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JTAG/Debug Port 9 9.1 Description T
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SA-1110/Applications Processor Migr
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Example Form Factor Reference Desig
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8 1 7 6 5 4 3 2 Copyright 2002 Inte
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8 1 Sheet 4 of 16 1 7 6 5 4 3 2 Cop
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8 1 Sheet 10 of 16 1 7 6 5 4 3 2 Co
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8 IN_PWR {10,15} D10 1 Pg. 12 7 6 5
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8 C C 1 7 6 5 4 3 2 Copyright 2002
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8 B B A A PXA250 Processor Referenc
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BBPXA2xx Development Baseboard Sche
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BBPXA2xx Development Baseboard Sche
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DCPXA250 Processor Card 32-bit vers
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DCPXA210 Processor Card 4 CONNECTOR
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Intel PXA250 and PXA210 Applications Processors

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