Intel PXA250 and PXA210 Applications Processors

Intel ® PXA250 and PXA210 

Applications Processors 

Design Guide 

February, 2002 

Order Number: 278523-001

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whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to 

fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not 

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Intel may make changes to specifications and product descriptions at any time, without notice. 

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for 

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. 

The PXA250 and PXA210 applications processors may contain design defects or errors known as errata which may cause the product to deviate from 

published specifications. Current characterized errata are available on request. 

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Copyright © Intel Corporation, 2002 

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ii 

PXA250 and PXA210 Applications Processors Design Guide

Contents 

Contents 

1 Introduction.................................................................................................................................1-1 

1.1 Functional Overview ..........................................................................................................1-1 

1.2 Package Information..........................................................................................................1-2 

1.2.1 Package Introduction ............................................................................................1-2 

1.2.2 Signal Pin Descriptions.........................................................................................1-4 

2 System Memory Interface ..........................................................................................................2-1 

2.1 Overview............................................................................................................................2-1 

2.2 SDRAM Interface...............................................................................................................2-3 

2.3 SDRAM memory wiring diagram .......................................................................................2-3 

2.4 SDRAM Support ................................................................................................................2-5 

2.5 SDRAM Address Mapping.................................................................................................2-6 

2.6 Static Memory....................................................................................................................2-7 

2.6.1 Overview...............................................................................................................2-7 

2.6.2 Boot Time Defaults ...............................................................................................2-8 

2.6.3 SRAM / ROM / Flash / Synchronous Fast Flash Memory Options .......................2-9 

2.6.4 Variable Latency I/O Interface Overview ..............................................................2-9 

2.6.5 External Logic for PCMCIA Implementation .......................................................2-11 

2.6.6 DMA / Companion Chip Interface .......................................................................2-14 

2.7 System Memory Layout Guidelines .................................................................................2-17 

2.7.1 System Memory Topologies (Min and Max Simulated Loading).........................2-17 

2.7.2 System Memory Recommended Trace Lengths.................................................2-18 

3 LCD Display Controller ..............................................................................................................3-1 

3.1 LCD Display Overview.......................................................................................................3-1 

3.2 Passive (DSTN) Displays ..................................................................................................3-1 

3.2.1 Typical Connections for Passive Panel Displays..................................................3-2 

3.2.1.1 Passive Monochrome Single Panel Displays........................................3-2 

3.2.1.2 Passive Monochrome Single Panel Displays, Double-Pixel Data.........3-3 

3.2.1.3 Passive Monochrome Dual Panel Displays ..........................................3-3 

3.2.1.4 Passive Color Single Panel Displays ....................................................3-4 

3.2.1.5 Passive Color Dual Panel Displays.......................................................3-4 

3.3 Active (TFT) Displays ........................................................................................................3-5 

3.3.1 Typical connections for Active Panel Displays......................................................3-6 

3.4 PXA250 Pinout ..................................................................................................................3-7 

3.5 Additional Design Considerations......................................................................................3-8 

3.5.1 Contrast Voltage ...................................................................................................3-8 

3.5.2 Backlight Inverter ..................................................................................................3-8 

3.5.3 Signal Routing and Buffering ................................................................................3-8 

3.5.4 Panel Connector ...................................................................................................3-9 

4 USB Interface ..............................................................................................................................4-1 

4.1 Self Powered Device .........................................................................................................4-1 

4.1.1 Operation if GPIOn and GPIOx are Different Pins................................................4-1 

4.1.2 Operation if GPIOn and GPIOx are the Same Pin................................................4-2 

4.2 Bus Powered Device .........................................................................................................4-2 

PXA250 and PXA210 Applications Processors Design Guide 

iii

Contents 

5 MultiMediaCard (MMC)...............................................................................................................5-1 

5.1 Schematics ........................................................................................................................5-1 

5.1.1 Signal Description.................................................................................................5-1 

5.1.2 How to Wire ..........................................................................................................5-2 

5.1.2.1 SDCard Socket .....................................................................................5-4 

5.1.2.2 MMC Socket .........................................................................................5-4 

5.1.3 Simplified Schematic ............................................................................................5-5 

5.1.4 Pull-up and Pull-down...........................................................................................5-6 

5.2 Utilized Features................................................................................................................5-6 

6 AC97 ............................................................................................................................................6-1 

6.1 Schematics ........................................................................................................................6-1 

6.2 Layout................................................................................................................................6-2 

7 I2C................................................................................................................................................7-1 

7.1 Schematics ........................................................................................................................7-1 

7.1.1 Signal Description.................................................................................................7-1 

7.1.2 Digital-to-Analog Converter (DAC) .......................................................................7-2 

7.1.3 Other Uses of I2C .................................................................................................7-2 

7.1.4 Pull-Ups and Pull-Downs ......................................................................................7-3 

7.2 Utilized Features................................................................................................................7-4 

8 Power and Clocking ...................................................................................................................8-1 

8.1 Operating Conditions.........................................................................................................8-1 

8.2 Electrical Specifications .....................................................................................................8-2 

8.3 Power Consumption Specifications ...................................................................................8-2 

8.4 Oscillator Electrical Specifications .....................................................................................8-4 

8.4.1 32.768 kHz Oscillator Specifications ....................................................................8-4 

8.4.2 3.6864 MHz Oscillator Specifications ...................................................................8-5 

8.5 Reset and Power AC Timing Specifications ......................................................................8-6 

8.5.1 Power Supply Connectivity ...................................................................................8-6 

8.5.2 Power On Timing ................................................................................................8-11 

8.5.3 Hardware Reset Timing ......................................................................................8-12 

8.5.4 Watchdog Reset Timing .....................................................................................8-13 

8.5.5 GPIO Reset Timing.............................................................................................8-13 

8.5.6 Sleep Mode Timing.............................................................................................8-14 

8.6 Memory Bus and PCMCIA AC Specifications .................................................................8-15 

8.7 Example Form Factor Reference Design Power Delivery Example ................................8-20 

8.7.1 Power System.....................................................................................................8-20 

8.7.1.1 Power System Configuration ..............................................................8-21 

8.7.2 CORE Power ......................................................................................................8-22 

8.7.3 PLL Power ..........................................................................................................8-22 

8.7.4 I/O 3.3 V Power ..................................................................................................8-23 

8.7.5 Peripheral 5.5 V Power.......................................................................................8-23 

9 JTAG/Debug Port........................................................................................................................9-1 

9.1 Description.........................................................................................................................9-1 

9.2 Schematics ........................................................................................................................9-1 

9.3 Layout................................................................................................................................9-2 

A SA-1110/Applications Processor Migration ............................................................................ A-1 

iv 


Contents 

A.1 SA-1110 Hardware Migration Issues ................................................................................ A-2 

A.1.1 Hardware Compatibility........................................................................................ A-2 

A.1.2 Signal Changes ................................................................................................... A-2 

A.1.3 Power Delivery..................................................................................................... A-4 

A.1.4 Package............................................................................................................... A-4 

A.1.5 Clocks .................................................................................................................. A-4 

A.1.6 UCB1300 ............................................................................................................. A-5 

A.2 SA-1110 to PXA250 Software Migration Issues ............................................................... A-5 

A.2.1 Software Compatibility ......................................................................................... A-6 

A.2.2 Address space ..................................................................................................... A-6 

A.2.3 Page Table Changes ........................................................................................... A-6 

A.2.4 Configuration registers......................................................................................... A-6 

A.2.5 DMA..................................................................................................................... A-7 

A.3 Using New PXA250 Features ........................................................................................... A-7 

A.3.1 Intel® XScale Microarchitecture....................................................................... A-8 

A.3.2 Debugging ........................................................................................................... A-8 

A.3.3 Cache Attributes .................................................................................................. A-8 

A.3.4 Other features...................................................................................................... A-8 

A.3.5 Conclusion ........................................................................................................... A-9 

B Example Form Factor Reference Design Schematic Diagrams ............................................ B-1 

B.1 Notes ................................................................................................................................ B-1 

B.2 Schematic Diagrams......................................................................................................... B-1 

C BBPXA2xx Development Baseboard Schematic Diagram .................................................... C-1 

C.1 Schematic Diagram .......................................................................................................... C-1 

D PXA250 Processor Card Schematic Diagram ......................................................................... D-1 

D.1 Schematic Diagram .......................................................................................................... D-1 

E PXA210 Processor Card Schematic Diagram ......................................................................... E-1 

E.1 Schematic Diagram .......................................................................................................... E-1 


v

Contents 

Figures 

1-1 Applications Processor Block Diagram......................................................................................1-2 

1-2 PXA250 Applications Processor..............................................................................................1-11 

1-3 PXA210 Applications Processor..............................................................................................1-15 

2-1 General Memory Interface Configuration ..................................................................................2-2 

2-2 SDRAM Memory System Example............................................................................................2-4 

2-3 32-Bit Variable Latency I/O Read Timing (Burst-of-Four, One Wait Cycle Per Beat)..............2-10 

2-4 Expansion Card External Logic for a Two-Socket Configuration.............................................2-12 

2-5 Expansion Card External Logic for a One-Socket Configuration.............................................2-13 

2-6 Alternate Bus Master Mode .....................................................................................................2-15 

2-7 Variable Latency I/O ................................................................................................................2-16 

2-8 CS, CKE, DQM, CLK, MA minimum loading topology.............................................................2-17 

2-9 CS, CKE, DQM, CLK, MA Maximum Loading Topology .........................................................2-17 

2-10MD Minimum Loading Topology..............................................................................................2-17 

2-11MD maximum loading topology ...............................................................................................2-18 

3-1 Single Panel Monochrome Passive Display Typical Connection ..............................................3-3 

3-2 Passive Monochrome Single Panel Displays, Double-Pixel Data Typical Connection..............3-3 

3-3 Passive Monochrome Dual Panel Displays Typical Connection ...............................................3-4 

3-4 Passive Color Single Panel Displays Typical Connection .........................................................3-4 

3-5 Passive Color Dual Panel Displays Typical Connection............................................................3-5 

3-6 Active Color Display Typical Connection...................................................................................3-7 

4-1 Self Powered Device .................................................................................................................4-1 

5-1 Applications Processor MMC and SDCard Signal Connections................................................5-3 

5-2 Applications Processor MMC to SDCard Simplified Signal Connection....................................5-5 

6-1 AC97 connection .......................................................................................................................6-1 

7-1 Linear Technology DAC with I2C Interface ...............................................................................7-2 

7-2 Using an Analog Switch to Allow a Second CF Card ................................................................7-3 

7-3 I 2 C Pull-Ups and Pull-Downs.....................................................................................................7-3 

8-1 Power-On Reset Timing ..........................................................................................................8-12 

8-2 Hardware Reset Timing...........................................................................................................8-13 

8-3 GPIO Reset Timing .................................................................................................................8-13 

8-4 Sleep Mode Timing..................................................................................................................8-14 

8-5 Example Form Factor Reference Design Power System Design............................................8-22 

9-1 JTAG/Debug Port Wiring Diagram ............................................................................................9-1 

Tables 

1-1 Revision History.........................................................................................................................1-1 

1-2 Related Documentation .............................................................................................................1-1 

1-3 Signal Pin Descriptions..............................................................................................................1-4 

1-4 PXA250 Applications Processor Pinout — Ballpad Number Order .........................................1-12 

1-5 PXA210 Applications Processor Pinout — Ballpad Number Order .........................................1-16 

2-1 Memory Address Map ...............................................................................................................2-3 

2-2 SDRAM Memory Types Supported by the Applications Processor...........................................2-5 

2-3 Normal Mode Memory Address Mapping ..................................................................................2-6 

2-4 Applications Processor Compatibility Mode Address Line Mapping..........................................2-7 

2-5 Valid Booting Configurations Based on Package Type .............................................................2-8 

2-6 BOOT_SEL Definitions..............................................................................................................2-8 

vi 


Contents 

2-7 SRAM / ROM / Flash / Synchronous Fast Flash AC Specifications ..........................................2-9 

2-8 Variable Latency I/O Interface AC Specifications ....................................................................2-10 

2-9 Card Interface (PCMCIA or Compact Flash) AC Specifications ..............................................2-13 

2-10Minimum and Maximum Trace Lengths for the SDRAM Signals.............................................2-18 

3-1 LCD Controller Data Pin Utilization............................................................................................3-1 

3-2 Passive Display Pins Required..................................................................................................3-2 

3-3 Active Display Pins Required.....................................................................................................3-6 

3-4 PXA250 LCD Controller Ball Positions ......................................................................................3-7 

5-1 MMC Signal Description ............................................................................................................5-1 

5-2 SDCard Socket Signals .............................................................................................................5-2 

5-3 MMC Controller Supported Sockets and Devices .....................................................................5-2 

5-4 SDCard Pull-up and Pull-down Resistors ..................................................................................5-6 

5-5 MMC Pull-up and Pull-down Resistors ......................................................................................5-6 

7-1 I2C Signal Description ...............................................................................................................7-1 

8-1 Voltage, Temperature, and Frequency Electrical Specifications ...............................................8-1 

8-2 Absolute Maximum Ratings .......................................................................................................8-2 

8-3 Power Consumption Specifications ...........................................................................................8-3 

8-4 32.768 kHz Oscillator Specifications .........................................................................................8-4 

8-5 3.6864 MHz Oscillator Specifications ........................................................................................8-5 

8-6 PXA250 and PXA210 VCCN vs. VCCQ ....................................................................................8-6 

8-7 Power-On Timing Specifications..............................................................................................8-12 

8-8 Hardware Reset Timing Specifications....................................................................................8-13 

8-9 GPIO Reset Timing Specifications ..........................................................................................8-14 

8-10Sleep Mode Timing Specifications...........................................................................................8-14 

8-11SRAM / ROM / Flash / Synchronous Fast Flash AC Specifications (3.3 V) ............................8-15 

8-12Variable Latency I/O Interface AC Specifications (3.3 V) ........................................................8-16 

8-13Card Interface (PCMCIA or Compact Flash) AC Specifications (3.3 V) ..................................8-16 

8-14Synchronous Memory Interface AC Specifications (3.3 V)......................................................8-17 

8-15SRAM / ROM / Flash / Synchronous Fast Flash AC Specifications (2.5 V) ............................8-18 

8-16Variable Latency I/O Interface AC Specifications (2.5 V) ........................................................8-19 

8-17Card Interface (PCMCIA or Compact Flash) AC Specifications (2.5 V) ..................................8-19 

8-18Synchronous Memory Interface AC Specifications (2.5 V)......................................................8-20 


vii

Contents 

viii 


Introduction 1 

Table 1-1. 

Revision History 

Date Revision Description 

Nov 2000 0.1 Initial Release: RS-Intel ® PXA250 Platform Design Guide 

Nov 2000 0.2 Second draft 

Jan 2001 0.3 

Corrected name of FFRTS in Table 1-4. 

Reorganized Table 1-4 and Table 1-5 for readability. 

May 2001 0.6 Added reference to PXA210 and performed editorial clean-up. 

February 2002 1.0 Public Release 

This document presents design recommendations, board schematics, and debug recommendations 

for the Intel® PXA250 and PXA210 applications processors. The PXA250 applications processor 

is the 32-bit version of the device and the PXA210 applications processor is the 16-bit version. 

This document refers to both versions as the applications processor. When differences are 

discussed, the specific applications processor is called by name. 

The guidelines presented in this document ensure maximum flexibility for board designers, while 

reducing the risk of board-related issues. Use the schematics in Appendix B, “Example Form 

Factor Reference Design Schematic Diagrams” as a reference for your own design. While the 

included schematics cover a specific design, the core schematics remain the same for most 

PXA250 and PXA210 applications processor based platforms. Consult the debug 

recommendations when debugging an applications processor based system. To ensure the correct 

implementation of the debug port (refer to Section 9 for more information), these debug 

recommendations should be understood before completing board design, in addition to other debug 

features. 

Table 1-2. Related Documentation 

Document Title 

Order Number 

Intel® PXA250 and PXA210 Applications Processors Developer’s Manual 278522 

Intel® PXA250 and PXA210 Applications Processors Electrical, Mechanical, 

and Thermal Specification 

278524 

1.1 Functional Overview 

The PXA250 and PXA210 applications processors are the first integrated-system-on-a-chip design 

based on the Intel® XScale microarchitecture. The PXA250 and PXA210 applications 

processors integrate the Intel® XScale microarchitecture core with many peripherals to let you 

design products for the handheld market. 

Figure 1-1 on page 1-2 is a block diagram of the applications processor. 

PXA250 and PXA210 Applications Processors Design Guide 1-1

Introduction 

s 

Figure 1-1. Applications Processor Block Diagram 

RTC 

OS Timer 

PWM(2) 

Color or 

Grayscale 

LCD 

Controller 

Memory 

Controller 

General Purpose I/O 

Int. 

Controller 

Clocks & 

Power Man. 

I 2 S 

I 2 C 

AC97 

UART1 

UART2 

Slow IrDA 

Fast IrDA 

Peripheral Bus 

DMA Controller 

and Bridge 

System Bus 

Megacell 

Core 

Variable 

Latency I/O 

Control 

PCMCIA 

& CF 

Control 

Dynamic 

Memory 

Control 

Static 

Memory 

Control 

ASIC 

XCVR 

SDRAM/ 

SMROM 

4 banks 

ROM/ 

Flash/ 

SRAM 

4 banks 

Socket 0 

Socket 1 

SSP 

USB 

Client 

MMC 

3.6864 

MHz 

Osc 

32.768 

KHz 

Osc 

A8651-01 

The PXA250 applications processor package is: 256 pin, 17x17 mBGA – 32-bit functionality. The 

PXA210 applications processor package is: 225 pin, 13x13 MMAP – 16-bit functionality, a subset 

of the PXA250 applications processor feature set. 

Section 1.2.1, “Package Introduction” contains a breakdown of the features supported by the two 

different packages. 

1.2 Package Information 

This section describes the package types, pinouts, and signal descriptions. 

1.2.1 Package Introduction 

Package features of the PXA250 applications processor are: 

• Core frequencies supported - 100 MHz - 400 MHz 

1-2 PXA250 and PXA210 Applications Processors Design Guide

Introduction 

• System memory interface 

—100MHz SDRAM 

— 4 MB to 256 MB of SDRAM memory 

— Support for 16, 64, 128, or 256 Mbit DRAM technologies 

— 4 Banks of SDRAM, each supporting 64 MB of memory 

— Clock enable (1 CKE pin is provided to put the entire SDRAM interface into self refresh) 

— Supports as many as 6 static memory devices (SRAM, Flash, or VLIO) 

• PCMCIA/Compact Flash card control pins 

• LCD Controller pins 

• Full Function UART 

• Bluetooth UART 

• MMC Controller pins 

• SSP Pins 

• USB Client Pins 

• AC’97 Controller Pins 

• Standard UART Pins 

• I 2 C Controller pins 

• PWM pins 

• 15 dedicated GPIOs pins 

• Integrated JTAG support 

Package features of the PXA210 applications processor are: 

• Core frequencies supported – 100 MHz, 133 MHz, 200 MHzSystem memory interface 

— 100 MHz SDRAM, 16-bit only 

— 2 MB to 128 MB of SDRAM memory 

— Support for 16, 64, 128, or 256 Mbit DRAM technologies 

— 2 Banks of SDRAM, each supporting 64 MB of memory 

— Supports as many as 6 static memory devices (SRAM, Flash, or VLIO) 

• Clock enable (1 CKE pin is provided to put the entire SDRAM interface into self refresh) 

• LCD Controller pins 

• Bluetooth UART 

• MMC Controller pins 

• SSP Pins 

• USB Client Pins 

• AC97 Controller Pins 

• Standard UART Pins 


Introduction 

• I 2 C Controller pins 

• PWM pins 

• 2 dedicated GPIOs pins 

• Integrated JTAG support 

1.2.2 Signal Pin Descriptions 

Table 1-3 defines the signal descriptions for the applications processor. 

Table 1-3. Signal Pin Descriptions (Sheet 1 of 7) 

Name Type Description 

Memory Controller Pins 

MA[25:0] OCZ Memory address bus. This bus signals the address requested for memory accesses. 

MD[15:0] ICOCZ Memory data bus. D[15:0] are used for 16-bit and 32-bit data modes. 

MD[31:16] 

nOE 

ICOCZ 

OCZ 

Memory data bus. D[31:16]: These signals are the upper memory data bus address 

bits. 

See Note [1] 

Memory output enable. Connect this signal to the output enables of memory devices 

to control their data bus drivers. 

nWE OCZ Memory write enable. Connect this signal to the write enables of memory devices. 

nSDCS[3:0] 

DQM[3:0] 

nSDRAS 

nSDCAS 

SDCKE[0] 

SDCKE[1] 

SDCLK[2:0] 

OCZ 

OCZ 

OCZ 

OCZ 

OC 

OC 

OCZ 

SDRAM CS for banks 0 through 3. Connect these signals to the chip select (CS) pins 

for SDRAM. nSDCS0 is a three-state signal, while nSDCS1-3 are not three-state. 

SDRAM DQM for data bytes 0 through 3. Connect these signals to the data output 

mask enables (DQM) for SDRAM. 

SDRAM RAS. Connect this signal to the row address strobe (RAS) pins for all banks 

of SDRAM. 

SDRAM CAS. Connect this signal to the column address strobe (CAS) pins for all 

banks of SDRAM. 

SDRAM and/or Synchronous Static Memory/SDRAM-like synchronous Flash clock 

enable clock enable. 

ConnectSDCKE[0] to the CKE pins of SMROM and SDRAM-timing Synchronous 

Flash. 

The memory controller provides control register bits for deassertion of each SDCKE 

pin. 

SDRAM device clock enable. 

Connect SDCKE[1] to the clock enable pins of SDRAM. It is de-asserted (held low) 

during sleep. SDCKE[1] is always deasserted upon reset. 

The memory controller provides control register bits for deassertion of each SDCKE 

pin. 

See Note [1] 

Use these clocks to clock synchronous memory devices: 

SDCLK0 - connected to either SMROM or synchronous Flash devices 

SDCLK1 - connected to SDRAM banks 0/1 

SDCLK2 - connected to SDRAM banks 2/3 

See Note [1] 


Introduction 



nCS[5]/ 

GPIO[33] 

nCS[4]/ 

GPIO[80] 

nCS[3]/ 

GPIO[79] 

nCS[2]/ 

GPIO[78] 

nCS[1]/ 

GPIO[15] 

nCS[0] 

ICOCZ 

ICOCZ 

ICOCZ 

ICOCZ 

ICOCZ 

ICOCZ 

Static chip selects. These signals are chip selects to static memory devices such as 

ROM and Flash. They are individually programmable in the memory configuration 

registers. nCS[5:3] may be used with variable data latency variable latency I/O 

devices. 

See Note [2] 

Static chip select 0. This is the chip select for the boot memory. nCS[0] is a dedicated 

pin. 

RD/nWR OCZ Read/Write for static interface. Intended for use as a steering signal for buffering logic 

RDY/ 

GPIO[18] 

MBGNT/GP[13] 

MBREQ/GP[14] 

ICOCZ 

ICOCZ 

ICOCZ 

Variable Latency I/O Ready pin (input) 

See Note [2] 

Memory Controller grant. (output) Notifies an external device that it has been granted 

the system bus. 

Memory Controller alternate bus master request. (input) Allows an external device to 

request the system bus from the Memory Controller. 

PCMCIA/CF Control Pins - PXA250 Applications Processor only 

nPOE/ GPIO[48] 

nPWE/ 

GPIO[49] 

nPIOW/ 

GPIO[51] 

nPIOR/ 

GPIO[50] 

nPCE[2:1]/ 

GPIO[53, 52] 

nIOIS16/ 

GPIO[57] 

nPWAIT/ 

GPIO[56] 

nPSKTSEL/ 

GPIO[54] 

ICOCZ 

ICOCZ 

ICOCZ 

ICOCZ 

ICOCZ 

ICOCZ 

ICOCZ 

ICOCZ 

PCMCIA output enable. Output PCMCIA signal that performs reads from memory and 

attribute space. 

See Note [2] 

PCMCIA write enable. Output signal that performs writes to memory and attribute 

space. 

See Note [2] 

PCMCIA I/O write. Output signal that performs write transactions to the PCMCIA I/O 

space. 

See Note [2] 

PCMCIA I/O read. Output signal that performs read transactions from the PCMCIA I/O 

space. 

See Note [2] 

PCMCIA card enable. Output signals that selects a PCMCIA card. Bit one enables the 

high byte lane and bit zero enables the low byte lane. 

See Note [2] 

I/O Select 16. Input signal from the PCMCIA card that indicates the current address is 

a valid 16 bit wide I/O address. 

See Note [2] 

PCMCIA wait. Input signal that is driven low by the PCMCIA card to extend the length 

of the transfers to/from the applications processor. 

See Note [2] 

PCMCIA socket select. Output signal used by external steering logic to route control, 

address, and data signals to one of the two PCMCIA sockets. When PSKTSEL is low, 

socket zero is selected. When PSKTSEL is high, socket one is selected. This signal 

has the same timing as address. 

See Note [2] 


Introduction 



nPREG/ 

GPIO[55] 

LCD Controller Pins 

L_DD(15:0)/ 

GPIO[73:58] 

L_FCLK/ 

GPIO[74] 

L_LCLK/ 

GPIO[75] 

L_PCLK/ 

GPIO[76] 

L_BIAS/ 

GPIO[77] 

ICOCZ 

ICOCZ 

ICOCZ 

ICOCZ 

ICOCZ 

ICOCZ 

PCMCIA register select. Output signal that indicates the target address is attribute 

space, on a memory transaction. This signal has the same timing as address. 

See Note [2] 

LCD Controller display data 

See Note [2] 

LCD Frame clock 

See Note [2] 

LCD Line clock 

See Note [2] 

LCD pixel clock 

See Note [2] 

AC Bias Drive 

See Note [2] 

Full Function UART Pins 

FFRXD/ 

GPIO[34] 

FFTXD/ 

GPIO[39] 

FFCTS/ 

GPIO[35] 

FFDCD/ 

GPIO[36] 

FFDSR/ 

GPIO[37] 

FFRI/ 

GPIO[38] 

FFDTR/ 

GPIO[40] 

FFRTS/ 

GPIO[41] 

Bluetooth UART Pins 

BTRXD/ 

GPIO[42] 

BTTXD/ 

GPIO[43] 

BTCTS/ 

GPIO[44] 

BTRTS/ 

GPIO[45] 

MMC Controller Pins 

ICOCZ 

ICOCZ 

ICOCZ 

ICOCZ 

ICOCZ 

ICOCZ 

ICOCZ 

ICOCZ 

ICOCZ 

ICOCZ 

ICOCZ 

ICOCZ 

Full Function UART Receive pin 

See Note [2] 

Full Function UART Transmit pin 

See Note [2] 

Full Function UART Clear-to-Send pin 

See Note [2] 

Full Function UART Data-Carrier-Detect Pin 

See Note [2] 

Full Function UART Data-Set-Ready Pin: 

See Note [2] 

Full Function UART Ring Indicator Pin 

See Note [2] 

Full Function UART Data-Terminal-Ready pin 

See Note [2] 

Full Function UART Ready-to-Send pin 

See Note [2] 

Bluetooth UART Receive pin 

See Note [2] 

Bluetooth UART Transmit pin 

See Note [2] 

Bluetooth UART Clear-to-Send pin 

See Note [2] 

Bluetooth UART Data-Terminal-Ready pin 

See Note [2] 

MMCMD ICOCZ Multimedia Card Command pin (I/O) 


Introduction 



MMDAT ICOCZ Multimedia Card Data Pin (I/O) 

MMCCLK/GP[6] ICOCZ MMC clock. (output) Clock signal for the MMC Controller. 

MMCCS0/GP[8] ICOCZ MMC chip select 0. (output) Chip select 0 for the MMC Controller. 

MMCCS1/GP[9] ICOCZ MMC chip select 1. (output) Chip select 1 for the MMC Controller. 

SSP Pins 

SSPSCLK/ 

GPIO[23] 

SSPSFRM/ 

GPIO[24] 

SSPTXD/ 

GPIO[25] 

SSPRXD/ 

GPIO[26] 

SSPEXTCLK/ 

GPIO[27] 

USB Client Pins 

ICOCZ 

ICOCZ 

ICOCZ 

ICOCZ 

ICOCZ 

Synchronous Serial Port Clock (output) 

See Note [2] 

Synchronous serial port Frame Signal (output) 

See Note [2] 

Synchronous serial port transmit (output) 

See Note [2] 

Synchronous serial port receive (input) 

See Note [2] 

Synchronous Serial port external clock (input) 

See Note [2] 

USB_P IAOA USB Client port positive Pin of differential pair. 

USB_N IAOA USB Client port negative Pin of differential pair. 

AC97 Controller Pins 

BITCLK/ 

GPIO[28] 

SDATA_IN0/ 

GPIO[29] 

SDATA_IN1/ 

GPIO[32] 

SDATA_OUT/ 

GPIO[30] 

SYNC/ 

GPIO[31] 

nACRESET 

ICOCZ 

ICOCZ 

ICOCZ 

ICOCZ 

ICOCZ 

OC 

AC97 Audio Port bit clock (output) 

See Note [2] 

AC97 Audio Port data in (input) 

See Note [2] 

AC97 Audio Port data in (input) 

See Note [2] 

AC97 Audio Port data out (output) 

See Note [2] 

AC97 Audio Port sync signal (output) 

See Note [2] 

AC97 Audio Port reset signal (output) 

This pin is a dedicated output. 

Standard UART and ICP Pins 

IRRXD/ 

GPIO[46] 

IRTXD/ 

GPIO[47] 

I 2 C Controller Pins 

SCL 

ICOCZ 

ICOCZ 

ICOCZ 

IrDA Receive signal (input). 

See Note [2] 

IrDA Transmit signal (output). 

Transmit pin for both the SIR and FIR functions. 

See Note [2] 

I2C clock (Bidirectional) 

Bidirectional signal. When it is driving, it functions as an open collector device and 

requires a pull up resistor. As an input, it expects standard CMOS levels. 


Introduction 



SDA 

PWM Pins 

PWM[1:0]/ 

GPIO[17,16] 

Dedicated GPIO Pins 

GPIO[1:0] 

GPIO[14:2]) 

GPIO[22:21] 

Crystal Pins 

ICOCZ 

ICOCZ 

ICOCZ 

ICOCZ 

ICOCZ 

I2C Data signal (bidirectional). 

Bidirectional signal. When it is driving, it functions as an open collector device and 

requires a pull up resistor. As an input, it expects standard CMOS levels. 

Pulse Width Modulation channels 0 and 1 (outputs) 

See Note [2] 

General Purpose I/O: These two pins are contained in both the PXA250 and PXA210 

applications processors. They are preconfigured at a hard reset (nRESET) as wakeup 

sources for both rising and falling edge detects. 

These GPIOs do not have alternate functions and are intended to be used as the main 

external sleep wakeup stimulus. 


See Note [1] 

See Note [2] 


Additional general purpose I/O pins. 

PXTAL IA Input connection for 3.6864 Mhz crystal 

PEXTAL OA Output connection for 3.6864 Mhz crystal 

TXTAL IA Input connection for 32.768 khz crystal 

TEXTAL OA Output connection for 32.768 khz crystal 

48MHz/GP[7] ICOCZ 48 MHz clock. (output) Peripheral clock output derived from the PLL. 

RTCCLK/GP[10] ICOCZ Real time clock. (output) HZ output derived from the 32kHz or 3.6864MHz output. 

3.6MHz/GP[11] ICOCZ 3.6864 MHz clock. (output) Output from 3.6864 MHz oscillator. 

32kHz/GP[12] ICOCZ 32 kHz clock. (output) Output from the 32 kHz oscillator. 

Miscellaneous Pins 

BOOT_SEL 

[2:0] 

PWR_EN 

nBATT_FAULT 

IC 

OCZ 

IC 

Boot programming select pins. These pins are sampled to indicate the type of boot 

device present per the following table; 

BOOT_SEL[2:0] Description 

000Asynchronous 32-bit ROM 

001Asynchronous 16-bit ROM 

100One 32-bit SMROM 

101One 16 bit SMROM 

110Two 16 bit SMROMs (32 bit bus) 

111Reserved 

Power Enable. Active high Output. 

PWR_EN enables the external power supply. Negating it signals the power supply 

that the system is going into sleep mode and that the VDD power supply should be 

removed. 

Battery Fault. Active low input. 

The assertion of nBATT_FAULT causes the applications processor to enter Sleep 

Mode.The applications processor will not recognize a wakeup event while this signal 

is asserted. Use nBATT_FAULT signal to flag a critical power failure, such as the main 

battery being removed. Minimum assertion time for nBATT_FAULT is 1ms. 


Introduction 



nVDD_FAULT 

nRESET 

nRESET_OUT 

JTAG Pins 

nTRST 

IC 

IC 

OC 

IC 

VDD Fault. Active low input. 

nVDD_FAULT causes the applications processor to enter Sleep Mode. nVDD_FAULT 

is ignored after a wakeup event until the power supply timer completes (approximately 

10 ms). use the nVDD_FAULT signal to flag a low battery. Minimum assertion time for 

nVDD_FAULT is 1 ms. 

Hard reset. Active low input. 

nRESET is a level sensitive input which starts the processor from a known address. A 

LOW level causes the current instruction to terminate abnormally, and all on-chip state 

to be reset. When nRESET is driven HIGH, the processor re-starts from address 0. 

nRESET must remain LOW until the power supply is stable and the internal 3.6864 

MHz oscillator has come up to speed. While nRESET is LOW the processor performs 

idle cycles. 

Reset Out. Active low output. 

This signal is asserted when nRESET is asserted and de-asserts after nRESET is 

negated but before the first instruction fetch. nRESET_OUT is also asserted for “soft” 

reset events (sleep, watchdog reset, GPIO reset) 

JTAG Test Interface Reset. Resets the JTAG/Debug port. If JTAG/Debug is used, 

drive nTRST from low to high either before or at the same time as nRESET. If JTAG is 

not used, nTRST must be either tied to nRESET or tied low. Intel recommends that a 

JTAG/Debug port be added to all systems for debug and download. See Chapter 9 for 

details. 

TDI IC JTAG test interface data input. Note this pin has an internal pullup resistor. 

TDO 

OCZ 

JTAG test interface data output. Note this pin does NOT have an internal pullup 

resistor. 

TMS IC JTAG test interface mode select. Note this pin has an internal pullup resistor. 

TCK 

IC 

JTAG test interface reference Clock. TCK is the reference clock for all transfers on the 

JTAG test interface. 

NOTE: This pin needs an external pulldown resistor. 

TEST IC Test Mode. You should ground this pin. This pin is for manufacturing purposes only. 

TESTCLK IC Test Clock. Use this pin for test purposes only. An end user should ground this pin. 

Power and Ground Pins 

VCC 

VSS 

SUP 

SUP 

Positive supply for the internal logic. Connect this supply to the low voltage (.85 - 

1.65v) supply on the PCB. 

Ground supply for the internal logic. Connect these pins to the common ground plane 

on the PCB. 

PLL_VCC SUP Positive supply for PLLs and oscillators must be shorted to VCC. 

PLL_VSS SUP Ground supply for the PLL. Must be connected to common ground plane on the PCB. 

VCCQ 

VSSQ 

VCCN 

SUP 

SUP 

SUP 

Positive supply for all CMOS I/O except memory bus and PCMCIA pins. Connect 

these pins to the common 3.3v supply on the PCB. 

Ground supply for all CMOS I/O except memory bus and PCMCIA pins. Connect 

these pins to the common ground plane on the PCB. 

Positive supply for memory bus and PCMCIA pins. Connect these pins to the common 

3.3 V or 2.5 V supply on the PCB. 


Introduction 

VSSN 



SUP 

Ground supply for memory bus and PCMCIA pins. Connect these pins to the common 

ground plane on the PCB. 

BATT_VCC SUP 

Backup battery connection. Connect this pin to the backup battery supply. If a backup 

battery is not required then this pin may be connected to the common 3.3v supply on 

the PCB. 

NOTES: 

1. Not pinned out for the PXA210 applications processor. 

2. GPIO Reset Operation: After any reset, these pins are configured as GPIO inputs by default. The input buffers for these pins 

are disabled to prevent current drain and must be enabled prior to use by clearing the Read Disable Hold (RDH) bit. 

To use a GPIO pin as an alternate function, follow this sequence: 

1) Program the pin to the desired direction (input or output) using the GPIO Pin Direction Registers (GPDR). 

2) Enable the input buffer by clearing the RDH bit, described above. 

3) If needed, select the desired alternate function by programming the proper bits in the GPIO Alternate Function 

Register (GAFR). 


Introduction 

Figure 1-2. PXA250 Applications Processor 


Introduction 

Table 1-4. PXA250 Applications Processor Pinout — Ballpad Number Order (Sheet 1 of 3) 

Ball # Signal Ball # Signal Ball # Signal 

A1 VCCN F7 GPIO[10] L13 GPIO[2] 

A2 L_DD[13]/GPIO[71] F8 FFRTS/GPIO[41] L14 VSSQ 

A3 L_DD[12]/GPIO[70] F9 SSPSCLK/GPIO[23] L15 TEXTAL 

A4 L_DD[11]/GPIO[69] F10 FFDTR/GPIO[40] L16 TXTAL 

A5 L_DD[9]/GPIO[67] F11 VCC M1 MA[14] 

A6 L_DD[7]/GPIO[65] F12 GPIO[9] M2 MD[21] 

A7 GPIO[11] F13 BOOT_SEL[2] M3 MA[15] 

A8 L_BIAS/GPIO[77] F14 GPIO[8] M4 VCCN 

A9 SSPRXD/GPIO[26] F15 VSSQ M5 MD[1] 

A10 SDATA_OUT/GPIO[30] F16 VSSQ M6 MD[6] 

A11 SDA G1 MA[0] M7 MD[7] 

A12 FFDCD/GPIO[36] G2 VSSN M8 DQM[0] 

A13 FFRXD/GPIO[34] G3 nSDCS[2] M9 MD[8] 

A14 FFCTS/GPIO[35] G4 nWE M10 MD[15] 

A15 BTCTS/GPIO[44] G5 nOE M11 BATT_VCC 

A16 SDATA_IN1/GPIO[32] G6 nSDCS[1] M12 GPIO[22] 

B1 DQM[1] G7 VCC M13 nPREG/GPIO[55] 

B2 DQM[2] G8 VSSQ M14 VCCN 

B3 L_DD[15]/GPIO[73] G9 VCC M15 VSSN 

B4 GPIO[14] G10 VSSQ M16 nIOIS16/GPIO[57] 

B5 GPIO[13] G11 TESTCLK N1 MD[22] 

B6 GPIO[12] G12 TEST N2 VSSN 

B7 L_DD[3]/GPIO[61] G13 BOOT_SEL[1] N3 MA[16] 

B8 L_PCLK/GPIO[76] G14 VCCQ N4 MD[0] 

B9 SSPEXTCLK/GPIO[27] G15 GPIO[7] N5 VCCN 

B10 FFRI/GPIO[38] G16 BOOT_SEL[0] N6 MD[4] 

B11 FFDSR/GPIO[37] H1 MA[2] N7 VCCN 

B12 USB_N H2 MA[1] N8 nCS[0] 

B13 BTRXD/GPIO[42] H3 MD[16] N9 VCCN 

B14 BTRTS/GPIO[45] H4 VCCN N10 MD[13] 

B15 IRRXD/GPIO[46] H5 MD[17] N11 VCCN 

B16 MMDAT H6 MA[3] N12 DREQ[0]/GPIO[20] 

C1 RDY/GPIO[18] H7 VSSQ N13 VCCN 

C2 VSSN H8 VSS N14 DREQ[1]/GPIO[19] 

C3 L_DD[14]/GPIO[72] H9 VSS N15 GPIO[21] 

C4 VSSQ H10 VCC N16 nPWAIT/GPIO[56] 

C5 L_DD[8]/GPIO[66] H11 nTRST P1 MA[17] 


Introduction 



C6 VCCQ H12 TCK P2 MA[19] 

C7 L_DD[2]/GPIO[60] H13 TMS P3 VCCN 

C8 VSSQ H14 GPIO[6] P4 MA[25] 

C9 BITCLK/GPIO[28] H15 TDI P5 MA[23] 

C10 VCCQ H16 TDO P6 MD[24] 

C11 VSSQ J1 MA[7] P7 MD[26] 

C12 USB_P J2 VSSN P8 MD[27] 

C13 VCCQ J3 MA[6] P9 nCS[2]/GPIO[78] 

C14 VSSQ J4 MD[18] P10 MD[29] 

C15 IRTXD/GPIO[47] J5 MA[5] P11 MD[12] 

C16 VSS J6 MA[4] P12 MD[31] 

D1 SDCLK[2] J7 VCC P13 nPOE/GPIO[48] 

D2 SDCLK[0] J8 VSS P14 nPCE[1]/GPIO[52] 

D3 RDnWR J9 VSS P15 VSSN 

D4 VCCN J10 VSSQ P16 nPSKTSEL/GPIO[54] 

D5 L_DD[10]/GPIO[68] J11 GPIO[5] R1 MA[18] 

D6 L_DD[5]/GPIO[63] J12 GPIO[4] R2 VSSN 

D7 L_DD[1]/GPIO[59] J13 nRESET R3 MA[20] 

D8 L_LCLK/GPIO[75] J14 VSSQ R4 VSSN 

D9 SSPTXD/GPIO[25] J15 PLL_VCC R5 MA[22] 

D10 nACRESET J16 PLL_VSS R6 VSSN 

D11 SCL K1 MA[8] R7 MD[25] 

D12 PWM[1]/GPIO[17] K2 MA[9] R8 VSSN 

D13 BTTXD/GPIO[43] K3 MD[19] R9 MD[10] 

D14 MMCMD K4 VCCN R10 VSSN 

D15 VCCQ K5 MA[10] R11 MD[30] 

D16 VSSQ K6 MA[11] R12 VSSN 

E1 nSDRAS K7 VSSQ R13 nCS[4]/GPIO[80] 

E2 VSSN K8 VCC R14 VSSN 

E3 SDCKE[1] K9 VSSQ R15 nPIOW/GPIO[51] 

E4 SDCKE[0] K10 VCC R16 nPCE[2]/GPIO[53] 

E5 L_DD[6]/GPIO[64] K11 nRESET_OUT T1 VSS 

E6 L_DD[4]/GPIO[62] K12 nBATT_FAULT T2 VCCN 

E7 L_DD[0]/GPIO[58] K13 nVDD_FAULT T3 MD[23] 

E8 L_FCLK/GPIO[74] K14 GPIO[3] T4 MA[21] 

E9 SSPSFRM/GPIO[24] K15 PXTAL T5 MA[24] 

E10 SDATA_IN0/GPIO[29] K16 PEXTAL T6 MD[3] 

E11 SYNC/GPIO[31] L1 MA[12] T7 MD[5] 


Introduction 



E12 PWM[0]/GPIO[16] L2 VSSN T8 nCS[1]/GPIO[15] 

E13 FFTXD/GPIO[39] L3 MA[13] T9 nCS[3]/GPIO[79] 

E14 VCCQ L4 MD[20] T10 MD[9] 

E15 VSSQ L5 MD[2] T11 MD[11] 

E16 VSSQ L6 VCC T12 MD[14] 

F1 nSDCS[0] L7 DQM[3] T13 nCS[5]/GPIO[33] 

F2 nSDCS[3] L8 MD[28] T14 nPWE/GPIO[49] 

F3 nSDCAS L9 VCC T15 nPIOR/GPIO[50] 

F4 VCCN L10 GPIO[0] T16 VCCN 

F5 SDCLK[1] L11 PWR_EN 

F6 VSSQ L12 GPIO[1] 


Introduction 

Figure 1-3. PXA210 Applications Processor 

φ 


Introduction 



A1 DQM[1] F1 VSSN L1 VSSN 

A2 L_DD[14]/GPIO[72] F2 nSDCS[0] L2 VCCN 

A3 L_DD[10]/GPIO[68] F3 nSDRAS L3 MA[12] 

A4 VSSQ F4 nSDCS[1] L4 MA[13] 

A5 L_DD[6]/GPIO[64] F5 VCC L5 MA[11] 

A6 L_DD[2]/GPIO[60] F6 L_DD[8]/GPIO[66] L6 VSSQ 

A7 L_LCLK/GPIO[75] F7 L_FCLK/GPIO[74] L7 MD[2] 

A8 SPPSCLK/GPIO[23] F8 SSPRXD/GPIO[26] L8 MD[6] 

A9 SPPEXTCLK/GPIO[27] F9 VCC L9 VSSN 

A10 nACRESET F10 FFTXD/GPIO[39] L10 MD[11] 

A11 PWM[1]/GPIO[17] F11 VCC L11 BATT_VCC 

A12 VSSQ F12 VSSQ L12 GPIO[54] 

A13 FFRXD/GPIO[34] F13 TESTCLK L13 GPIO[55] 

A14 BTCTS/GPIO[44] F14 BOOT_SEL[0] L14 GPIO[57] 

A15 IRRXD/GPIO[46] F15 TEST L15 GPIO[0] 

B1 RDY/GPIO[18] G1 MA[0] M1 MA[14] 

B2 VSSN G2 nOE M2 MA[15] 

B3 L_DD[13]/GPIO[71] G3 nWE M3 VCCN 

B4 L_DD[9]/GPIO[67] G4 VCCN M4 MA[16] 

B5 VSSQ G5 VSSN M5 VCCN 

B6 L_DD[3]/GPIO[61] G6 RDnWR M6 VSSN 

B7 L_PCLK/GPIO[76] G7 VSS M7 MD[3] 

B8 VSSQ G8 VSS M8 MD[7] 

B9 BITCLK/GPIO[28] G9 VSS M9 nCS[1]/GPIO[15] 

B10 SDA G10 BTRXD/GPIO[42] M10 MD[10] 

B11 VSSQ G11 nTRST M11 MD[13] 

B12 USB_N G12 TDI M12 GPIO[48] 

B13 BTRTS/GPIO[45] G13 TCK M13 GPIO[52] 

B14 IRTXD/GPIO[47] G14 TMS M14 VSSN 

B15 MMDAT G15 TDO M15 GPIO[56] 

C1 SDCKE[1] H1 VCCN N1 VSSN 

C2 SDCKE[0] H2 VSSN N2 MA[18] 

C3 VCCN H3 MA[2] N3 VSS1 

C4 L_DD[12]/GPIO[70] H4 MA[1] N4 MA[22] 

C5 VCCQ H5 VCC N5 MA[24] 

C6 L_DD[4]/GPIO[62] H6 VSSQ N6 VCCN 

C7 L_BIAS/GPIO[77] H7 VSS N7 VCC 


Introduction 



C8 VCCQ H8 VSS N8 VSSN 

C9 SDATA_IN0/GPIO[29] H9 VSS N9 DQM[0] 

C10 PWM[0]/GPIO[16] H10 VSSQ N10 VCCN 

C11 USB_P H11 VCC N11 MD[12] 

C12 BTTXD/GPIO[43] H12 VSSQ N12 VSSN 

C13 VSSQ H13 VCC N13 nCS[5]/GPIO[33] 

C14 VSS H14 PLL_VCC N14 GPIO[53] 

C15 VCCQ H15 PLL_VSS N15 VCCN 

D1 VCC J1 MA[5] P1 MA[17] 

D2 VSSQ J2 MA[6] P2 VSSN 

D3 SDCLK[1] J3 VSSN P3 VCCN 

D4 L_DD[15]/GPIO[73] J4 MA[4] P4 MA[23] 

D5 VCC J5 MA[3] P5 MD[0] 

D6 L_DD[5]/GPIO[63] J6 VSSQ P6 VSSN 

D7 L_DD[0]/GPIO[58] J7 VSS1 P7 MD[4] 

D8 SPPSFRM/GPIO[24] J8 VSS1 P8 VCCN 

D9 SDATA_OUT/GPIO[30] J9 VSS1 P9 nCS[2]/GPIO[78] 

D10 SCL J10 VSSQ P10 MD[8] 

D11 SDATA_IN1/GPIO[32] J11 nRESET P11 VCCn 

D12 BOOT_SEL[1] J12 nRESET_OUT P12 MD[15] 

D13 VSSQ J13 PWR_EN P13 VCCN 

D14 VSSQ J14 nVDD_FAULT P14 GPIO[50] 

D15 VSSQ J15 nBATT_FAULT P15 VSSQ 

E1 nSDCAS K1 MA[8] R1 MA[19] 

E2 VCCN K2 MA[9] R2 MA[20] 

E3 VSSN K3 MA[10] R3 MA[21] 

E4 SDCLK[0] K4 MA[7] R4 MA[25] 

E5 L_DD[11]/GPIO[69] K5 VCCN R5 MD[1] 

E6 L_DD[7]/GPIO[65] K6 VCC R6 VCCN 

E7 L_DD[1]/GPIO[59] K7 VSSQ R7 MD[5] 

E8 SSPTXD/GPIO[25] K8 VCC R8 nCS[0] 

E9 SYNC/GPIO[31] K9 VSSQ R9 nCS[3]/GPIO[79] 

E10 VCCQ K10 VCC R10 MD[9] 

E11 MMCMD K11 GPIO[1] R11 VSSN 

E12 VCCQ K12 TEXTAL R12 MD[14] 

E13 VSSQ K13 TXTAL R13 nCS[4]/GPIO[80] 

E14 VSSQ K14 PEXTAL R14 nPWE/GPIO[49] 

E15 BOOT_SEL[2] K15 PXTAL R15 GPIO[51] 


Introduction 


System Memory Interface 2 

This section is the design guidelines for the system memory interface. 

2.1 Overview 

The external memory bus interface for the applications processor supports: 

• 100 MHz SDRAM at 3.3 V 

• 100 MHz SDRAM at 2.5 V 

• Synchronous and asynchronous Burst mode and Page mode Flash 

• Synchronous Mask ROM (SMROM) 

• Page Mode ROM 

• SRAM 

• SRAM-like Variable Latency I/O (VLIO) 

• PCMCIA expansion memory 

• Compact Flash 

Use the memory interface configuration registers to program the memory types. Refer to 

Figure 1-1, “Applications Processor Block Diagram” on page 1-2 for the block diagram of the 

Memory Controller configuration. Refer to Figure 2-1, “Memory Address Map” on page 2-3 for 

the applications processor memory map. Refer to Table 2-3, “Normal Mode Memory Address 

Mapping” on page 2-6 for alternate mode address mapping. 


System Memory Interface 

Figure 2-1. General Memory Interface Configuration 

nSDCS 

nSDCS 

SDCLK, SDCKE 

nSDCS 

nSDCS 

SDCLK, SDCKE 

SDRAM Partition 0 




SDRAM Memory Interface 

Up to 4 partitions of SDRAM 

memory (16- or 32-bit wide) 

DQM 

nSDRAS, nSDCAS 

PXA250 

Memory 

Controller 

Interface 

MD 

MA 

Card Control 

Buffers and 

Transceivers 

Card Memory Interface 

Up to 2-socket support. 

Requires some 

external buffering. 

nCS 

nCS 

nCS 

SDCLK, SDCKE 

Static Bank 0 

Static Bank 1 

Static Bank 2 

Static Memory or 

Variable Latency I/O Interface 

Up to 6 banks of ROM, Flash, 

SRAM, Variable Latency I/O, 

(16- or 32-bit wide) 

NOTE: 

Static Bank 0 must be populated by 

“bootable” memory 

nCS 

nCS 

nCS 

RDY 

Static Bank 3 

Static Bank 4 

Static Bank 5 

Synchronous Static Memory Interface 

Up to 4 banks of synchronous 

static memory (nCS). 

(16- or 32-bit wide) 

NOTE: 

Static Bank 0 must be populated by 

“bootable” memory 



Table 2-1. Memory Address Map 

0x6000 0000 Reserved Address Space 

0x5C00 0000 Reserved Address Space 





0x4800 0000 Memory Mapped Registers (Memory Ctl) 

0x4400 0000 Memory Mapped Registers (LCD) 

0x4000 0000 Memory Mapped Registers (Peripherals) 

0x3000 0000 PCMCIA/CF – Slot 1 

0x2000 0000 PCMCIA/CF – Slot 0 



0x1400 0000 Static Chip Select 5 


0x0C00 0000 Static Chip Select 3 




2.2 SDRAM Interface 

The applications processor supports an SDRAM interface at a maximum frequency of 100 MHz. 

The SDRAM Interface supports four 16-bit or 32-bit wide partitions of SDRAM. Each partition is 

allocated 64 MBytes of the internal memory map. However, the actual size of each partition is 

dependent on the particular SDRAM configuration used. The four partitions are divided into two 

partition pairs: the 0/1 pair and the 2/3 pair. Both partitions within a pair (for example, partition 0 

and partition 1) must be identical in size and configuration; however, the two pairs can be different. 

For example, the 0/1 pair can be 100 MHz SDRAM on a 32-bit data bus, while the 2/3 pair can be 

50 MHz SDRAM on a 16-bit data bus. 

Note: 

For proper SDRAM operation above 50 MHz, 22 ohm series resistors must be placed on the 

memory address lines. 

2.3 SDRAM memory wiring diagram 

Figure 2-2, “SDRAM Memory System Example” on page 2-4 is a wiring diagram example that 

shows a system using 1Mword x 16-bit x 4-bank SDRAM devices for a total of 48 Mbytes. Refer 

to Section 2.5, “SDRAM Address Mapping” on page 2-6 to determine the individual SDRAM 

component address. 



Figure 2-2. SDRAM Memory System Example 

nSDCS(3:0) 

nSDRAS, nSDCAS, nWE, CKE(1) 

SDCLK(2:1) 

MA(23:10) 

4Mx16 

SDRAM 

4Mx16 

SDRAM 

4Mx16 

SDRAM 

0 

nCS 

1 

nCS 

2 

nCS 

nRAS 

nRAS 

nRAS 

nCAS 

nCAS 

nCAS 

nWE 

nWE 

nWE 

1 

CKE 

CLK 

1 

CKE 

CLK 

2 

CKE 

CLK 

addr(11:0) 

addr(11:0) 

addr(11:0) 

0 

1 

BA(1:0) 

DQML 

DQMH 

BA(1:0) 

DQML 

DQMH 

BA(1:0) 

DQML 

DQMH 

15:0 

DQ(15:0) 

DQ(15:0) 

DQ(15:0) 

MD(31:0) 

DQM(3:0) 

4Mx16 

SDRAM 

4Mx16 

SDRAM 

4Mx16 

SDRAM 

0 

nCS 

1 

nCS 

2 

nCS 

nRAS 

nRAS 

nRAS 

nCAS 

nCAS 

nCAS 

nWE 

nWE 

nWE 

31:16 

1 

2 

3 

CKE 

CLK 

addr(11:0) 

BA(1:0) 

DQML 

DQMH 

DQ(15:0) 

1 

CKE 

CLK 

addr(11:0) 

BA(1:0) 

DQML 

DQMH 

DQ(15:0) 

2 

21:10 

23:22 

CKE 

CLK 

addr(11:0) 

BA(1:0) 

DQML 

DQMH 

DQ(15:0) 


. 


2.4 SDRAM Support 

Table 2-2 shows the SDRAM memory types and densities that are supported by the applications 

processor. 

Table 2-2. SDRAM Memory Types Supported by the Applications Processor 

Partition Size 

(Mbyte/Partition) 

16-bit 

Bus 

32-bit 

Bus 

SDRAM 

Configuration 

(Words x 

Bits) 

Chip 

Size 

Number Chips/ 

Partition 

16-bit 

Bus 

32-bit 

bus 

Bank Bits x 

Row bits x 

Column 

Bits 

Maximum 

Memory 

(4 Partitions) 

16-bit 

Bus 

32-bit 

Bus 

Total Number 

of Chips 

16-bit 

Bus 

32-bit 

Bus 

2 Mbyte 4 Mbyte 1M x 16 16 Mbit 1 2 1 x 11 x 8 8 Mbyte 16 Mbyte 4 8 

4 Mbyte 8 Mbyte 2 M x 8 16 Mbit 2 4 1 x 11 x 9 16 Mbyte 32 Mbyte 8 16 

8 Mbyte 16 Mbyte 4 M x 4 16 Mbit 4 8 1 x 11 x 10 32 Mbyte 64 Mbyte 16 32 

N/A 8 Mbyte 2 M x 32 64 Mbit N/A 1 2 x 11 x 8 N/A 32 Mbyte N/A 4 

8 Mbyte 16 Mbyte 4 M x 16 64 Mbit 1 2 

1 x 13 x 8 

2 x 12 x 8 

32 Mbyte 64 Mbyte 4 8 


1 x 13 x 9 

2 x 12 x 9 

64 Mbyte 

128 

Mbyte 

8 16 


1 x 13 x 10 

2 x 12 x 10 

128 

Mbyte 

256 

Mbyte 

16 32 

16 Mbyte 32 Mbyte 8 M x 16 128 Mbit 1 2 2 x 12 x 9 64 Mbyte 

128 

Mbyte 

4 8 

32 Mbyte 64 Mbyte 16 M x 8 128 Mbit 2 4 2 x 12 x 10 

128 

Mbyte 

256 

Mbyte 

8 16 

64 Mbyte N/A 32 M x 4 128 Mbit 4 8 2 x 12 x 11 

256 

Mbyte 

N/A 16 32 

32 Mbyte 64 Mbyte 

16 M x 

16 

256 Mbit 1 2 2 x 13 x 9 

128 

Mbyte 

256 

Mbyte 

4 8 

64 Mbyte N/A 32 M x 8 256 Mbit 2 4 2 x 13 x 10 

256 

Mbyte 

N/A 8 16 



2.5 SDRAM Address Mapping 

SDRAM Address Mapping is shown in Table 2-3 and Table 2-4. 

Table 2-3. Normal Mode Memory Address Mapping 

SDRAM 

# Bits 

Bank x 

Row x 

Col 

The applications processor pin mapping to SDRAM devices 

(The address lines at the top of the columns are the processor address lines) 

Device Technology A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 

1Mx16 16Mbit 1x11x8 BS0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 



1x12x8 BS0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 




1x13x8 BS0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 




2Mx32 64Mbit 2x11x8 BS1 BS0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 

2x11x9 BS1 BS0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 


4Mx16/4Mx32 64Mbit/128Mbit 2x12x8 BS1 BS0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 



32Mx4 128Mbit 2x12x11 BS1 BS0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 

8Mx32 256Mbit 2x13x8 BS1 BS0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 

16Mx16 256Mbit 2x13x9 BS1 BS1 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 



Table 2-4. Applications Processor Compatibility Mode Address Line Mapping 

SDRAM 

# Bits 

Bank x 

Row x 

Col 

The applications processor pin mapping to SDRAM devices 

(The address lines at the top of the columns are the processor address lines) 

Device Technology A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 




1x12x8 A11 BS0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 




1x13x8 A12 A11 BS0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 




2Mx32 64Mbit 2x11x8 BS1 BS0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 






32Mx4 128Mbit 2x12x11 BS1 BS0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 

8Mx32 256Mbit 2x13x8 A12 BS1 BS0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 

16Mx16 256Mbit 2x13x9 A12 BS1 BS0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 

2.6 Static Memory 

2.6.1 Overview 

The applications processor external memory bus interface supports the following static memory 

types: 

• Synchronous and asynchronous Burst mode and Page mode Flash 

• Synchronous Mask ROM (SMROM) 

• Page Mode ROM 

• SRAM 

• SRAM-like Variable Latency I/O (VLIO) 

• PCMCIA expansion memory 

• Compact Flash 



Memory types are programmable through the memory interface configuration registers. 

Six chip selects control the static memory interface, nCS. All are configurable for nonburst 

ROM or Flash memory, burst ROM or Flash, SRAM, or SRAM-like variable latency I/O devices. 

The variable latency I/O interface differs from SRAM in that it allows the data ready input signal 

(RDY) to insert a variable number of memory-cycle-wait states. The data bus width for each chip 

select region may be programmed to be 16-bit or 32-bit. nCS are also configurable for 

Synchronous Static Memory. 

For SRAM and variable latency I/O implementations, DQM signals are used for the write 

byte enables, where DQM corresponds to the MSB. The applications processor supplies 26- 

bits of byte address for access of up to 64 Mbytes per chip select. However, when the address is 

sent out on the MA pins, MA reflects the actual address, not the byte address. The lower one or two 

internal address bits are truncated appropriately. 

2.6.2 Boot Time Defaults 

Booting configuration is device specific. For example, you cannot use a 32-bit memory booting 

configuration with a PXA210 applications processor. Table 2-5 shows valid booting configurations 

based on processor type, while Table 2-6 shows boot selection definitions. See Section 7.10.2, 

“Boot-Time Configurations” in the Intel® PXA250 and PXA210 Applications Processors 

Developer’s Manual for more detailed descriptions of these Boot Time Configurations. 

Table 2-5. Valid Booting Configurations Based on Package Type 

Processor Type 

0 (PXA210 

applications 

processor) 

Valid Booting Configurations 

001 

101 

111 

000 

1 (PXA250 

applications 

processor) 

001 

100 

101 

110 

111 

Table 2-6. BOOT_SEL Definitions (Sheet 1 of 2) 

BOOT_SEL 

2 1 0 

Boot From . . . 

0 0 0 Asynchronous 32-bit ROM 


1 0 0 

1 32-bit Synchronous Mask ROM (64 Mbits) 

2 16-bit Synchronous Mask ROMs = 32-bits (32 Mbits each) 



Table 2-6. BOOT_SEL Definitions (Sheet 2 of 2) 

BOOT_SEL 

2 1 0 

Boot From . . . 

1 0 1 1 16-bit Synchronous Mask ROM (64 Mbits) 

1 1 0 2 16-bit Synchronous Mask ROMs = 32-bits (64 Mbits each) 

1 1 1 1 16-bit Synchronous Mask ROM (64 Mbits) 

2.6.3 SRAM / ROM / Flash / Synchronous Fast Flash Memory 

Options 

Table 2-7 contains the AC specification for SRAM / ROM / Flash / Synchronous Fast Flash. 

Table 2-7. SRAM / ROM / Flash / Synchronous Fast Flash AC Specifications 

Symbol 

Description 

MEMCKLK 

99.5 118.0 132.7 147.5 165.9 

Units 

Notes 

SRAM / ROM / Flash / Synchronous Fast Flash (WRITES) (Asynchronous) 

tromAS 

MA(25:0) setup to nOE, nSDCAS (as 

nADV) asserted 

10 8.5 7.5 6.8 6 ns, 1 

tromAH 

MA(25:0) hold after nCS, nOE, 

nSDCAS (as nADV) de-asserted 

10 8.5 7.5 6.8 6 ns, 1 

tromASW MA(25:0) setup to nWE asserted 30 25.5 22.5 20.4 18 ns, 3 

tromAHW MA(25:0) hold after nWE de-asserted 10 8.5 7.5 6.8 6 ns, 1 

tromCES nCS setup to nWE asserted 20 17 15 13.6 12 ns, 2 

tromCEH nCS hold after nWE de-asserted 10 8.5 7.5 6.8 6 ns, 1 

tromDS 

tromDSWH 

tromDH 

tromNWE 

MD(31:0), DQM(3:0) write data setup to 

nWE asserted 


nWE de-asserted 

MD(31:0), DQM(3:0) write data hold 

after nWE de-asserted 

nWE high time between beats of write 

data 

NOTES: 

1. This number represents 1 MEMCLK period 

2. This number represents 2 MEMCLK periods 

10 8.5 7.5 6.8 6 ns, 1 

20 17 15 13.6 12 ns, 2 

10 8.5 7.5 6.8 6 ns, 1 

20 17 15 13.6 12 ns, 2 

2.6.4 Variable Latency I/O Interface Overview 

Both reads and writes for VLIO differ from SRAM in that the PXA250 applications processor 

samples the data-ready input, RDY. The RDY signal is level sensitive and goes through a two-stage 

synchronizer on input. When the internal RDY signal is high, the I/O device is ready for data 

transfer. This means that for a transaction to complete at the minimum assertion time for either 

nOE or nPWE (RDF+1), the RDY signal must be high two clocks prior to the minimum assertion 

time for either nOE or nPWE (RDF-1). Data will be latched on the rising edge of memclk once the 

internal RDY signal is high and the minimum assertion time of RDF+1 has been reached. Once the 



data has been latched, the address may change on the next rising edge of MEMCLK or any cycles 

thereafter. The nOE or nPWE signal de-asserts one MEMCLK after data is latched. Before a 

subsequent data beat, nOE or nPWE remains deasserted for RDN+1 memory cycles. The chip 

select and byte selects, DQM[3:0], remain asserted for one memory cycle after the burst’s final 

nOE or nPWE deassertion. Refer to Figure 2-3 for 32-Bit Variable Latency I/O read timing and 

Figure 2-8 for Variable Latency I/O Interface AC Specifications 

Figure 2-3. 32-Bit Variable Latency I/O Read Timing (Burst-of-Four, One Wait Cycle Per Beat) 

0ns 100ns 200ns 300ns 

memlk 

nCS[0] 

MA[25:2] 

MA[1:0] 

tAS 

0 1 2 3 

"00" 

nOE 

tASRW0 

tCES 

tAH 

RDN+1 

tASWN 

RDF+1+Waits 

tCEH 

RRR+1 

nPWE 

RDnWR 

RDY 

MD[31:0] 

DQM[3:0] 

"0000" 

nCS[1] 

A8867-01 

Table 2-8. Variable Latency I/O Interface AC Specifications (Sheet 1 of 2) 

Symbol 

Description 

MEMCKLK 

99.5 118.0 132.7 147.5 165.9 

Units 

Notes 

Variable Latency IO Interface (VLIO) (Asynchronous) 

tvlioAS MA(25:0) setup to nCS asserted 10 8.5 7.5 6.8 6 ns, 1 

tvlioASRW 

MA(25:0) setup to nOE or nPWE 

asserted 

10 8.5 7.5 6.8 6 ns, 1 

tvlioAH 

MA(25:0) hold after nOE or nPWE deasserted 

10 8.5 7.5 6.8 6 ns, 1 

tvlioCES nCS setup to nOE or nPWE asserted 20 17 15 13.6 12 ns, 2 

tvlioCEH 

nCS hold after nOE or nPWE deasserted 

10 8.5 7.5 6.8 6 ns, 1 



Table 2-8. Variable Latency I/O Interface AC Specifications (Sheet 2 of 2) 

Symbol 

Description 

MEMCKLK 

99.5 118.0 132.7 147.5 165.9 

Units 

Notes 

tvlioDSW 

tvlioDSWH 

tvlioDHW 

tvlioDHR 

tvlioRDYH 


nPWE asserted 


nPWE de-asserted 

MD(31:0), DQM(3:0) hold after nPWE 

de-asserted 

MD(31:0) read data hold after nOE deasserted 

RDY hold after nOE, nPWE deasserted 

nPWE, nOE high time between beats of 

tvlioNPWE 

write or read data 

NOTES: 



10 8.5 7.5 6.8 6 ns, 1 

20 17 15 13.6 12 ns, 2 

10 8.5 7.5 6.8 6 ns, 1 

0 0 0 0 0 ns 

0 0 0 0 0 ns 

20 17 15 13.6 12 ns, 2 

2.6.5 External Logic for PCMCIA Implementation 

The PXA250 applications processor requires external glue logic to complete the PCMCIA socket 

interface. Figure 2-4, “Expansion Card External Logic for a Two-Socket Configuration” on page 2- 

12 and Figure 2-5, “Expansion Card External Logic for a One-Socket Configuration” on page 2-13 

show general solutions for one and two socket configurations. Use GPIO or memory-mapped 

external registers to control the PCMCIA interface’s reset, power selection (V CC and V PP ), and 

drive enables. These diagrams show the logical connections necessary to support hot insertion 

capability. For dual-voltage support, level shifting buffers are required for all the applications 

processor input signals. Hot insertion capability requires each socket be electrically isolated from 

the other and from the remainder of the memory system. If one or both of these features are not 

required, you may eliminate some of the logic shown in these diagrams. The applications processor 

allows either 1-socket or 2-socket solutions. In the 1-socket solution, only minimal glue logic is 

required (typically for the data transceivers, address buffers, and level shifting buffers.) To achieve 

this some of the signals are routed through dual-duty GPIO pins. The nOE of the transceivers is 

driven through the PSKTSEL pin, which is not needed in the one-socket solution. The DIR pin of 

the transceiver is driven through the RDnWR pin. A GPIO is used for the three-state signal of the 

address and nPWE lines. These signals are used for memories other than the card interface and 

must be three-stated. 

Note: 

Note: 

For 2.5 V VCCN, 5 V to 2.5 V level shifters are required. 

PCMCIA is only implemented on the PXA250 applications processor. 

In the 2-socket solution, all pins assume their normal duties and glue logic is necessary for proper 

operation of the system. The pull-ups shown are included for compliance with PC Card Standard - 

Volume 2 - Electrical Specification. Remove power from these pull-ups during sleep to avoid 

unnecessary power consumption. Refer to Table 2-9 for the PCMCIA or compact Flash card 

interface AC specifications. 



Figure 2-4. Expansion Card External Logic for a Two-Socket Configuration 


Applications 

Processor 

D(15:0) 

Socket 0 

D(15:0) 

nPCEx 

DIR OE# 

Socket 1 

D(15:0) 

nPOE 

nPIOR 

nPCEx 

DIR OE# 

GPIO(w) 

CD1# 

CD2# 

GPIO(x) 

CD1# 

CD2# 

GPIO(y) 

RDY/BSY# 

GPIO(z) 

RDY/BSY# 

PSKTSEL 

MA(25:0) 

nPREG 

A(25:0) 

REG# 

nPCE(1:2) 

nPOE, 

nPWE 

nPIOW, 

nPIOR 

6 6 

6 

CE(1:2)# 

OE# 

WE# 

IOR# 

IOW# 

WAIT# 

A(25:0) 

REG# 

CE(1:2)# 

OE# 

WE# 

IOR# 

IOW# 

nPWAIT 

WAIT# 

IOIS1616# 

nPIOIS16 

IOIS1616# 

A8863-02 



Figure 2-5. Expansion Card External Logic for a One-Socket Configuration 

PXA250 Socket 0 

MD 

D 

DIR 

nOE 

RD/nWR 

GPIO 

GPIO 

PSKTSEL 

GPIO 

GPIO 

MA 

nPCD0 

nPCD1 

PRDY_BSY0 

PADDR_EN0 

nCD 

nCD 

RDY/nBSY 

A 

nPWE 

nWE 

nPREG 

nPCE 

nPOE 

nPIOR 

nPIOW 

nPWAIT 

nIOIS16 

5V to 3.3V 

5V to 3.3V 

nREG 

nCE 

nOE 

nIOR 

nIOW 

nWAIT 

nIOIS16 

Table 2-9. Card Interface (PCMCIA or Compact Flash) AC Specifications (Sheet 1 of 2) 

Symbol 

Description 

MEMCKLK 

99.5 118.0 132.7 147.5 165.9 

Units 

Notes 

Card Interface (PCMCIA or Compact Flash) (Asynchronous) 

tcardAS 

tcardAH 

tcardDS 

MA(25:0), nPREG, PSKTSEL, nPCE 

setup to nPWE, nPOE, nPIOW, or 

nPIOR asserted 

MA(25:0), nPREG, PSKTSEL, nPCE 

hold after nPWE, nPOE, nPIOW, or 

nPIOR de-asserted 

MD(31:0) setup to nPWE, nPOE, 

nPIOW, or NPIOR asserted 

20 17 15 13.6 12 ns, 1 

10 8.5 7.5 6.8 6 ns, 1 

10 8.5 7.5 6.8 6 ns, 1 



Table 2-9. Card Interface (PCMCIA or Compact Flash) AC Specifications (Sheet 2 of 2) 

Symbol 

Description 

MEMCKLK 

99.5 118.0 132.7 147.5 165.9 

Units 

Notes 

tcardDH 

tcardCMD 

MD(31:0) hold after nPWE, nPOE, 

nPIOW, or NPIOR de-asserted 

nPWE, nPOE, nPIOW, or nPIOR 

command assertion 

10 8.5 7.5 6.8 6 ns, 1 

30 25.5 22.5 20.4 18 ns, 1 

NOTE: 

1. These numbers are minmums. They can be much larger based on the programmable Card Interface 

timing registers. 

2.6.6 DMA / Companion Chip Interface 

Connect a companion chip to the applications processor via: 

• Alternate Bus Master Mode 

• Variable Latency I/O 

• Flow through DMA 

These connections are illustrated in Figure 2-6 and Figure 2-7. 



Figure 2-6. Alternate Bus Master Mode 


EXTERNAL SYSTEM 

SDCKE 


Memory 

Controller 

SDCLK 

nSDCS(0) 

nSDRAS 

nSDCAS 

nWE 

MA 

External 

SDRAM 

Bank 0 

DQM 

MD 

MBREQ 

MBGNT 


GPIO 

Block 

GPIO (MBGNT) 

GPIO (MBREQ) 

Companion 

Chip 



Figure 2-7. Variable Latency I/O 



Memory 

Controller 

EXTERNAL SYSTEM 

nCS(0,1,2,3,4,5) 

nOE 

nPWE 

MA 

DQM 

Companion 

Chip 

MD 

RDY 



2.7 System Memory Layout Guidelines 

2.7.1 System Memory Topologies (Min and Max Simulated 

Loading) 

Figure 2-8, Figure 2-9, Figure 2-10, and Figure 2-11 are the topologies that where simulated to 

develop the trace length recommendations in Section 2.7.2. These topologies are for reference 

only. 

Figure 2-8. CS, CKE, DQM, CLK, MA minimum loading topology 

CS, CKE, DQM, 

CLK, MA 

SDRAM 

Figure 2-9. CS, CKE, DQM, CLK, MA Maximum Loading Topology 

SDRAM 

CS, CKE, DQM, 

CLK, MA 

SDRAM 

SDRAM 

SDRAM 

Figure 2-10. MD Minimum Loading Topology 

MD 

SDRAM 



Figure 2-11. MD maximum loading topology 

SDRAM 

SDRAM 

MD 

AUX 

AUX 

AUX 

AUX 

2.7.2 System Memory Recommended Trace Lengths 

Table 2-10 details the minimum and maximum trace lengths that were simulated for the 

applications processor. These trace lengths are not the absolute trace lengths that will work given 

the loading conditions. The trace lengths in Table 2-10 are measured from the applications 

processor to the individual component pins. The board impedance for the simulations was 60ohm 

+/- 10%. 

Table 2-10. Minimum and Maximum Trace Lengths for the SDRAM Signals 

Signal 

Min 

Trace Length 

Max 

Trace Length 

CS, CKE, DQM 0.75 in 4.5 in 

CLK 1.0 in 4.25 in 

MA 1.0 in 4.5 in 

MD 1.0 in 4.25 in 


LCD Display Controller 3 

This chapter describes sample hardware connections from the PXA250 applications processor to 

various types of LCD controllers. Active (TFT) as well as passive (DSTN) displays are discussed 

as well as single and dual panel displays. These should not be considered the only possible ways to 

connect an LCD panel to the PXA250 applications processor, but should serve as a reference to 

assist with hardware design considerations. Other panels, for example panels without L_FCLK or 

L_LCLK, have been successfully connected to the PXA250. 

3.1 LCD Display Overview 

The PXA250 applications processor supports both active and passive LCD displays. Active 

displays generally produce better looking images, but at a higher cost. Passive displays are 

generally less expensive, but their displays are inferior to active displays. However, recent 

advances in dithering technology are closing the quality gap between passive and active displays. 

Note: 

Names used for “LCD Panel Pin” are representative names and may not match those on all LCD 

panels. Refer to the LCD panel reference documentation for the actual name. 

3.2 Passive (DSTN) Displays 

Several different types of passive displays are available in both color and monochrome. These 

maybe single or dual panel displays. Additionally, some monochrome displays use double-pixel 

data mode (twice the number of pixels as a normal monochrome display). With the exception of the 

number of data pins required, all of these choices affect the software configuration and support, not 

the system hardware design. In fact, most passive displays use a single interconnection scheme. For 

information on the software changes and performance considerations of the various display 

options, refer to the PXA250 and PXA210 Applications Processors Developer’s Manual. 

Passive displays drive dithered data to the LCD panel - which means that for each pixel clock cycle 

a single data line drives an ON/OFF signal for one color of a single pixel. 

Table 3-1 describes the number of L_DD pins required for the various types of passive displays, as 

well as which LCD data pins are used for which panel (upper or lower). 

Table 3-1. LCD Controller Data Pin Utilization (Sheet 1 of 2) 

Color/ 

Monochrome 

Panel 

Single/ 

Dual Panel 

Double-Pixel 

Mode 

Screen Portion 

Pins 

Monochrome Single No Whole L_DD 

Monochrome Single Yes Whole L_DD 1 

Top 

L_DD 

Monochrome Dual No 

Bottom 

L_DD 

Color Single N/A Whole L_DD 

PXA250 and PXA210 Applications Processor Design Guide 3-1

LCD Display Controller 

Table 3-1. LCD Controller Data Pin Utilization (Sheet 2 of 2) 

Color/ 

Monochrome 

Panel 

Single/ 

Dual Panel 

Double-Pixel 

Mode 

Screen Portion 

Pins 

Color Dual N/A 

NOTE: 1. Double pixel data mode (DPD)=1. 

Top 

Bottom 

L_DD 

L_DD 

For passive displays, the pins described in Table 3-2 are required connections between the PXA250 

applications processor and your LCD panel. 

Table 3-2. Passive Display Pins Required 

PXA250 Pin LCD Panel Pin PIn Type 1 Definition 

L_DD DU_x, DL_x Output 

Data lines used to transmit either four or eight data values at a time to 

the LCD display. For monochrome displays, each pin value represents 

a single pixel; for passive color, groupings of three pin values represent 

one pixel (red, green, and blue data values). Either the bottom four pins 

(L_DD), the bottom 8 pins (L_DD) or all 16 pixel data pins 

(L_DD)will be used as shown in Table 3-1 

L_PCLK Pixel_Clock Output 

L_LCLK Line_Clock Output 

L_FCLK Frame_Clock Output 

L_BIAS Bias Output 

N/A Vcon 2 N/A 

Pixel Clock - used by the LCD display to clock the pixel data into the 

line shift register. 

Line Clock - used by the LCD display to signal the end of a line of pixels 

that transfers the line data from the shift register to the screen and 

increment the line pointers. 

Frame Clock - used by the LCD displays to signal the start of a new 

frame of pixels that resets the line pointers to the top of the screen. 

AC bias used to signal the LCD display to switch the polarity of the 

power supplies to the row and column axis of the screen to counteract 

DC offset. 

Contrast Voltage - Adjustable voltage input to LCD panel - external 

voltage circuitry is required (no pin available on PXA250). 

NOTES: 

1. “Pin Type” is in reference to the PXA250 applications processor. Therefore, outputs are pins that drive a signal from the processor to another 

device. 

2. Vcon is a signal external to the PXA250 applications processor. Please refer to “Contrast Voltage” on page 8 

3.2.1 Typical Connections for Passive Panel Displays 

The following diagrams are typical connections and serve a guide for designing systems which 

contain passive LCD displays. Panels differ on which is the panel’s lest significant bit (Refer to the 

LCD panel reference documentation for the lest significant bit.) Each figure indicates the top-left 

pixel (1,1) bit. While dual panels indicates the top-left pixel (1,n/2) of the upper and lower panels 

and color passive panels show the top-left-pixel color bits. 

3.2.1.1 Passive Monochrome Single Panel Displays 

Figure 3-1 is a typical single-panel-monochrome passive display connection. 

3-2 PXA250 and PXA210 Applications Processor Design Guide


Figure 3-1. Single Panel Monochrome Passive Display Typical Connection 

L_DD0 - Top left 

L_DD1 

L_DD2 

L_DD3 

D0 

D1 

D2 

D3 

PXA250 Processor 

LCD Display 

L_PCLK 

L_LCLK 

L_FCLK 

L_BIAS 

Pixel_Clock 

Line_Clock 

Frame_Clock 

Bias 

3.2.1.2 Passive Monochrome Single Panel Displays, Double-Pixel Data 

Figure 3-2 shows typical connections for a single-panel-monochrome passive display using 

double-pixel data mode. 

Figure 3-2. Passive Monochrome Single Panel Displays, Double-Pixel Data Typical 

Connection 


L_DD0 - Top left 

L_DD1 

L_DD2 

L_DD3 

L_DD4 

L_DD5 

L_DD6 

L_DD7 

D0 

D1 

D2 

D3 

D4 

D5 

D6 

D7 

LCD Display 

L_PCLK 

L_LCLK 

L_FCLK 

L_BIAS 

Pixel_Clock 

Line_Clock 

Frame_Clock 

Bias 

3.2.1.3 Passive Monochrome Dual Panel Displays 

Figure 3-3 is a typical dual-panel-monochrome passive display connection. 



Figure 3-3. Passive Monochrome Dual Panel Displays Typical Connection 

L_DD0 - Top left for upper panel 

L_DD1 

L_DD2 

L_DD3 

DU_0 

DU_1 

DU_2 

DU_3 

Upper Panel 


L_PCLK 

L_LCLK 

L_FCLK 

L_BIAS 

Pixel_Clock 

Line_Clock 

Frame_Clock 

Bias 

LCD Display 

L_DD4 - Top left for lower panel 

L_DD5 

L_DD6 

L_DD7 

DL_0 

DL_1 

DL_2 

DL_3 

Lower Panel 

3.2.1.4 Passive Color Single Panel Displays 

Figure 3-4 is a typical single-panel-color passive display connection. 

Figure 3-4. Passive Color Single Panel Displays Typical Connection 


L_DD0 

L_DD1 

L_DD2 

L_DD3 

L_DD4 

L_DD5 - Top left Blue 

L_DD6 - Top left Green 

L_DD7 - Top left Red 

D0 

D1 

D2 

D3 

D4 

D5 

D6 

D7 

LCD Display 

L_PCLK 

L_LCLK 

L_FCLK 

L_BIAS 

Pixel_Clock 

Line_Clock 

Frame_Clock 

Bias 

3.2.1.5 Passive Color Dual Panel Displays 

Figure 3-5 is a typical dual-panel-color passive display connection. 



Figure 3-5. Passive Color Dual Panel Displays Typical Connection 


L_DD0 

L_DD1 

L_DD2 

L_DD3 

L_DD4 

L_DD5 - Top left Blue for upper panel 

L_DD6 - Top left Green for upper panel 

L_DD7 - Top left Red for upper panel 

L_PCLK 

L_LCLK 

L_FCLK 

L_BIAS 

DU_0 

DU_1 

DU_2 

DU_3 

DU_4 

DU_5 

DU_6 

DU_7 

Pixel_Clock 

Line_Clock 

Frame_Clock 

Bias 

Upper Panel 

LCD Display 

L_DD8 

L_DD9 

L_DD10 

L_DD11 

L_DD12 

L_DD13 - Top left Blue for lower panel 

L_DD14 - Top left Green for lower panel 

L_DD15 - Top left Red for lower panel 

DL_0 

DL_1 

DL_2 

DL_3 

DL_4 

DL_5 

DL_6 

DL_7 

Lower Panel 

3.3 Active (TFT) Displays 

Because data is sent to the panel as raw 16-bit pixel data, active displays require16 data pins in 

order to transfer the pixel data from the controller. All 16 data lines are also required to drive one 

pixel value. The 16 bits of data describe the intensity level of the red, green and blue for each pixel. 

Typically, this is formatted as 5 bits for red, 6 bits for green and 5 bits for blue, but this can vary by 

display and is controlled by the software writing to the frame buffer. Refer to the display datasheet 

to ensure that the correct the PXA250 applications processor LCD data lines are connected to the 

correct LCD panel data lines. 

Many active displays actually have more than 16 data lines - usually 18 (6 of each color). For these 

panels it is recommended that the most significant lines of the panel lines are connected to the data 

lines from the PXA250 applications processor. This maintains the panel’s full range of colors but 

increases the granularity of the color spectrum with an insufficient number of data lines. All unused 

panel data lines can be tied either high or low. Other options include tying the LSB of red and blue 

to the next bit, R1 or B1. 

For active displays, connect the pins described in Table 3-3 between the PXA250 applications 

processor and the LCD panel. 



Table 3-3. Active Display Pins Required 

PXA250 Pin LCD Panel Pin PIn Type 1 Definition 

L_DD 

R,G, 

B 

Output 

L_PCLK Clock Output 

L_LCLK Horizontal Sync Output 

L_FCLK Vertical Sync Output 

L_BIAS 

DE (Data 

Enable) 

Output 

N/A Vcon 2 N/A 

Data lines used to transmit the 16 bit data values to the LCD display. 

Pixel Clock - used by the LCD display to clock the pixel data into the 

line shift register. In active mode this clock transitions constantly. 

Line Clock - used by the LCD display to signal the end of a line of pixels 

that transfers the line data from the shift register to the screen and 

increment the line pointers. Also signals the panel to start a new line. 

Frame Clock - used by the LCD displays to signal the start of a new 

frame of pixels that resets the line pointers to the top of the screen. 

AC biases used in active mode as a data enable signal when data 

should be latched by the pixel clock from the data lines. 

Contrast Voltage - Adjustable voltage input to LCD panel - external 

voltage circuitry is required (no pin available on the PXA250 

applications processor). 

NOTES: 

1. In reference to the PXA250 applications processor. Therefore, outputs are pins that drive a signal from the PXA250 

applications processor to another device. 

2. Vcon is a signal external to the PXA250 applications processor. Please refer to Section 3.5.1, “Contrast Voltage” on page 8. 

3.3.1 Typical connections for Active Panel Displays 

Figure 3-6, “Active Color Display Typical Connection” on page 7 shows a typical connection for 

an active panel display and should serve as a guide for designing systems which contain active 

LCD displays. The MSB of each color is indicated. The panel is 18-bit, with the LSB of red and 

blue tied to ground. 



Note: 

This example shows 6 red, 6 green and 6 blue bits on the LCD panel. However, different active 

display panels might have more or different data lines. Consult the LCD panel manufacturer’s 

datasheet for the actual data lines. 

Figure 3-6. Active Color Display Typical Connection 


L_DD0 

L_DD1 

L_DD2 

L_DD3 

L_DD4 - MSB of Blue 

L_DD5 

L_DD6 

L_DD7 

L_DD8 

L_DD9 

L_DD10 - MSB of Green 

L_DD11 

L_DD12 

L_DD13 

L_DD14 

L_DD15 - MSB of Red 

B0 

B1 

B2 

B3 

B4 

B5 

G0 

G1 

G2 

G3 

G4 

G5 

R0 

R1 

R2 

R3 

R4 

R5 

LCD Panel 

L_PCLK 

L_LCLK 

L_FCLK 

L_BIAS 

Clock 

Horizontal Sync 

Vertical Sync 

Data Enable 

3.4 PXA250 Pinout 

Table 3-4 describes the ball positions for the LCD controller on the PXA250 applications 

processor. 

Table 3-4. PXA250 LCD Controller Ball Positions (Sheet 1 of 2) 

Pin Name 

L_DD0 

L_DD1 

L_DD2 

L_DD3 

L_DD4 

L_DD5 

L_DD6 

L_DD7 

L_DD8 

L_DD9 

L_DD10 

L_DD11 

Ball Position 

E7 

D7 

C7 

B7 

E6 

D6 

E5 

A6 

C5 

A5 

D5 

A4 



Table 3-4. PXA250 LCD Controller Ball Positions (Sheet 2 of 2) 

Pin Name 

L_DD12 

L_DD13 

L_DD14 

L_DD15 

L_FCLK 

L_LCLK 

L_PCLK 

Bias 

Ball Position 

A3 

A2 

C3 

B3 

E8 

D8 

B8 

A8 

3.5 Additional Design Considerations 

3.5.1 Contrast Voltage 

Many displays, both active and passive, include a pin for adjusting the display contrast voltage. 

This is a variable analog voltage that is supplied to the panel via an voltage source on the system 

board. The contrast voltage is adjusted via a variable resistor on the circuit board. 

The required voltage range and current capabilities vary between panel manufacturers. Consult the 

datasheet for your panel to determine the variable voltage circuit design. Ensure that the contrast 

voltage is stable, otherwise visual artifacts might result. Possible contrast-voltage circuits are often 

suggested by the panel manufacturers. 

3.5.2 Backlight Inverter 

One potential source of noise for the LCD panel can be the backlight inverter. Since this is a high 

voltage device with frequent voltage inversions, it has the potential to inject spurious noise onto the 

LCD panel lines. To minimize noise: 

• Use a shielded backlight inverter 

• Physically locate the inverter as far away from the LCD data lines and system board as 

possible, usually located with the LCD panel 

If power consumption is an issue, chose a backlight inverter that can be disabled through software. 

This lets you save power by automatically disabling the backlight if no activity occurs within a 

preset period of time 

3.5.3 Signal Routing and Buffering 

Signal transmission rates between the LCD controller and the LCD panel are moderate, which 

helps to simplify the design of the LCD system. The minimum Pixel Clock Divider (PCD) value 

results in a pixel clock rate of one half of the LCLK (this is not the L_LCLK of the LCD 

controller.) The maximum LCLK for the PXA250 applications processor is 166 MHz, resulting in 

a maximum pixel clock rate of 83 MHz. Thus, use of 100 MHz design considerations are sufficient 

to ensure LCD panel signal integrity. 



However, typical transfer rates are considerably less than 83 Mhz. For example, an 800x600 color 

active display running at 75 Hz requires a transfer rate of approximately 36 MHz. To determined 

this, calculate the number of pixels (800 x 600 = 480,000) and multiply by the screen refresh rate 

(75 Hz). Since active panels replace 1 pixel of data with every clock cycle this determines the final 

transfer rate. Active displays normally do not require refresh rates as high as 75 Hz, so you may use 

a lower refresh rate to reduce transmission rates even more. 

Passive displays often do require refresh rates greater than 75 Hz, which transfers more pixels each 

clock cycle. For instance, a color passive display with 8 data lines transfers 2 2/3 pixels’ worth of 

data each clock cycle. This divides the transmission rate by 2 2/3. Further reductions in the transfer 

rate come by using dual panel displays which use twice as many data lines to transfer data - halving 

the rate again. 

Generally, this gives you lower transfer rates to even large displays and thus simpler design 

considerations and fewer layout constraints. 

When laying out your design, minimize trace length of the LCD panel signals and allow sufficient 

spacing between signals to avoid crosstalk. Crosstalk decreases the signal integrity, especially the 

data line signals. 

LCD system design is not considered to be critical as infrequent or single bit errors are, typically, 

not noticed by the user. Also, the errors are transitory, as the old data is constantly being replaced 

with new data. Slower panel refresh rates increase the likelihood that a single error is noticed by the 

user. However, there is an counteracting effect in that slower refresh rates relax LCD timing and 

therefore result in fewer screen transmission errors. There are other factors related to choosing a 

refresh rate for an LCD system, most significant is the impact on system bandwidth. 

If you must use excessively long or poorly routed signals, one possible solution is to add buffers 

between the PXA250 applications processor and the LCD panel. This helps strengthen the LCD 

panel signal levels and synchronizes signal timing. However, this is usually not required as the 

LCD panel timings are fairly relaxed. Since the LCD display essentially operates asynchronously 

from the processor, the propagation delay of the buffers is not a major concern. 

When mounting the LCD panel, it is critical to shield the touchscreen control lines, if present. 

Noise from the LCD panel and its control signals can become injected into the touchscreen control 

lines, causing spurious touch interrupts or loss of resolution. 

3.5.4 Panel Connector 

Most LCD panels are connected to the system board via a connector, instead of being directly 

mounted on the system board. This increases flexibility and ease of manufacture. Typically the 

manufacturer of the panel recommends a particular connector for the panel. Follow the panel 

manufacturer’s recommendation. 




USB Interface 4 

4.1 Self Powered Device 

Figure 4-1 shows the USB interface connection for a self-powered device. The 0 ohm resistors are 

optional, and if not used, then connect USB UDC+ directly to the device UDC+ and connect USB 

UDC- directly to device UDC-. The device UDC+ and UDC- pins match the impedance of a USB 

cable, 90 ohms, without the use of external series resistors. You may install 0 ohm resistors on your 

board to compensate for minor differences between the USB cable and your board trace 

impedance. 

The 5 to 3.3 voltage divider is required since the device GPIO pins cannot exceed 3.3 V. This 

voltage divider can be implemented in a number of ways. The most robust and expensive solution 

is to use a MAX6348 Power-On-Reset device. This solution produces a very clean signal edge and 

minimizes signal bounce. The more inexpensive solution is to use a 3.3 V line buffer with 5 V 

tolerant inputs. This solution does not reduce signal bounce, so software must compensate by 

reading the GPIO signal after it stabilizes. A third solution is to implement a signal bounce 

minimization circuit that is 5 V tolerant, but produces a 3.3 V signal to the GPIO pin. 

Note: 

If GPIOn and GPIOx are the same pin, never put the device to sleep while the USB cable is 

connected to the device. During sleep, the USB controller is in reset and will not respond to the 

host; after sleep, the device will not respond to its host-assigned address. 

Figure 4-1. Self Powered Device 

USB 5V 

5V to 3.3V 

GPIOn 

USB UDC+ 

USB GND 

470K 

1.5K 

0 ohm 

(optional) 

0 ohm 

(optional) 

USB UDC- 

GPIOx 

UDC+ 

UDC- 

Board GND 

4.1.1 Operation if GPIOn and GPIOx are Different Pins 

Any GPIO pins can be defined as GPIOn and GPIOx. GPIOn should be a GPIO which can bring 

the device out of sleep. Out of reset, configure GPIOx as an input that causes the UDC+ line to 

float. GPIOn is configured as an input that causes an interrupt whenever a rising or falling edge is 


USB Interface 

detected. When an interrupt occurs, software must read the GPIOn pin to determine if the cable is 

connected or not. GPIOn is 1 if the cable is connected or 0 if the cable is disconnected. If a USB 

connect is detected, then software enables the UDC peripheral and drives a 1 onto the GPIOx pin to 

indicate to the host PC a fast USB device is connected. If a USB disconnect is detected, then 

software must configure the GPIOx pin as an input, configure the GPIOn pin to detect a wakeup 

event, and then put the part into sleep mode. 

Also, at any time, you may use software to put the part into sleep mode. Before entering sleep 

mode, configure the GPIOx pin as an input to cause the UDC+ line to float. This looks like a 

disconnect to the host PC. The device can then be put into sleep mode. When the device becomes 

active, software must drive a 1 onto the GPIOx pin to indicate to the host PC a fast USB device has 

been connected. 

4.1.2 Operation if GPIOn and GPIOx are the Same Pin 

Out of reset, GPIOn is configured as an input and configured to cause an interrupt whenever a 

rising or falling edge is detected. When an interrupt occurs, software must read the GPIOn pin to 

determine if the cable is connected or not. This pin is 1 if the cable is connected or 0 if the cable is 

disconnected. If the USB cable is connected, then software must enable the UDC peripheral before 

the host sends the first USB command. If the USB cable is not connected, then software must 

configure the GPIOn pin to detect a wakeup event, and then put the part into sleep mode. 

4.2 Bus Powered Device 

The applications processor cannot support a bus powered device model. When the host sends a 

suspend, the device is required to consume less than 500 uA (Section 7.2.3 of the USB spec version 

1.1). The applications processor cannot limit its current consumption to 500 uA unless it enters 

sleep mode. If it enters sleep mode, all USB registers are reset and it does not respond to its hostassigned 

address. 


MultiMediaCard (MMC) 5 

The MultiMediaCard (MMC) is a low cost data storage and communication media. The MMC 

supports the translation protocol from a standard MMC or Serial Peripheral Interface (SPI) bus to 

an application bus. 

The MMC controller in the applications processor is compliant with The MultiMediaCard System 

Specification, Version 2.1. The only exception is one and three byte data transfers are not 

supported. The MMC controller is capable of communicating with a card in MMC or SPI mode. 

Your application is responsible for specifying the MMC controller communication mode. 

5.1 Schematics 

The MultiMediaCard (MMC) controller on the applications processor supports MMC and SDCard 

devices. (The MMC controller does not support SDCard nibble mode.) This section presents 

several options on how to connect each type of device to the controller. 

5.1.1 Signal Description 

MMC controller signal functions are described in Table 5-1. 

Table 5-1. MMC Signal Description 

Signal Name Input/Output Description 

MMCLK Output Clock signal to MMC 

MMCMD BiDirectional Command line 

MMDAT BiDirectional Data line 

MMCCS0 Output Chip Select 0 

MMCCS1 Output Chip Select 1 

The MMCLK, MMCCS0, and MMCCS1 signals are routed through alternate functions within the 

applications processor general purpose input/output (GPIO) module. Each of these signals can be 

programmed to a particular GPIO pin. 

The signals defined in The MultiMediaCard System Specification for an MMC device are CLK, 

CMD, and DAT which correspond to the MMCLK, MMCMD, and MMDAT in the applications 

processor, respectively. The two chip selects in the controller are for the MMC SPI mode and 

correspond to the reserved pin of two different devices, defined in the specification. 

The signals defined in the Physical Layer Specification of the SD Memory Card Specifications for 

an SDCard device are CLK, CMD, and DAT0-DAT3. The obvious difference is the number of 

DAT signals. In addition, the socket for an SDCard contains mechanical switches for write protect 

(WP) and card detect (CD). For an SDCard to be connected to the MMC controller, only one data 

line, DAT0, is used. Otherwise the signal mapping remains the same as an MMC device. The WP 

and CD switches on the socket are discussed in Section 5.1.2, “How to Wire” on page 5-2. 


MultiMediaCard (MMC) 

5.1.2 How to Wire 

Notice in the example schematic (Figure 5-1, “Applications Processor MMC and SDCard Signal 

Connections” on page 5-3) an SDCard socket is used. The signals on the socket are defined in 

Table 5-2. 

Table 5-2. SDCard Socket Signals 

Signal Name Pin # 

DAT3 1 

CMD 2 

VSS1 3 

VDD 4 

CLK 5 

VSS2 6 

DAT0 7 

DAT1 8 

DAT2 9 

As stated previously, the PXA250 MMC controller can be connected to either an MMC device or 

an SDCard device, but you are limited to which device installs in which socket. Refer to Table 5-3 

for information on sockets and device supported by the MMC controller. 

Table 5-3. MMC Controller Supported Sockets and Devices 

Sockets 

Devices Supported 

SDCard socket 

MMC socket 

SDCard device 

MMC device 

MMC device 

Figure 5-1 is a schematic that supports both MMC and SDCard devices. In the schematic, the 

signals SA_MMCLK, SA_MMCMD, and SA_DAT correspond to the applications processor 

signals MMCLK, MMCMD, and MMDAT, respectively. These three signals are also directly 

connected to the socket. 



Figure 5-1. Applications Processor MMC and SDCard Signal Connections 

J10 

DC3P3V 

CHECK II 

Bottom Mount 

DAT2 0 

CD_DAT3 1 

CMD 

2 

VSS1 

3 

VDD 

4 

CLK 

5 

VSS2 

6 

DAT0 

7 

DAT1 

8 

WP 

COMM 

CD 

10 

11 

12 

R229 

100K 

DC3P3V 

MMC_WP 

MMC_C50 

R147 

SA_MMCCLK 

SA_MMDAT 

R150 

47.5K 

DC3P3V 

10K 

R226 

C91 

0K 

SA_MMCMD 

0.1uF 

R225 

0K 

DNI 

IF 

SD 

CARD Selection Resistors and Values 

Resistors SDCard MMC 

R226 

R227 

R225 

R228 

DNI 

DNI 

0 

100K 

0 

100K 

DNI 

DNI 

DNI IF MMC 

R227 

R228 

DC3P3V 

100K 

100K 

MMC_PWR 

DNI 

IF 

SD 

nMMC_DETECT 

DNI 

IF 

MMC 

U27 

MMC_ON 

DC5P5V 

1 

2 

3 

MIC5207- 3.38M5 

3.3V LDO REG 180ns 

VIN 

GND 

EN 

LE33 

VOUT 

BYP 

5 

4 

4.7uF 

1 

C92 

MMC_PWR 

2 

A8698-01 

MMC_CS0, which corresponds to the applications processor MMCCS0 signal, is connected to the 

socket at pin 1. This connection is the SPI mode chip select and is available on both MMC and 

SDCard. This pin is also labeled DAT3. DAT3 is only used with an SDCard in SDCard mode and 

not available on the applications processor MMC controller. 

The signals DAT1 and DAT2 are not connected because these are specific to SDCard operation in 

SDCard mode. 



Three other signals shown on the connector are COMM and the mechanical switches write protect 

(WP) and card detect (CD). WP and CD are both connected to COMM via a mechanical switch 

inside the socket when a device is inserted. 

Three other signals shown on the connector are COMM and the mechanical switches WP and CD. 

When a device is inserted in the example schematic (Figure 5-1), WP may be and CD is connected 

to COMM via a mechanical switch inside the socket 

SDCard devices have a write protect tab. Depending on the position of the tab, the WP signal may 

or may not be connected to the COMM signal. Connect the WP signal to a CPLD or other device 

capable of indicating to the driver software that the card is write protected. In this example, 

COMM is tied to a VCC and WP has a pull-down resistor. This causes a rising edge when the tab is 

in the write protect position and the WP signal remains low when the tab is in the read/write 

position. 

The CD signal, MMC_DETECT, indicates to the MMC controller when a card is installed. It is 

used for both an SDCard socket and an MMC socket. Since the MMC socket does not have the 

mechanical CD switch, other measures must be taken to produce a card detect. Thus, the SDCard 

and MMC cases are discussed separately. 

Note: 

While this schematic shows two ways to create a card detect, it is recommended that an SDCard 

socket be used if a card detect and write protection signal are desired even if only MMC devices 

are being used. 

5.1.2.1 SDCard Socket 

When using Figure 5-1, “Applications Processor MMC and SDCard Signal Connections” on 

page 5-3 as a template for your SDCard circuit design, all resistors labeled “DNI IF SD” should not 

be installed and all resistors labeled “DNI IF MMC” should be installed in the circuit. Removing 

R226 and inserting R225 causes the VSS2 signal on pin 6 to be tied to ground. Also, the SDCard 

needs a pull-down resistor in position R228. 

SDCard sockets have a card detect switch internal to the socket. The CD signal is physically 

connected to the COMM signal. Connect the CD signal to a CPLD or other device capable of 

indicating to the driver software that a card has been inserted in the socket. In this example, 

COMM is tied to a V CC and CD has a pull-down resistor. This causes a rising edge on CD when a 

card is inserted while the CD signal remains low if no card is in the socket. 

5.1.2.2 MMC Socket 

When using Figure 5-1, “Applications Processor MMC and SDCard Signal Connections” on 

page 5-3 as a template for your MMC circuit design, all resistors labeled “DNI IF MMC” should 

not be installed and all resistors labeled “DNI IF SD” should be installed in the circuit. This causes 

the VSS2 signal on pin 6 to be pulled-up through resistor R227. 

Unlike SDCard sockets, MMC sockets do not have a card detect or write protect switch. In order to 

implement this, a pull-up is placed on the VSS2 signal (pin 6 of the socket.) Since VSS2 and VSS1 

are connected internally on the MMC device, the signal called nMMC_DETECT on the schematic 

is driven low when the MMC device is inserted. 



Warning: 

Connecting VSS2 to something other than the power supply ground violates The MultiMediaCard 

System Specification, Version 2.1. Because the MMC specification does not state that VSS1 and 

VSS2 must be connected internal to the MMC device, the design in Figure 5-1 may not work with 

all MMC devices. Use caution when using the card detection method shown in Figure 5-1. 

5.1.3 Simplified Schematic 

Figure 5-2 shows another SDCard socket. In this case, all applications processor signals are 

connected to the socket. This socket does not have a common signal for the write protect and card 

detect and are connected to the two tabs shown on the left side of the diagram. Inserting a card into 

the socket may cause the write protect signal and will cause the card detect signal to change states 

and must be interpreted by the CPLD software. 

Figure 5-2. Applications Processor MMC to SDCard Simplified Signal Connection 

+3.3V 

12 13 

ESD 

GND 

Jx 

WP 

CD 

DAT1 

DAT0 

VSS2 

CLK 

VDD 

VSS1 

CMD 

CD/DAT3 

DAT2 

11 

10 

5638 SDMC_NORMAL_SPRG_EJCT 

Kyoc 10 5638 009 353 833 

8 

7 

6 

5 

4 

3 

2 

1 

9 

Rx 

10K Ω 

5% 0.1W 

Rx 

10K Ω 

5% 0.1W 

Rx 

10K Ω 

5% 0.1W 

Rx 

10K Ω 

5% 0.1W 

SD_WP 

SD_CD 

MMDAT 

MMCLK 

MMCMD 

MMCCS0 

A8699-01 



5.1.4 Pull-up and Pull-down 

Table 5-4 and Table 5-5 show the pull-up and pull-down resistors required for SDCard and MMC 

devices according to their respective specifications. 

Table 5-4. SDCard Pull-up and Pull-down Resistors 

Signal Pull-up or Pull-down Min Max Remark 

CMD pull-up 10kΩ 100kΩ Prevents bus floating 

DAT0-DAT3 pull-up 10kΩ 100kΩ Prevents bus floating 

WP 1 pull-up — — Any value sufficient to prevent bus floating 

NOTE: 1. This resistor is shown in the specification but the value is not specified 

Table 5-5. MMC Pull-up and Pull-down Resistors 

Signal Pull-up or Pull-down Min Max Remark 

CMD pull-up 4.7kΩ 100kΩ Prevents bus floating 

DAT pull-up 50kΩ 100kΩ Prevents bus floating 

5.2 Utilized Features 

The applications processor MultiMediaCard controller has these features: 

• Data transfer rates as fast as 20 Mbps 

• A16 bit response FIFO 

• Dual receive data FIFOs 

• Dual transmit FIFOs 

• Support for two MMCs in either MMC or SPI mode 

The sample schematics in this section support MMC and SDCard and are configured to use MMC 

or SPI mode. 

The applications processor MultiMediaCard controller and the MMC device have the same 

maximum data rate, 20 Mbps, so their communication rates are compatible. However, because the 

maximum applications processor MultiMediaCard controller data rate is 20 Mbps and the 

maximum SDCard data rate is 25 Mbps, SDCard devices are not utilized to their fullest extent. 

The circuit designs presented in this guide (Figure 5-1 and Figure 5-2) only show support for one 

SDCard or MMC device, but the applications processor MultiMediaCard controller handles as 

many as two devices. 


AC97 6 

The AC97 controller unit (ACUNIT) connects audio chips and codecs to the applications 

processor. It uses a six-wire interface to transmit and receive data from AC97 2.0 compliant 

codecs. The AC97 port is a bidirectional, serial PCM digital stream. A maximum of two codecs 

may be connected to the ACUNIT. 


The schematics for an AC97 connection are shown in Figure 6-1. The primary codec supplies the 

12.288 MHz clock to the AC97. This clock is then driven into the ACUNIT on the applications 

processor and the AC97 Secondary Codec. 

Figure 6-1. AC97 connection 

nACRESET 

SDATA_OUT 


AC97 

Controller 

SYNC (48KHz) 

SDATA_IN_0 

SDATA_IN_1 

BITCLK (12.288MHz) 

AC97 

Primary 

CODEC 

AC97 

Secondary 

Codec 


AC97 

6.2 Layout 

Because of the analog/digital nature of the codecs, it is important that proper mixed-signal layout 

procedures be followed. Intel recommends you follow the layout recommendations given in your 

Codec datasheet. Some general recommendations are: 

• Use a separate power supply for the analog audio portion of the design. 

• Place a digital power/ground plane keep-out underneath the analog portion. Use a separate 

analog ground plane. You can create an island inside the keep-out. Connect the digital ground 

pins of the codec to the digital ground. Keep the two ground planes on the same layer, with at 

least 1/8 of an inch separation between them. 

• Connect the two ground planes underneath your codec with a 0 ohm jumper. Add optional Do 

Not Populate 0 ohm jumpers between analog and digital ground at the power supply. 

Excessive noise on the board may be reduced by installing the 0 ohm resistor. 

• Do not to route digital signals underneath the analog portion. Digital traces must go over the 

digital ground plane, analog traces over the analog plane. 

• Buffer any digital signals to or from the codec that go off the board, for example, if your codec 

is on a daughter card. 

• Fill the areas between analog traces with copper tied to the analog ground. Fill the regions 

between digital traces with copper tied to the digital ground. 

• Locate the decoupling capacitors for the analog portion as close to the codec as possible. 


I 2 C 7 

The Inter-Integrated Circuit (I 2 C) bus interface unit lets the applications processor serve as a 

master and slave device residing on the I 2 C bus. The I 2 C bus is a serial bus developed by Philips 

Corporation consisting of a two-pin interface. SDA is the serial data line and SCL is the serial 

clock line. 

Using the I 2 C bus lets the applications processor interface to other I 2 C peripherals and 

microcontrollers for system management functions. The serial bus requires a minimum of 

hardware for an economical system to relay status and reliability information to an external device. 

The I 2 C bus interface unit is a peripheral device that resides on the applications processor internal 

bus. Data is transmitted to and received from the I 2 C bus via a buffered interface. Control and 

status information is relayed through a set of memory-mapped registers. Refer to the I 2 C Bus 

Specification for complete details on I 2 C bus operation. 


The I 2 C bus is used by many different applications. This reference guide presents two possible 

methods for using the I 2 C bus interface. The first method controls a digital-to-analog converter 

(DAC) to vary the DC voltage to the processor core. The second method expands the capabilities of 

an existing compact flash socket. 

7.1.1 Signal Description 

The I 2 C bus interface unit signals are SDA and SCL. Table 7-1 describes the function of each 

signal. 

Table 7-1. I 2 C Signal Description 

Signal Name Input/Output Description 

SDA BiDirectional Serial data 

SCL BiDirectional Serial clock 

The I 2 C bus serial operation uses an open-drain, wired-AND bus structure, which allows multiple 

devices to drive the bus lines and to communicate status about events such as arbitration, wait 

states, error conditions and so on. For example, when a master drives the clock (SCL) line during a 

data transfer, it transfers a bit on every instance that the clock is high. When the slave is unable to 

accept or drive data at the rate that the master is requesting, the slave can hold the clock line low 

between the high states to insert a wait interval. The master’s clock can only be altered by a slow 

slave peripheral keeping the clock line low or by another master during arbitration. 

The I 2 C bus lets you design a multi-master system; meaning more than one device can initiate data 

transfers at the same time. To support this feature, the I 2 C bus arbitration relies on the wired-AND 

connection of all I 2 C interfaces to the I 2 C bus. Two masters can drive the bus simultaneously 

provided they are driving identical data. The first master to drive SDA high while another master 

drives SDA low loses the arbitration. The SCL line consists of a synchronized combination of 

clocks generated by the masters using the wired-AND connection to the SCL line. 


I2C 

7.1.2 Digital-to-Analog Converter (DAC) 

Figure 7-1 shows the schematic for connecting the I 2 C interface to a Linear Technology 

micropower DAC. The DAC output is connected to the buck converter feedback path and is 

controlled by the I 2 C bus interface unit. The DAC can modify the voltage of the feedback path, 

which effects the processor core voltage. 

Figure 7-1. Linear Technology DAC with I 2 C Interface 

DC3P3V 

R165 1.00M 

U30 

4 

VCC 

LTC1663 

SA_I2C_SDA 

1 

SDA 

VOUT 

3 

SA_I2C_SCL 

5 

SCL 

GND 

2 

LTEP 

LTC1663C35 

A8752-01 

The signals SA_I2C_SDA and SA_I2C_SCL correspond to the applications processor signals 

SDA and SCL, respectively. 

7.1.3 Other Uses of I 2 C 

Figure 7-2 shows the I 2 C signals passing through an analog switch to a compact flash socket. Since 

the CF socket has all of the signals to support two CF cards, and this design only uses one CF card, 

the signals meant for a second card are being used for alternate functions. If you decide not to use a 

CF card, a different application using a CF card socket could be designed to utilize the I 2 C bus 

interface unit. If this alternate function is used, the I 2 C bus can be enabled to the CF socket by 

asserting the signal SA_I2C_ENAB shown in the diagram. If the user decides to use a CF Card, 

negate the SA_I2C_ENAB signal so the I 2 C bus traffic does not interfere with the CF card. 

Note: 

The CF card socket is disabled if a device is inserted in the expansion bus. 


. 

I2C 

Figure 7-2. Using an Analog Switch to Allow a Second CF Card 

DC3P3V 

U26 

MAX4547 

V* 

2 

SA_I2C_SCL 

8 

COM_1 

7 

IN_7 

NC_1 

1 

CF_I2C_SCL 

SA_I2C_SDA 

SA_I2C_ENAB 

4 

3 

COM_7 

IN_2 

NC_2 

GND 

5 

6 

CI_I2C_SDA 

AAAF 

A8750-01 

7.1.4 Pull-Ups and Pull-Downs 

The I 2 C Bus Specification, available from Philips Corporation, states: 

The external pull-up devices connected to the bus lines must be adapted to accommodate the shorter 

maximum permissible rise time for the Fast-mode I 2 C-bus. For bus loads up to 200 pF, the pull-up 

device for each bus line can be a resistor; for bus loads between 200 pF and 400 pF, the pull-up device 

can be a current source (3 mA max.) or a switched resistor circuit. 

The design presented in this guide is not intended for loads larger than 200pF, so the pull-up device is a 

resistor as shown in Figure 7-3. 

Figure 7-3. I 2 C Pull-Ups and Pull-Downs 

DC3P3V 

SA_I2C_SCL 

SA_I2C_SDA 

R4 

4.99K 

R5 

4.99K 

A8751-01 


I2C 

The actual value of the pull-up is system dependant and a guide is presented in the I 2 C Bus 

Specification on determining the maximum and minimum resistors to use when the system is 

intended for standard or fast-mode I 2 C bus devices. 

7.2 Utilized Features 

The applications processor I 2 C bus interface unit is compatible with the two pin interface 

developed by Phillips Corporation. A complete list of features and capabilities can be found in the 

I 2 C Bus Specification. 


Power and Clocking 8 

8.1 Operating Conditions 

Table 8-1 shows voltage, frequency, and temperature specifications for the applications processor 

for four different ranges. The temperature specification for each range is constant; the frequency 

range is operation voltage dependent. On a prototype design, the VCC/PLL_VCC regulator should 

have a range from 0.85 V to 1.65 V. PLL_VCC and VCC must be connected together on the board 

or driven by the same supply. 

Table 8-1. Voltage, Temperature, and Frequency Electrical Specifications 

Symbol Description Min Typical Max 

t A Ambient Temperature -40°C — 85° C 

V VSS VSS, VSSN, VSSQ Voltage -0.3 V 0V 0.3 V 

V VCCQ VCCQ 3.0 V 3.3 V 3.6 V 

V VCCN_H VCCN @ 3.3V 3.0 V 3.3 V 3.6 V 

V VCCN_L VCCN @ 2.5V 2.375 V 2.5 V 2.625 V 

Low Voltage Range (PXA210 and PXA250) 

V VCC_L VCC, PLL_VCC Voltage, Low Range 0.8075 V 0.85 V 0.935 V 

f TURBO_L Turbo Mode Frequency, Low Range 99.5 MHz — 132.7 MHz 

f SDRAM_L External Synchronous Memory Frequency, Low Range — — 66.4 MHz 

Medium Voltage Range (PXA250 and PXA210) 

V VCC_M VCC, PLL_VCC Voltage, Mid Range 0.9 V 1.0 V 1.1 V 

f TURBO_M Turbo Mode Frequency, Mid Range 99.5 MHz — 199.1 MHz 

f SDRAM_M External Synchronous Memory Frequency, Mid Range — — 99.5 MHz 

High Voltage Range (PXA250 applications processor only) 

V VCC_H VCC, PLL_VCC Voltage, High Range 1.0 V 1.1 V 1.21 V 

f TURBO_H Turbo Mode Frequency, High Range 99.5 MHz — 298.7 MHz 

f SDRAM_H External Synchronous Memory Frequency, High Range — — 99.5 MHz 

Peak Voltage Range (PXA250 applications processor only) 

V VCC_P VCC, PLL_VCC Voltage, Peak Range 1.17 V 1.3 V 1.43 V 

f TURBO_P Turbo Mode Frequency, Peak Range 99.5 MHz — 398.2 MHz 

f SDRAM_P External Synchronous Memory Frequency, Peak Range — — 99.5 MHz 

NOTE: When VCCN=2.5 V, the I/O signals that are supplied by VCCN are 2.5 V tolerant only. Do not apply 3.3 V to any pin 

supplied by VCCN in this case. 


Power and Clocking 

8.2 Electrical Specifications 

Table 8-2 provides the Absolute Maximum ratings for the applications processor. These parameters 

may not be exceeded or the part may be permanently damaged. Operation at Absolute Maximum 

Ratings is not guaranteed. 

Table 8-2. Absolute Maximum Ratings 

Symbol Description Min Max 

T S Storage Temperature -40° C 125° C 

V SS_O 

V CC_O 

Offset Voltage between any two VSS pins 

(VSS, VSSQ, VSSN) 

Offset Voltage between any of the following pins: 

VCCQ, VCCN 

-0.3 V 0.3 V 

-0.3 V 0.3 V 

V CC_HV 

Voltage Applied to High Voltage Supplies 

(VCCQ, VCCN) 

VSS-0.3 V 

VSS+4.0 V 

V CC_LV 

Voltage Applied to Low Voltage Supplies 

(VCC, PLL_VCC) 

VSS-0.3 V 

VSS+1.45 V 

V IP Voltage Applied to non-Supply pins except XTAL pins VSS-0.3 V 

max of 

VCCQ+0.3 V, 

VSS+4.0 V 

V IP_X 

Voltage Applied to XTAL pins 

(PXTAL, PEXTAL, TXTAL, TEXTAL) 

VSS-0.3 V 

max of 

VCC+0.3 V, 

VSS+1.45 V 

V ESD 

Maximum ESD stress voltage, Human Body Model; 

Any pin to any supply pin, either polarity, or 

Any pin to all non-supply pins together, either polarity. 

Three stresses maximum. 

2000 V 

I EOS Maximum DC Input Current (Electrical Overstress) for any non-supply pin 5mA 

8.3 Power Consumption Specifications 

Power consumption on any highly integrated device is extremely dependent on the operating 

voltage, external switching activity, and external loading (shown in Table 8-3, “Power 

Consumption Specifications” on page 8-3). Because power consumption on the applications 

processor is optimized, power varies based on which functions are being performed and by the data 

and frequency requirements of the module. 

The maximum power consumption specification is determined by all units running at their 

maximum: processor speed, voltage, and loading conditions. This method generates a conservative 

power consumption value; however, power supply and thermal management design requires the 

highest possible power consumption for robust design.The applications processor’s maximum 

power consumption is calculated using the following conditions: 

• All peripheral units operating at maximum frequency and size configuration 

• All I/O loads maximum (50pF for Memory interface, 100pF for peripherals) 

• Core operating at worst case power scenario (hit rates adjusted for worst power) 

• All voltages at maximum of range 



Since few systems operate at maximum loading, performance, and voltage, a more optimal system 

design requires more typical power consumption parameters. These parameters are important when 

considering battery size and optimizing regulator efficiency. Typical systems operate with fewer 

modules active and at nominal voltage and load. Typical power consumption for the applications 

processor is calculated using these conditions: 

• SSP, STUART, USB, PWM, Timer, I2S peripherals operating 

• LCD enabled with 320x240x16bit color 

• MMC, AC97, BTUART, FFUART, ICP, I2C peripherals disabled 

• I/O loads at nominal (35pf for all pins) 

• Core operating at 98% Instruction Hit Rate, 95% Data Hit Rate 

• All voltages at nominal value 

The individual power supply specifications add up to more than the total because the operating 

conditions which cause maximum power consumption on each supply are sometimes mutually 

exclusive. 

Table 8-3. Power Consumption Specifications (Sheet 1 of 2) 

Symbol Description Min 1 Typical 1 Max 1 

Package, Frequency, and Voltage Range Independent Power Supplies 

P VCCQ Power from VCCQ Supply — 16 mW 115 mW 

Low Voltage Range (PXA210 and PXA250) 

P T_L Total Power, Low Range — 250 mW 550 mW 

P VCC_L Power from VCC Supply, Low Range — 110 mW 65 mW 

P VCCN_L 

@2.5V 

P VCCN_L 

@3.3V 

Power from VCCN Supply, Low Range — 65 mW 145 mW 

Power from VCCN Supply, Low Range — 120 mW 250 mW 

PT_IDLE_L Total Power, IDLE Mode, Low Range — 110mW — 

Medium Voltage Range (PXA250 and PXA210) 

P T_MM Total Power, Mid Range (PXA210 applications processor) — 350 mW 690 mW 

P T_MB Total Power, Mid Range (PXA250 applications processor) — 420 mW 840 mW 

P VCC_M Power from VCC Supply, Mid Range — 180 mW 130 mW 

P VCCN_MM 

P VCCN_MB 

@2.5V 

P VCCN_MB 

@3.3V 

Power from VCCN Supply, Mid Range (PXA210 applications 

processor) 


processor) 


processor) 

— 160 mW 325 mW 

— 100 mW 250 mW 

— 160 mW 440 mW 

PT_IDLE_M Total Power, IDLE Mode, Medium Range — 110mW — 

High Voltage Range (PXA250 applications processor only) 

P T_HB Total Power, High Range (PXA250 applications processor) — 450 mW 890 mW 

P VCC_H Power from VCC Supply, High Range — 275 mW 220 mW 



Table 8-3. Power Consumption Specifications (Sheet 2 of 2) 

Symbol Description Min 1 Typical 1 Max 1 

P VCCN_HB 

@2.5V 

P VCCN_HB 

@3.3V 

Power from VCCN Supply, High Range (PXA250 applications 

processor) 

Power from VCCN Supply, High Range (PXA250 applications 

processor) 

— 115 mW 250 mW 

— 160 mW 440 mW 

PT_IDLE_H Total Power, IDLE Mode, High Range — 135mW — 

Peak Voltage Range (PXA250 applications processor only) 

P T_P Total Power, Peak Range — 635 mW 950 mW 

P VCC_P Power from VCC Supply, Peak Range — 470 mW 360 mW 

P VCCN_P 

@2.5V 

P VCCN_P 

@3.3V 

Power from VCCN Supply, Peak Range — 115 mW 255 mW 

Power from VCCN Supply, Peak Range — 160 mW 440 mW 

PT_IDLE_H Total Power, IDLE Mode, High Range — 185mW — 

NOTE: 

1. These numbers are pre-silicon estimates, and will be replaced with the correct values when characterization is complete. 

8.4 Oscillator Electrical Specifications 

The applications processor contains two oscillators – 32.768 kHz and 3.6864 MHz; each chosen 

for a specific crystal. When choosing a crystal, match the crystal parameters as closely as possible. 

8.4.1 32.768 kHz Oscillator Specifications 

The 32.768 kHz Oscillator is connected between the TXTAL (amplifier input) and TEXTAL 

(amplified output). The 32.768 kHz specifications are shown in Table 8-4. 

Table 8-4. 32.768 kHz Oscillator Specifications (Sheet 1 of 2) 


Crystal Specifications - Typical is FOX NC38 

F XT Crystal Frequency, TXTAL/TEXTAL — 32.768 kHz — 

L MT Motional Inductance, TXTAL/TEXTAL — 6827.81 H — 

C MT Motional Capacitance, TXTAL/TEXTAL — 3.455 fF — 

R MT Motional Resistance, TXTAL/TEXTAL 6kΩ 16 kΩ 35 kΩ 

C OT Shunt Capacitance TXTAL to TEXTAL — 1.6 pF — 

C LT Load Capacitance TXTAL/TEXTAL — 12.5 pF — 

Amplifier Specifications 

V IH_X Input High Voltage, TXTAL 0.8 V*VCC — VCC 

V IL_X Input Low Voltage, TXTAL VSS — 0.2 V*VCC 

I IN_XT Input Leakage, TXTAL — — 1 µA 

C IN_XT Input Capacitance, TXTAL/TEXTAL — 18 pF 25 pF 



Table 8-4. 32.768 kHz Oscillator Specifications (Sheet 2 of 2) 


t S_XT Stabilization Time 2s — 10 s 

Board Specifications 

R P_XT Parasitic Resistance, TXTAL/TEXTAL to any node 20 MΩ — — 

C P_XT Parasitic Capacitance, TXTAL/TEXTAL, total — — 5pF 

C OP_XT Parasitic Shunt Capacitance, TXTAL to TEXTAL — — 0.4 pF 

To drive the 32.768 kHz crystal pins from an external source: 

• Drive the TEXTAL pin with a digital signal that has a low level near 0 V and a high level near 

VCC. Do not exceed VCC or go below VSS by more than 100 mV. The minimum slew rate is 

1V per µs. The maximum current drawn by the external clock source when the clock is at its 

maximum positive voltage should be about 1mA. 

• Float the TXTAL pin or drive it complementary to the TEXTAL pin, using the same voltage 

level, slew rate, and input current restrictions. 

8.4.2 3.6864 MHz Oscillator Specifications 

The 3.6864 MHz Oscillator is connected between the PXTAL (amplifier input) and PEXTAL 

(amplified output). The 3.6864 MHz specifications are shown in Table 8-5 

Table 8-5. 3.6864 MHz Oscillator Specifications 


Crystal Specifications - Typical is FOX HC49S 

F XP Crystal Frequency, PXTAL/PEXTAL — 3.6864 MHz — 

L MP Motional Inductance, PXTAL/PEXTAL — 0.50593 H — 

C MP Motional Capacitance, PXTAL/PEXTAL — 3.68488 fF — 

R MP Motional Resistance, PXTAL/PEXTAL 50 Ω 99.3 Ω 200 Ω 

C OP Shunt Capacitance PXTAL to PEXTAL — 1.7 pF — 

C LP Load Capacitance PXTAL/PEXTAL — 20 pF — 

Amplifier Specifications 

V IH_X Input High Voltage, PXTAL 0.8V*VCC — VCC 

V IL_X Input Low Voltage, PXTAL VSS — 0.2 V*VCC 

I IN_XP Input Leakage, PXTAL — — 10 µA 

C IN_XP Input Capacitance, PXTAL/PEXTAL — 40 pF 50 pF 

t S_XP Stabilization Time 17.8 ms — 67.8 ms 

Board Specifications 

R P_XP Parasitic Resistance, PXTAL/PEXTAL to any node 20 MΩ — — 

C P_XP Parasitic Capacitance, PXTAL/PEXTAL, total — — 5pF 

C OP_XP Parasitic Shunt Capacitance, PXTAL to PEXTAL — — 0.4 pF 

To drive the 3.6864 MHz crystal pins from an external source: 



• Drive the PEXTAL pin with a digital signal that has a low level near 0 V and a high level near 

VCC. Do not exceed VCC or go below VSS by more than 100 mV. The minimum slew rate is 

1 V per 100 ns. The maximum current drawn by the external clock source when the clock is at 

its maximum positive voltage should be about 1 mA. 

• Float the PXTAL pin or drive it complementary to the PEXTAL pin, using the same voltage 

level, slew rate, and input current restrictions. If floated, some degree of noise susceptibility 

will be introduced in the system, and it is therefore not recommended. 

8.5 Reset and Power AC Timing Specifications 

The applications processor asserts the nRESET_OUT pin in one of several modes: 

• Power On 

• Hardware Reset 

• Watchdog Reset 

• GPIO Reset 

• Sleep Mode 

The following sections give the timing and other specifications for the entry and exit of these 

modes. 

8.5.1 Power Supply Connectivity 

The PXA250 applications processor requires two or three externally-supplied voltage levels. 

VCCQ requires high voltage, VCCN requires high or medium voltage, and VCC and PLL_VCC 

require low voltage. PLL_VCC must be separated from other low voltage supplies. Depending on 

the availability of independent regulator outputs and the desired memory voltage, VCCQ may have 

to be separated from VCCN. VCCN does not have to be separated at the board level. 

Note: 

Shaded sections are not supported for the PXA210 applications processor. 

Table 8-6. PXA250 and PXA210 VCCN vs. VCCQ (Sheet 1 of 6) 

Pin 

Pin 

Count 

Alt_fn 

1-(in) 

Alt_fn 

2-(in) 

Alt_fn 

1-(out) 

Alt_fn 

2-(out) 

Signal Description and 

Comments 

Power 

Supply 

MA(25:0) 26 Main Memory Address Bus VCCN 

MD(31:16) 16 Main Memory Data Bus (high) VCCN 

MD(15:0) 16 Main Memory Data Bus (low) VCCN 

nOE 1 Main Memory Bus Output Enable VCCN 

nWE 1 Main Memory Bus Write Enable VCCN 

nSDRAS 1 Main Memory Bus RAS VCCN 

nSDCAS 1 Main Memory Bus CAS VCCN 

DQM(3:2) 2 

Main Memory Bus SDRAM byte 

selects 

VCCN 




Pin 

Pin 

Count 

Alt_fn 

1-(in) 

Alt_fn 

2-(in) 

Alt_fn 

1-(out) 

Alt_fn 

2-(out) 


Comments 

Power 

Supply 

DQM(1:0) 2 

nSDCS(3:2) 2 

nSDCS(1:0) 2 

SDCKE(1:0) 2 

Main Memory Bus SDRAM byte 

selects 

Main Memory Bus SDRAM chip 

selects 

Main Memory Bus SDRAM chip 

selects 

Main Memory Bus SDRAM clock 

enable 

VCCN 

VCCN 

VCCN 

VCCN 

SDCLK(2) 1 Main Memory Bus SDRAM clocks VCCN 

SDCLK(1:0) 2 Main Memory Bus SDRAM clocks VCCN 

RD/nWR 1 CC Steering Signal VCCN 

CS(0) 1 Static chip selects VCCN 

GP15 1 nCS_1 Active low chip select 1 VCCN 

GP18 1 RDY Ext. Bus Ready VCCN 

GP19 1 DREQ[1] Ext. Bus Master Request VCCN 

GP20 1 DREQ[0] Ext. Bus Master Request VCCN 

GP21 1 General Purpose I/O pin VCCN 

GP22 1 General Purpose I/O pin VCCN 

GP33 1 nCS[5] Active low chip select 5 VCCN 

GP48 1 nPOE Output Enable for Card Space VCCN 

GP49 1 nPWE Write Enable for Card Space VCCN 

GP50 1 nPIOR I/O Read for Card Space VCCN 

GP51 1 nPIOW I/O Write for Card Space VCCN 

GP52 1 nPCE[1] Card Enable for Card Space VCCN 

GP53 1 

MMCCLK 

nPCE[2] 

Card Enable for Card Space 

MMC CLock 

VCCN 

GP54 1 

MMCCLK 

pSKTSEL 

MMC CLock 

Socket Select for Card Space 

VCCN 

GP55 1 nPREG Card Address bit 26 VCCN 

GP56 1 nPWAIT Wait signal for Card Space VCCN 

GP57 1 nIOIS16 

Bus Width select for I/O Card 

Space 

VCCN 







Pin 

Pin 

Count 

Alt_fn 

1-(in) 

Alt_fn 

2-(in) 

Alt_fn 

1-(out) 

Alt_fn 

2-(out) 


Comments 

Power 

Supply 

MMCMD 1 MMC Command VCCQ 

MMDAT 1 MMC Data VCCQ 

AC_RESET_n 1 ac97 RESET VCCQ 

UDC+ 1 USB client high differential signal VCCQ 

UDC- 1 USB client low differential signal VCCQ 

SCL 1 I2C Clock VCCQ 

SDA 1 I2C Bidirectional Data VCCQ 

nRESET 1 Hardware reset VCCQ 

nRESET_OUT 1 Reset output VCCQ 

BOOT_SEL[2:0] 3 ROM Width Select (16/32) VCCQ 

PWR_EN 1 power enable VCCQ 

nBATT_FAULT 1 Battery Fault VCCQ 

nVDD_FAULT 1 VDD Fault VCCQ 

nTRST 1 JTAG Reset VCCQ 

TDI 1 JTAG Data In VCCQ 

TDO 1 JTAG Data Out VCCQ 

TMS 1 JTAG Mode Select VCCQ 

TCK 1 JTAG Clock VCCQ 

TESTCLK 1 TEST Clock VCCQ 

TEST 1 TEST mode VCCQ 

GP0 1 Reserved for sleep wakeup VCCQ 

GP1 1 GP_RST Active low GP_reset VCCQ 

GP2 1 General Purpose I/O pin VCCQ 




GP6 1 MMCCLK MMC Clock VCCQ 

GP7 1 48 MHz 48 mhz clock output VCCQ 

GP8 1 MMCCS0 MMC Chip Select 0 VCCQ 

GP9 1 MMCCS1 MMC Chip Select 1 VCCQ 

GP10 1 RTCCLK real time clock (1Hz) VCCQ 




Pin 

Pin 

Count 

Alt_fn 

1-(in) 

Alt_fn 

2-(in) 

Alt_fn 

1-(out) 

Alt_fn 

2-(out) 


Comments 

Power 

Supply 

GP11 1 3.6 MHz 3.6 MHz oscillator out VCCQ 

GP12 1 32 KHz 32 KHz out VCCQ 

GP13 1 MBGNT memory controller grant VCCQ 

GP14 1 MBREQ Alternate Bus Master Request VCCQ 

GP16 1 PWM0 PWM0 output VCCQ 

GP17 1 PWM1 PWM1 output VCCQ 

GP23 1 SCLK SSP clock VCCQ 

GP24 1 SFRM SSP Frame VCCQ 

GP25 1 TXD SSP transmit VCCQ 

GP26 1 RXD SSP receive VCCQ 

GP27 1 EXTCLK SSP ext_clk VCCQ 

BITCLK 

AC97 bit_clk 

GP28 1 

BITCLK 

BITCLK 

I2S bit_clk 

I2S bit_clk 

VCCQ 

BITCLK 

AC97 bit_clk 

GP29 1 

SDATA_IN0 

SDATA_ 

IN 

AC97 Sdata_in0 

I2S Sdata_in 

VCCQ 

GP30 1 

SDATA_ 

OUT 

SDATA_ 

OUT 

I2S Sdata_out 

AC97 Sdata_out 

VCCQ 

GP31 1 

SYNC 

SYNC 

I2S sync 

AC97 sync 

VCCQ 

GP32 1 

SDATA_IN1 

SYSCLK 

I2S sysclk 

AC97 Sdata_in1 

VCCQ 

GP34 1 

FFRXD 

FFUART receive 

MMCCS0 MMC Chip Select 0 

VCCQ 

GP35 1 CTS FFUART Clear to send VCCQ 

GP36 1 DCD FFUART Data carrier detect VCCQ 

GP37 1 DSR FFUART data set ready VCCQ 

GP38 1 RI FFUART Ring Indicator VCCQ 

GP39 1 


FFTXD 

FFUART transmit data 

VCCQ 




Pin 

Pin 

Count 

Alt_fn 

1-(in) 

Alt_fn 

2-(in) 

Alt_fn 

1-(out) 

Alt_fn 

2-(out) 


Comments 

Power 

Supply 

GP40 1 DTR FFUART data terminal Ready VCCQ 

GP41 1 RTS FFUART request to send VCCQ 

GP42 1 BTRXD BTUART receive data VCCQ 

GP43 1 BTTXD BTUART transmit data VCCQ 

GP44 1 CTS BTUART clear to send VCCQ 

GP45 1 RTS BTUART request to send VCCQ 

GP46 1 

ICP_RXD 

RXD 

ICP receive data 

STD_UART receive data 

VCCQ 

GP47 1 

TXD 

ICP_TXD 

STD_UART transmit data 

ICP transmit data 

VCCQ 

GP58 1 LDD[0] LCD data pin 0 VCCQ 








GP66 1 

MBREQ 

LDD[8] LCD data pin 8 

Alternate Bus Master Request 

VCCQ 

GP67 1 



VCCQ 

GP68 1 



VCCQ 

GP69 1 

MMCCLK 

MMC_CLK 


VCCQ 

GP70 1 

RTCCLK 

Real Time clock (1Hz) 


VCCQ 

GP71 1 

GP72 1 

3.6 MHz 3.6MHz Oscillator clock 


32 KHz 32 KHz clock 


VCCQ 

VCCQ 




Pin 

Pin 

Count 

Alt_fn 

1-(in) 

Alt_fn 

2-(in) 

Alt_fn 

1-(out) 

Alt_fn 

2-(out) 


Comments 

Power 

Supply 

GP73 1 

MBGNT 


memory controller grant 

VCCQ 

GP74 1 

LCD_FCL 

K 

LCD Frame clock 

VCCQ 

GP75 1 

LCD_LCL 

K 

LCD line clock 

VCCQ 

GP76 1 

LCD_PCL 

K 

LCD Pixel clock 

VCCQ 

GP77 1 

LCD_AC 

BIAS 

LCD AC Bias 

VCCQ 

PXTAL 1 3.6Mhz Crystal input 0.8 * VCC 

PEXTAL 1 3.6Mhz Crystal output 0.8 * VCC 

TXTAL 1 32khz Crystal input 0.8 * VCC 

TEXTAL 1 32khz Crystal output 0.8 * VCC 

8.5.2 Power On Timing 

The External Voltage Regulator and other power-on devices must provide the applications 

processor with a specific sequence of power and resets to ensure proper operation. This sequence is 

shown in Figure 8-1, “Power-On Reset Timing” on page 8-12 and detailed in Table 8-7, “Power- 

On Timing Specifications” on page 8-12. 

It is important that the applications processor power supplies be powered-up in a certain order to 

avoid high current situations. The required order is: 

1. VCCQ 

2. VCCN 

3. VCC and PLL_VCC 

VCCN may be powered at the same time as VCCQ, however do not apply power to VCCN before 

powering VCCQ. 



Note: 

If Hardware Reset is entered during Sleep Mode, the proper power-supply stabilization times and 

nRESET timing requirements indicated in Table 8-7, “Power-On Timing Specifications” on 

page 8-12 must be observed. 

Figure 8-1. Power-On Reset Timing 

t R_VCCQ 

VCCQ, PWR_EN 

t R_VCCN 

VCCN 

VCC 

nTRST 

t D_VCCN 

t D_VCC 

t R_VCC 

t D_NTRST 

t D_JTAG 

JTAG PINS 

nRESET 

t D_NRESET 

nRESET_OUT 

t D_OUT 

Note: nBATT_FAULT and nVDD_FAULT must be high before nRESET_OUT is 

deasserted or PXA250 enters Sleep Mode 

Table 8-7. Power-On Timing Specifications 


t R_VCCQ VCCQ Rise / Stabilization time 0.01 ms — 100 ms 

t R_VCCN VCCN Rise / Stabilization time 0.01 ms — 100 ms 

t R_VCC VCC, PLL_VCC Rise / Stabilization time 0.01 ms — 10 ms 

t D_VCCN Delay between VCCQ stable and VCCN applied 0ms — — 

t D_VCC Delay from VCCN stable and VCC, PLL_VCC applied 0ms — — 

t D_NTRST Delay between VCC, PLL_VCC stable and nTRST deasserted 50 ms — — 

t D_JTAG 

t D_NRESET 

t D_OUT 

Delay between nTRST deasserted and JTAG pins active, with 

nRESET asserted 

Delay between VCC, PLL_VCC stable and nRESET 

deasserted 

Delay between nRESET deasserted and nRESET_OUT 

deasserted 

0.03 ms — — 

50 ms — — 

18.1 ms — 18.2 ms 

8.5.3 Hardware Reset Timing 

The timing sequences shown in Figure 8-2 “Hardware Reset Timing” assumes the power supplies 

are stable at the assertion of nRESET. If the power supplies are unstable, follow the timings 

indicated in Section 8.5.2, “Power On Timing” on page 11. 



Figure 8-2. Hardware Reset Timing 

nRESET 

nRESET_OUT 

t DHW_NRESET 

t DHW_OUT 

t DHW_OUT_A 

Note: nBATT_FAULT and nVDD_FAULT must be high before nRESET is deasserted 

or PXA250 enters Sleep Mode 

Table 8-8. Hardware Reset Timing Specifications 


t DHW_NRESET Minimum assertion time of nRESET 0.001 ms — — 

t DHW_OUT_A Delay between nRESET Asserted and nRESET_OUT Asserted 0ms — 0.001 ms 

t DHW_OUT 

Delay between nRESET deasserted and nRESET_OUT 

deasserted 

18.1 ms — 18.2 ms 

8.5.4 Watchdog Reset Timing 

Watchdog Reset is an internally generated reset and therefore has no external pin dependencies. 

The nRESET_OUT pin is the only indicator of Watchdog Reset, and it stays asserted for 

t DHW_OUT . Refer to Figure 8-2, “Hardware Reset Timing” on page 8-13 for more information. 

8.5.5 GPIO Reset Timing 

GPIO Reset is generated externally. The pin used as the GPIO Reset is reconfigured as a standard 

GPIO after the reset propagates internally. Because the clock module is not reset by GPIO Reset, 

timing varies based on the frequency of the selected clock. Timing also varies in the Frequency 

Change Sequence (see Section 8.4.1, “32.768 kHz Oscillator Specifications” on page 4). Figure 

8-3 “GPIO Reset Timing” shows the possible GPIO Reset timing. 

Figure 8-3. GPIO Reset Timing 

t A_GP[1] 

GP[1] 

nRESET_OUT 

t DGP_OUT 

t DGP_OUT_A 

Note: nBATT_FAULT and nVDD_FAULT must be high before nRESET is deasserted 

or PXA250 enters Sleep Mode 



Table 8-9. GPIO Reset Timing Specifications 


t A_GP[1] Minimum assert time of GP[1] 1 in 3.6864 MHz input clock cycles 4 cycles — — 

t DGP_OUT_A 

Delay between GP[1] Asserted and nRESET_OUT Asserted in 

3.6864 MHz input clock cycles 

6 cycles — 8 cycles 

t DGP_OUT 

Delay between nRESET_OUT asserted and nRESET_OUT 

deasserted, Run or Turbo Mode 2 5 µs — 28 µs 

Delay between nRESET_OUT asserted and nRESET_OUT 

t DGP_OUT_F deasserted, during Frequency Change Sequence 3 5 µs — 380 µs 

NOTES: 

1. GP[1] is not recognized as a reset source again until configured to do so in software. Software should check the state of 

GP[1] before configuring it as a Reset to ensure no spurious reset is generated. 

2. Time is 512*N Processor Clock Cycles plus as many as 4 cycles of the 3.6864 MHz input clock. 

3. Time during the Frequency Change Sequence depends on the state of the PLL Lock Detector at the assertion of GPIO 

Reset. The Lock Detector has a maximum time of 350 us plus synchronization. 

8.5.6 Sleep Mode Timing 

Sleep Mode is internally asserted, and asserts the nRESET_OUT and PWR_EN signals. The 

sequence indicated in Figure 8-4 “Sleep Mode Timing” and detailed in Table 8-10, “Sleep Mode 

Timing Specifications” on page 8-14 are the required timing parameters for Sleep Mode. 

Figure 8-4. Sleep Mode Timing 

t A_GP[x] 

GP[x] 

PWR_EN 

VCC 

nVDD_FAULT 

tD_PWR_F 

t D_PWR_R 

t D_FAULT 

t DSM_VCC 

nRESET_OUT 

t DSM_OUT 

Note: nBATT_FAULT must be high or PXA250 will not exit Sleep Mode 

Table 8-10. Sleep Mode Timing Specifications (Sheet 1 of 2) 


t A_GP[x} Assert Time of GPIO Wake up Source (x=[15:0]) 91.6 µs — — 

t D_PWR_F Delay from nRESET_OUT asserted to PWR_EN deasserted 61 µs — 91.6 µs 

t D_PWR_R Delay between GP[x] asserted to PWR_EN asserted 30.5 µs — 122.1 µs 

t DSM_VCC Delay between PWR_EN asserted and VCC stable — — 10 ms 



Table 8-10. Sleep Mode Timing Specifications (Sheet 2 of 2) 


t D_FAULT 

t DSM_OUT 

t DSM_OUT_O 

Delay between PWR_EN asserted and nVDD_FAULT 

deasserted 

Delay between PWR_EN asserted and nRESET_OUT 

deasserted, OPDE Set 

Delay between PWR_EN asserted and nRESET_OUT 

deasserted, OPDE Clear 

— — 10 ms 

28.0 ms — 80 ms 

10.35 ms — 10.5 ms 

8.6 Memory Bus and PCMCIA AC Specifications 

This section gives the timing information for the following types of memory: 

• SRAM / ROM / Flash / Synchronous Fast Flash Asynchronous writes (Table 8-11) 

• Variable Latency I/O (Table 8-12) 

• Card Interface (PCMCIA or Compact Flash) (Table 8-13) 

• Synchronous Memories (Table 8-14) 

Table 8-11. SRAM / ROM / Flash / Synchronous Fast Flash AC Specifications (3.3 V) 

Symbol 

Description 

MEMCLK Frequency (MHz) 

99.5 118.0 132.7 147.5 165.9 

Notes 


tromAS 

tromAH 

MA(25:0) setup to nCS, nOE, nSDCAS (as nADV) 

asserted 

MA(25:0) hold after nCS, nOE, nSDCAS (as nADV) 

deasserted 

10 ns 8.5 ns 7.5 ns 6.8 ns 6 ns 1 

10 ns 8.5 ns 7.5 ns 6.8 ns 6 ns 1 

tromASW MA(25:0) setup to nWE asserted 30 ns 25.5 ns 22.5 ns 20.4 ns 18 ns 2 

tromAHW MA(25:0) hold after nWE deasserted 10 ns 8.5 ns 7.5 ns 6.8 ns 6 ns 1 

tromCES nCS setup to nWE asserted 20 ns 17 ns 15 ns 13.6 ns 12 ns 3 

tromCEH nCS hold after nWE deasserted 10 ns 8.5 ns 7.5 ns 6.8 ns 6 ns 1 

tromDS MD(31:0), DQM(3:0) write data setup to nWE asserted 10 ns 8.5 ns 7.5 ns 6.8 ns 6 ns 1 

tromDSWH 

tromDH 

MD(31:0), DQM(3:0) write data setup to nWE 

deasserted 

MD(31:0), DQM(3:0) write data hold after nWE 

deasserted 

20 ns 17 ns 15 ns 13.6 ns 12 ns 3 

10 ns 8.5 ns 7.5 ns 6.8 ns 6 ns 1 

tromNWE nWE high time between beats of write data 20 ns 17 ns 15 ns 13.6 ns 12 ns 3 

NOTES: 






Table 8-12. Variable Latency I/O Interface AC Specifications (3.3 V) 

Symbol 

Description 


99.5 118.0 132.7 147.5 165.9 

Notes 


tvlioAS MA(25:0) setup to nCS asserted 10 ns 8.5 ns 7.5 ns 6.8 ns 6 ns 1 

tvlioASRW MA(25:0) setup to nOE or nPWE asserted 10 ns 8.5 ns 7.5 ns 6.8 ns 6 ns 1 

tvlioAH MA(25:0) hold after nOE or nPWE deasserted 10 ns 8.5 ns 7.5 ns 6.8 ns 6 ns 1 

tvlioCES nCS setup to nOE or nPWE asserted 20 ns 17 ns 15 ns 13.6 ns 12 ns 2 

tvlioCEH nCS hold after nOE or nPWE deasserted 10 ns 8.5 ns 7.5 ns 6.8 ns 6 ns 1 

tvlioDSW MD(31:0), DQM(3:0) write data setup to nPWE asserted 10 ns 8.5 ns 7.5 ns 6.8 ns 6 ns 1 

tvlioDSWH 

MD(31:0), DQM(3:0) write data setup to nPWE 

deasserted 

20 ns 17 ns 15 ns 13.6 ns 12 ns 2 

tvlioDHW MD(31:0), DQM(3:0) hold after nPWE deasserted 10 ns 8.5 ns 7.5 ns 6.8 ns 6 ns 1 

tvlioDHR MD(31:0) read data hold after nOE deasserted 0 ns 0 ns 0 ns 0 ns 0 ns — 

tvlioRDYH RDY hold after nOE, nPWE deasserted 0 ns 0 ns 0 ns 0 ns 0 ns — 

nPWE, nOE high time between beats of write or read 

tvlioNPWE 

data 

NOTES: 



20 ns 17 ns 15 ns 13.6 ns 12 ns 2 

Table 8-13. Card Interface (PCMCIA or Compact Flash) AC Specifications (3.3 V) 

Symbol 

Description 


99.5 118.0 132.7 147.5 165.9 

Notes 

tcardAS 

tcardAH 

tcardDS 


MA(25:0), nPREG, PSKTSEL, nPCE setup to nPWE, 

nPOE, nPIOW, or nPIOR asserted 

MA(25:0), nPREG, PSKTSEL, nPCE hold after nPWE, 

nPOE, nPIOW, or nPIOR deasserted 

MD(31:0) setup to nPWE, nPOE, nPIOW, or nPIOR 

asserted 

20 ns 17 ns 15 ns 13.6 ns 12 ns 1 

10 ns 8.5 ns 7.5 ns 6.8 ns 6 ns 1 

10 ns 8.5 ns 7.5 ns 6.8 ns 6 ns 1 

tcardDH 

MD(31:0) hold after nPWE, nPOE, nPIOW, or nPIOR 

deasserted 

10 ns 8.5 ns 7.5 ns 6.8 ns 6 ns 1 

tcardCMD nPWE, nPOE, nPIOW, or nPIOR command assertion 30 ns 25.5 ns 22.5 ns 20.4 ns 18 ns 1 

NOTE: 

1. These numbers are minimums. They can be much longer based on the programmable Card Interface timing registers. 



Table 8-14. Synchronous Memory Interface AC Specifications (3.3 V) 

Symbol Description MIN MAX Notes 1 

SDRAM / SMROM 

tsynCLK SDCLK period 10 ns 20 ns 2 

tsynCMD nSDCAS, nSDRAS, nWE, nSDCS assert time 1 sdclk — — 

tsynRCD nSDRAS to nSDCAS assert time 1 sdclk — — 

tsynCAS nSDCAS to nSDCAS assert time 2 sdclk — — 

tsynSDOS 

MA(25:0), MD(31:0), DQM(3:0), nSDCS(3:0), nSDRAS, nSDCAS, nWE, nOE, 

SDCKE(1:0), RDnWR output setup time to SDCLK(2:0) rise 

5ns — 3 

tsynSDOH 


SDCKE(1:0), RDnWR output hold time from SDCLK(2:0) rise 

5ns — 3 

tsynSDIS MD(31:0) read data input setup time from SDCLK(2:0) rise 0.5 ns — 

tsynDIH MD(31:0) read data input hold time from SDCLK(2:0) rise 1.5 ns — — 

Fast Flash (Synchronous READS only) 

tffCLK SDCLK period 15 ns 20 ns 4 

tffAS MA(25:0) setup to nSDCAS (as nADV) asserted 0.5 sdclk — — 

tffCES nCS setup to nSDCAS (as nADV) asserted 0.5 sdclk — — 

tffADV nSDCAS (as nADV) pulse width 1 sdclk — — 

tffOS nSDCAS (as nADV) deassertion to nOE assertion 3 sdclk — — 

tffCEH nOE deassertion to nCS deassertion 4 sdclk — — 

NOTES: 

1. These numbers are for a maximum 99.5 MHz MEMCLK and 99.5 MHz output SDCLK. 

2. SDCLK for SDRAM and SMROM can be at the slowest, divide-by-2 of the 99.5 MHz MEMCLK. It can be 99.5 MHz at the 

fastest. 

3. This number represents 1/2 SDCLK period. 

4. SDCLK for Fast Flash can be at the slowest, divide-by-2 of the 99.5 MHz MEMCLK. It can be divide-by-2 of the 132.7 MHz 

MEMCLK at its fastest. 



Table 8-15. SRAM / ROM / Flash / Synchronous Fast Flash AC Specifications (2.5 V) 

Symbol 

Description 


99.5 118.0 132.7 147.5 165.9 

Notes 


tromAS 

tromAH 

tromASW 

tromAHW 

tromCES 

tromCEH 

tromDS 

tromDSWH 

tromDH 

tromNWE 

MA(25:0) setup to nCS, nOE, nSDCAS (as nADV) 

asserted 

MA(25:0) hold after nCS, nOE, nSDCAS (as nADV) 

deasserted 

MA(25:0) setup to nWE asserted 

MA(25:0) hold after nWE deasserted 

nCS setup to nWE asserted 

nCS hold after nWE deasserted 

MD(31:0), DQM(3:0) write data setup to nWE asserted 

MD(31:0), DQM(3:0) write data setup to nWE 

deasserted 

MD(31:0), DQM(3:0) write data hold after nWE 

deasserted 

nWE high time between beats of write data 

NOTES: 




TBD 



Table 8-16. Variable Latency I/O Interface AC Specifications (2.5 V) 

Symbol 

Description 


99.5 118.0 132.7 147.5 165.9 

Notes 


tvlioAS 

tvlioASRW 

tvlioAH 

tvlioCES 

tvlioCEH 

tvlioDSW 

tvlioDSWH 

tvlioDHW 

tvlioDHR 

tvlioRDYH 

MA(25:0) setup to nCS asserted 

MA(25:0) setup to nOE or nPWE asserted 

MA(25:0) hold after nOE or nPWE deasserted 

nCS setup to nOE or nPWE asserted 

nCS hold after nOE or nPWE deasserted 

MD(31:0), DQM(3:0) write data setup to nPWE asserted 

MD(31:0), DQM(3:0) write data setup to nPWE 

deasserted 

MD(31:0), DQM(3:0) hold after nPWE deasserted 

MD(31:0) read data hold after nOE deasserted 

RDY hold after nOE, nPWE deasserted 

nPWE, nOE high time between beats of write or read 

tvlioNPWE 

data 

NOTES: 



TBD 

Table 8-17. Card Interface (PCMCIA or Compact Flash) AC Specifications (2.5 V) 

Symbol 

Description 


99.5 118.0 132.7 147.5 165.9 

Notes 

tcardAS 

tcardAH 

tcardDS 

tcardDH 

tcardCMD 


MA(25:0), nPREG, PSKTSEL, nPCE setup to nPWE, 

nPOE, nPIOW, or nPIOR asserted 

MA(25:0), nPREG, PSKTSEL, nPCE hold after nPWE, 

nPOE, nPIOW, or nPIOR deasserted 

MD(31:0) setup to nPWE, nPOE, nPIOW, or nPIOR 

asserted 

MD(31:0) hold after nPWE, nPOE, nPIOW, or nPIOR 

deasserted 

nPWE, nPOE, nPIOW, or nPIOR command assertion 

NOTE: 

1. These numbers are minimums. They can be much longer based on the programmable Card Interface timing registers. 

TBD 



Table 8-18. Synchronous Memory Interface AC Specifications (2.5 V) 

Symbol Description MIN MAX Notes 1 

SDRAM / SMROM 

tsynCLK 

tsynCMD 

tsynRCD 

tsynCAS 

tsynSDOS 

tsynSDOH 

tsynSDIS 

tsynDIH 

tffCLK 

tffAS 

tffCES 

tffADV 

tffOS 

tffCEH 

SDCLK period 

nSDCAS, nSDRAS, nWE, nSDCS assert time 

nSDRAS to nSDCAS assert time 

nSDCAS to nSDCAS assert time 


SDCKE(1:0), RDnWR output setup time to SDCLK(2:0) rise 


SDCKE(1:0), RDnWR output hold time from SDCLK(2:0) rise 

MD(31:0) read data input setup time from SDCLK(2:0) rise 

MD(31:0) read data input hold time from SDCLK(2:0) rise 

Fast Flash (Synchronous READS only) 

SDCLK period 

MA(25:0) setup to nSDCAS (as nADV) asserted 

nCS setup to nSDCAS (as nADV) asserted 

nSDCAS (as nADV) pulse width 

nSDCAS (as nADV) deassertion to nOE assertion 

nOE deassertion to nCS deassertion 

TBD 

TBD 

NOTES: 

1. These numbers are for a maximum 99.5 MHz MEMCLK and 99.5 MHz output SDCLK. 

2. SDCLK for SDRAM and SMROM can be at the slowest, divide-by-2 of the 99.5 MHz MEMCLK. It can be 99.5 MHz at the 

fastest. 

3. This number represents 1/2 SDCLK period. 

4. SDCLK for Fast Flash can be at the slowest, divide-by-2 of the 99.5 MHz MEMCLK. It can be divide-by-2 of the 132.7 MHz 

MEMCLK at its fastest. 

8.7 Example Form Factor Reference Design Power 

Delivery Example 

8.7.1 Power System 

Features of the example form factor reference design power system (example in Figure 8-5, 

“Example Form Factor Reference Design Power System Design” on page 8-22) are: 

• A standard-size cylindrical single-cell Li+ 3.6 V battery with a 1.8 Ahr capacity 

• Battery temperature monitoring thermistor during charge cycles 

• Battery voltage monitoring 

• Charger supply voltage fault monitoring 

• Low battery interrupt signal to the microprocessor. 



• Provide power gating switches for the CF, LCD, backlight, RS-232, MMC, Radio, and audio 

amplifier subsystems 

• Provide a high-efficiency 5.5 V supply rail for LCD and other devices 

• Provide a high-efficiency 3.3 V supply rail for I/O and general system power 

• Provide a high-efficiency 0.8 – 1.3 V Core/PLL supply for the microprocessor 

• Provide separate, clean power rails for the LCD and Audio subsystems 

• A small, low-cost, low-heat dissipation pulse-charge method for the battery 

8.7.1.1 Power System Configuration 

The example form factor reference design power system design is described in Figure 8-5, 

“Example Form Factor Reference Design Power System Design” on page 8-22. Note that there are 

four main power rails in the system: 

• 3.3 V I/O power 

• 0.8-1.3 V Core power 

• 1.3 V PLL power 

• 5.5 V power 



Figure 8-5. Example Form Factor Reference Design Power System Design 

LDO 

ON/OFF 

Audio AMP 

LDO 

ON/OFF 

Audio_DC3P3V 

MMC_VDD 

LDO 

ON/OFF 

3.3V 

LDO 

ON/OFF 

LCD_DC3P3V 

LDO 

ON/OFF 

3.2V 

LDO 

ON/OFF 

LCD_DC5V 

LDO 

ON/OFF 

LCD_DC4V 

CF_VDD 

LDO 

ON/OFF 

3.3V 

Boost 

Converter 

MAX633 

LCD_DC15V 

LCD_DC14V- 

Boost 

Converter 

LTC1308A 

DC_5P5V 

LCD_DC11P7V- 

LDO 

3.2 V 

LDO 

3.3 V 

DC_3P3V 

DC_CORE 

Buck 

Converter 

LTC1878 

0.8 - 1.3 V 

Wall 

Input 

Current 

Limited 

Battery 

Charger 

LTC1730 

battery 

LDO 

1.3 V 

DC_PLL 

8.7.2 CORE Power 

The example form factor reference design has a variable 0.8 V – 1.3 V core power supply for the 

applications processor. This voltage varies depending on the performance required by the 

application. A Linear Technologies LTC1878 buck converter is chosen for this application. The 

power is drawn directly from the Li+ battery. This device operates at 550 kHz and can supply up to 

1 A at 0.8 V and 800 mA at 1.3 V with up to 95% efficiency. The device is turned on/off by the 

SA_PWR_EN signal directly from the applications processor. 

The required output voltage is statically adjusted by selecting the value of the feed-back resistor. 

Ultimately, output voltage can be changed using software control of the Linear Technologies 

LTC1663 DAC. This DAC is controllable via the standard I2C bus, and can modify the voltage of 

the feedback path of the buck converter, which effects a change in the output voltage. 

8.7.3 PLL Power 

DC_PLL supplies power to the three PLLs within the applications processor. This pin requires a 

0.85 V to 1.3 V nominal supply at an expected 20 mA load. 



8.7.4 I/O 3.3 V Power 

A simple LDO linear regulator supplies the 3.3V rail. The Analog Devices ADP3335 is chosen for 

its very low drop-out – 200 mV at 500 mA and 110 mV at 200 mA. So typically, the input cut-off 

voltage for this device is about 3.3 V + 0.11 V = 3.41 V. The power is drawn directly from the Li+ 

battery. For a 3.6 V battery, this device has a 82% efficiency. There are four zones of operation for 

the Li+ battery: 

• 4.1 – 3.8 V zone 10% of the time; 

• 3.7 – 3.6 V zone at 70% of the time; 

• 3.5 – 3.4 V at 10% of the time; and 

• 3.4 – 3.1 V at 10% of the time. 

The ADP3335 operates in zone 1,2, 3, and cutoffs in zone 4. 

The overall efficiency is: 

0.1(3.3/4.0) + 0.7(3.3/3.6) + 0.1(3.3/3.4) = 0.0825 + 0.642 + 0.097 = 0.82 

To access the energy in zone 4 use the second LDO linear regulator in a parallel configuration with 

the ADP3335 and set it to output 3.2 V. Input to this regulator is 5.5 V from the boost converter. 

When the battery voltage drops below 3.5 V, the ADP3335 drops-out and the second regulator 

takes over. 

8.7.5 Peripheral 5.5 V Power 

The example form factor reference design provides a 5.5 V rail to supply power to LCD, Audio 

amplifier and Radio modules. An LT1308A boost converter is used. This device supplies up to 1 A 

at 5.5 V while operating at 600 kHz with up to 90% efficiency at rated load and 3.6 V input. 

In addition, a low battery voltage detect circuit has an open-drain output. The detect voltage is set 

at 3.45 V by a resistor divider circuit. When the battery drops below 3.45 V the output transitions 

to a logic low. This output signal is used as a processor interrupt. 




JTAG/Debug Port 9 

9.1 Description 

The JTAG/Debug port is essentially several shift registers, with the destination controlled by the 

TMS pin and data I/O with TDI/TDO. nTRST provides initialization of the test logic. JTAG is 

testable via the IEEE 1149.1. Many use JTAG to control the address/data bus for Flash 

programming. JTAG is also a hardware debug port. 


All JTAG pins, except for nTRST and TCK, are directly connected. TCK is not driven internally 

and so you must add an external pull-up or pull-down resistor. Intel recommends adding a 1.5 k 

pull-down resistor to TCK. nTRST must be asserted during power-on. Asserting nRESET or 

nTRST must not cause the other reset signal to assert. Also, use an external pull-up resistor on 

nTRST to prevent spurious resets of the JTAG port when disconnected. The circuit in Figure 9-1 

drives nTRST. It uses a reset IC on nTRST to ensure that nTRST is reset at power-on. nRESET 

must be directly connected to the CPU nRESET. Do not connect pins 17 and 19 – they are special 

purpose functions and not used. 

Figure 9-1. JTAG/Debug Port Wiring Diagram 

3.3 V 

nTRST 

RESET MR 

MAX823 

TDI 

TMS 

1 

3 

5 

7 

2 

4 

6 

8 

nRESET 

TCK 

1.5K 

GND 

TDO 

9 

11 

13 

15 

10 

12 

14 

16 

17 

19 

18 

20 

If you are not utilizing either JTAG or the hardware debug functions, it is highly recommended that 

you design in a JTAG/debug port on your system anyway. This greatly facilitates board debug, 

startup, and software development. During final production you would not have to populate the 

JTAG connector. 


JTAG/Debug Port 

9.3 Layout 

Use the JTAG/Debug the port layout recommendations given in ARM’s application note, Multi- 

ICE System Design Considerations, Application Note 72. The recommended connector is a 2x10- 

way, 2.54 mm pitch pin header, shown in Figure 9-1. 

If board space is critical, use a small form-factor receptacle with a smaller pitch. Then use a cable 

interface that has a wire “dongle” with a 2.54 mm pitch pin header on one end and the smaller pitch 

connector on the other. 

Place the JTAG/Debug connector as close as possible to the applications processor to minimize 

signal degradation. 

If you follow these design recommendations, a JTAG bridge board is not required. Essentially, the 

JTAG bridge board for the example form factor reference design uses a 220 ohm resistor to tie 

nTRST high so that the JTAG logic can be brought out of reset (otherwise it would not come out of 

reset since nTRST is open-drain). 


SA-1110/Applications Processor 

Migration 

A 

The Intel® PXA250 an PXA210 applications processors represent the next generation follow-on to 

Intel® StrongARM* SA-1110 product. This appendix highlights the migration path needed to 

change an SA-1110 design to one that uses the applications processor. 

The majority of application code running on the SA-1110 will directly run on the applications 

processor, but there are substantial differences in hardware implementation and low-level coding, 

especially device configuration, that need to be noted. 

The applications processor has numerous new hardware and software features that substantially 

benefit a handheld product design. The applications processor can be considered a superset of the 

SA-1110, but with so many new features direct socket compatibility is impractical. 

For a detailed analysis of the differences between these products, refer to the full specifications of 

each device: 

• SA-1110 Advanced Developers Manual, Order# 278240 [http://developer.intel.com] 

• Intel® PXA250 and PXA210 Applications Processors Developer’s Manual, Order# 278522 

• ARM* Architecture Reference Manual, Order# ARM DDI 0100D-10 

• Intel 80200 Developers’ manual, Order# 273411-002 [http://developer.intel.com] 

Or later updated versions of any of the above. 

This appendix is separated into sections that focus on three different issues: 

1. SA-1110 hardware migration issues 

— Hardware Compatibility 

—Signal Changes 

— Power Delivery 

— Package 

—Clocks 

—UCB1300 

2. SA-1110 software migration issues 

— Software Compatibility 

— Address space 

— Page Table Changes 

— Configuration registers 

—DMA 

3. Using new features in the applications processor 

PXA250 and PXA210 Applications Processors Design Guide A-1

SA-1110/Applications Processor Migration 

— Intel® XScale microarchitecture 

—Debugging 

- Cache attributes 

- Other Features 

- Conclusion 

A.1 SA-1110 Hardware Migration Issues 

A.1.1 

Hardware Compatibility 

The majority of the features provided in the SA-1110 are also provided in the PXA250 applications 

processor. However, with the additional functionality of the PXA250 applications processor, the 

two devices are not pin compatible and cannot occupy the same socket. 

There has been an effort to ensure Companion Devices that take advantage of SA-1110 memory 

interface access works with the PXA250 applications processor. The memory controls for taking 

over the memory bus such as those exercised by the SA-1111, are included in the PXA250 

applications processor memory bus interface however, there are some issues. 

One difference in particular is the way PXA250 applications processor toggles the A1 and A0 

address lines. The SA-1110 toggled A1 and A0 regardless of the size of the data bus. With 

PXA250, if the data bus is set to 16-bit, then A0 does not toggle and if the data bus is set to 32-bit, 

then neither A1 nor A0 toggles. 

There is a big difference in manufacturing technology between the SA-1110 and the PXA250 

applications processors. The most significant change being from a 0.35 micron CMOS technology 

to a finer lithography of 0.18 microns. Aside from a potential impact to signal edge rates this 

allows for lower applications processor voltage operation. 

A.1.2 

Signal Changes 

There are two pins that control SA-1110 boot-up: 

• ROM select pin that selects a 16 or 32-bit interface 

• Synchronous Mask ROM enable pin that selects a synchronous or asynchronous ROM access 

The PXA250 applications processor has three pins that select eight different boot select options 

(see Table A-1. The subset of these options that are SA-1110 equivalent are not compatible with the 

PXA250 applications processor pin polarities, so these pins must be selected afresh when 

designing with the PXA250 applications processor. 

Table A-1. PXA250 Boot Select Options (Sheet 1 of 2) 

Boot Select Pins 

2 1 0 

Boot Location 



0 1 0 Synchronous 32-bit Flash 

A-2 PXA250 and PXA210 Applications Processors Design Guide


Table A-1. PXA250 Boot Select Options (Sheet 2 of 2) 

Boot Select Pins 

2 1 0 

Boot Location 

0 1 1 Synchronous 16-bit Flash 

1 0 0 

(1) Synchronous 32-bit Mask ROM (64 Mbit) 

(2) Synchronous 16-bit Mask ROM = 32bits (32 Mbit) 

1 0 1 (1) Synchronous 16-bit Mask ROM (64 Mbit) 

1 1 0 (2) Synchronous 16-bit Mask ROM = 32bits (64 Mbit) 

1 1 1 (1) Synchronous 16-bit Mask ROM (32 Mbit) 

The power fault (VDD_FAULT) and battery fault (BATT_FAULT) pins that drive the SA-1110 

sleep mode are negated with respect to the PXA250 applications processor. You must invert these 

signals or change the design to make sure that these signals are negated with respect to the SA- 

1110 design. 

The PXA250 applications processor treats variable latency IO differently than the SA-1110. The 

difference occurs only when a static chip select is configured to support variable latency IO, i.e. the 

bus cycle is to be extended by a value on the RDY pin. In this configuration, the SDRAM refresh 

cycle retains the use of the nWE pin to allow the memory bus to be held for an indeterminate time. 

During any variable latency IO cycle, the PCMCIA pin nPWE is used to write to an external device 

instead of the nWE pin. 

Note: 

Holding the bus for extended periods is not recommended because it interferes with the LCD DMA 

and prevents an LCD panel refresh. 

This change in write enables only causes an issue if an external companion bus master device has a 

single write enable pin and requires variable latency IO to be accessed. As shown in Figure A-1, 

the write enable to the companion master has to be gated to differentiate between a case where the 

PXA250 applications processor uses the WE to write to the companion and a case where the 

companion uses the WE to write into SDRAM memory. Gating the WE pin with the Bus Grant 

signal (as shown) segregates the two different memory bus cycle types. If the companion bus 

master has both a WE input pin and a WE output pin to SDRAM, this logic is unnecessary. 

Figure A-1. Write Enable Control Pins 

SDRAM 

~MBGNT 


nWE 

nPWE 

WE# 

SA-1110 

Companion 

Device 

MBGNT 



A.1.3 

Power Delivery 

Although both products are tolerant to 3.3 V inputs and outputs, there is a difference in the supply 

voltage that drives the transistors of the microprocessor megacell. The PXA250 applications 

processor takes advantage of lower supply voltages to offer substantial power consumption 

savings. A design using SA-1110 has a supply voltage of 1.55 V to 1.75 V. The PXA250 

applications processor is rated to 1.4 V maximum. 

Drive the PXA250 applications processor core voltage pins at a lower voltage than the SA-1110 to 

reduce overall power consumption. The choice of voltage impacts the maximum upper frequency 

of operation so check the PXA250 documentation for the correct voltages as they are application 

dependent. 

Also notice that the PXA250 applications processor supports independent power sources for Core, 

IO, Memory Bus, phase lock loops (PLLs), and a backup battery. It is recommended that these be 

independent power sources. 

A.1.4 

Package 

The SA-1110 and the PXA250 applications processors are similar but not identical. The ball pitch 

of 1 mm is the same and the body outlines are both 17x17 mm but the heights are different. The 

PXA250 applications processor contains 4-layers within the package making it fractionally thicker 

than the SA-1110 2-layer package. 

When migrating to the PXA210 applications processor there a few limits to functionality: 

• The upper 16-bits of the databus are unavailable 

• Only two of the primary GPIO pins are available 

• The upper two SDRAM bank strobes are unavailable 

• UART hardware flow control and external DMA are not accessible 

This smaller package than the SA-1110 accommodates a lower overall power envelope that may 

restrict upper voltage operation and maximum frequency for power consumption reasons. The ball 

pitch is reduced to 0.8 mm and the package is much thinner than the mBGA. 

A.1.5 

Clocks 

The crystal inputs for the PXA250 applications processor are at the same frequency as those for the 

SA-1110: 

• High frequency input of 3.6864 MHz 

• Slow real-time clock source of 32.768 KHz. 

The input frequency requirements are relatively low, such that any crystal that is an AT-cut style 

with a certain amount of shunt capacitance will work for both products. 

The actual PLL design and process technology is different between the two products, such that a 

marginal SA-1110 design may not work with the PXA250 applications processor. Please refer to 

the product specifications of each device for further details. 



You can program GPIO pins to generate various clocks in both the SA-1110 and the PXA250 

applications processors. For example, these are often used in audio codec designs to generate 

clocks. The inter-relationships of some of these clocks have changed from the SA-1110 to the 

PXA250 applications processor. You may need to select different GPIO pins and program different 

configuration registers to provide similar functionality. 

A.1.6 

UCB1300 

The SA-1110 supports a unique serial protocol for communication with the Philip’s UCB product 

family: UCB1100, 1200 and 1300. This serial interface is not available on the PXA250 

applications processor. Instead the PXA250 applications processor supports several industry 

standard Audio codec Interfaces. You may also use I 2 S/I 2 C combinations and an AC’97 interface. 

If an SA-1110 design utilizes this UCB interface then an alternative choice of components is 

necessary for the PXA250 applications processor. 

A.2 SA-1110 to PXA250 Software Migration Issues 

The difficulty of migrating software from the SA-1110 to the PXA250 applications processor 

depends on the amount of hardware and software interaction. SA-1110 applications running under 

an Operating System, which use device driver interfaces, should move seamlessly between the two 

devices. 

There is one exception; any application that explicitly uses the Read Buffer to prefetch external 

memory data into the SA-1110. This buffer does not exist on the PXA250 applications processor 

and register #9 in Coprocessor #15 that was used to access it are not compatible to software. 

As the Read Buffer prefetching activity was deemed to be a hint rather than an instruction, 

applications can simply delete all references to the Read Buffer and still function correctly. They 

may not even suffer a performance penalty, as the PXA250 ’hit-under-miss’ cache feature can turn 

the entire data space into a prefetchable region without any explicit software direction. 

Alternately, as a patch for software that cannot be modified, all applications must be limited to 

User Mode execution, whereupon an Exception can be generated for all Coprocessor activity. 

Such an exception manager needs to filter out the Read Buffer coprocessor calls, or convert them to 

PXA250 PLD instructions that can preload a data cache value. 

There are major software difference within the device initialization/configuration software and 

device drivers, such as low-level code that controls the hardware. 

The PXA250 applications processor has enhanced functionality and extra instructions not found in 

the SA-1110. The PXA250 applications processor software is not backward compatibility to the 

SA-1110. Once code is compiled for the PXA250 applications processor it is unlikely to run on the 

SA-1110. 



A.2.1 

Software Compatibility 

Because the PXA250 applications processor uses Intel® XScale microarchitecture, the PXA250 

applications processor has a different pipeline length relative to the SA-1110. This effects code 

performance when migrating between the two devices varies because of the number of clock cycles 

needed for execution. Any application that relies on specific cycle counts, or has specific timing 

components, will show a difference in performance. 

The PXA250 applications processor features: larger caches, Branch target buffering, and faster 

multiplication, and so many applications run faster than the SA-1110 when running at the same 

clock frequency. 

A.2.2 

Address space 

The physical address mapping of gross memory regions is not compatible between the PXA250 

applications processor and SA-1110. For example, on the PXA250 applications processor, Static 

chip selects 4 and 5 are lower in memory than PCMCIA, on the SA-1110 they are higher in the 

memory space. 

Changes of this kind could be managed by the Operating System remapping virtual memory pages 

to new physical addresses. This assumes that the Operating System has basic support for virtual 

memory, but not if this could be managed by initialization code modifications effecting the same 

change. 

More significantly, memory-mapped registers may have different names, new addresses and 

different functionality. This impacts all device drivers and register-level firmware, that at a 

minimum, requires re-mapping register address and changing the default configuration. 

A.2.3 

Page Table Changes 

There are differences in the virtual memory Page Table Descriptors between the SA-1110 and the 

PXA250 applications processors that impact software execution speed. A new bit has been added 

to differentiate ARM* compliant operation modes from some features Intel includes such as access 

to the Mini-Data-Cache. 

If any software attempts to explicitly control page table modifications, normally the domain of the 

Operating System, then that software may need annotation to allow for the extra opportunities the 

PXA250 applications processor offers. 

Any SA-1110 code that explicitly uses the Mini-Data-Cache is executed correctly, but it's ability to 

utilize a different cache is lost without a page table bit being changed. The impact here is 

performance not functionality. 

A.2.4 

Configuration registers 

There are numerous device configuration changes in the PXA250 applications processor. You must 

now select the configuration options for clock speeds such as Turbo Mode. This requirement is not 

found on the SA-1110. 



You must choose memory clocks, LCD clock rates, audio clocks and interfaces, which GPIOs are 

actually connected to hardware, and many more. There are no easy solutions here, the device 

space of the PXA250 applications processor is very diverse and a number of selections must be 

made in software to select your particular hardware functionality. 

All software that controls registers will need to be updated. If a switch is connected to a GPIO, then 

the software that reads the switch register will differ between the PXA250 applications processor 

and SA-1110. This applies to software that controls Configuration registers in Coprocessor space 

and also to a number of the memory-mapped registers. Many functions such as memory timing 

configuration are done through these registers. For example the registers to access USB have a 

different name, address and function. Any code that directly accesses the USB hardware registers 

will need to be rewritten. 

A.2.5 

DMA 

The SA-1110 contains a 6-channel DMA controller that pipes data between the serial channels and 

memory. The PXA250 applications processor provides a far more substantial 16-channel chained 

DMA controller that can be configured to do much more than the SA-1110, including memory-tomemory 

block moves. 

Clearly there are changes in software required to take advantage of this new asset. However this 

also implies changes necessary to maintain similar functionality to the SA-1110. To configure a 

DMA channel you no longer set it to a specific serial port, instead you map it to the specific source 

or destination address of the serial port FIFO. You must configure other parameters for address 

incrementing and memory width that differ between the PXA250 applications processor and SA- 

1110. 

Any device driver using the SA-1110 DMA controller, or application that takes direct advantage of 

DMA, will need to be modified. The impact of this varies as some Operating Systems and many 

device drivers have ignored the SA-1110 DMA in favor of programmed I/O. 

Some have argued to remove the required interrupt management code as they only move small 

blocks. Operating systems have excluded DMA to guarantee they can manage the real-time 

behavior of different threads. Other software providers saw the serial ports as so slow that DMA 

performance was unnecessarily complex. 

The performance benefit of the PXA250 DMA controller is one of the most significant 

improvements over the SA-1110, particularly in the area of memory-to-memory moves. Changing 

code on the PXA250 applications processor to utilize the new DMA functionality will significantly 

enhance applications. 

A.3 Using New PXA250 Features 

This appendix doesn’t attempt to discuss all the differences between the PXA250 applications 

processor and the SA-1110 or it would become quite substantial. There are numerous significant 

advantages that the PXA250 applications processor has to offer, all of which potentially require 

changes in hardware, firmware or software development tools. This section lists just a few of the 

chief additional benefits of the PXA250 applications processor. However, refer to the product 

specifications for further details. This list is not comprehensive. 



A.3.1 

Intel® XScale Microarchitecture 

The PXA250 applications processor is a system on a chip that includes Intel’s new microprocessor 

megacell. This includes Intel® Superpipelined Technology and a new optimized cache 

architecture that allows program execution to continue despite data cache misses. 

The PXA250 applications processor supports: 

• ARM* Architecture v5 instructions, including ARM’s Thumb extensions 

• DSP Extensions but not ARM’s optional Vector Floating Point instructions 

Appendix A in the Intel 80200 Developers’ manual, Order# 273411-002 [http:// 

developer.intel.com], is the best guide to the new capabilities available in the Intel® XScale 

Megacell's Instruction Set. 

Using a software development toolset that takes specific advantage of Intel® XScale 

microarchitecture, and Intel® Media Processing Technology could give you substantial 

performance benefits. 

The PXA250 applications processor offers increased performance at similar clock rates, and also a 

wider range of operating clock rates at lower voltages. The overall benefit is more work done for 

less battery power. 

A.3.2 

Debugging 

New PXA250 hardware creates new debugging possibilities. You can use the JTAG test port to 

download programs into a dedicated memory area to act as a debug monitor. Applications can be 

inspected and performance data, such as cache hit rates, can be measured via a dialog over JTAG. 

These features offer developers far more visibility inside a PXA250 system improving time to 

market. 

A.3.3 

Cache Attributes 

The PXA250 applications processor has twice the instruction cache and four times the data cache 

of the SA-1110. The Caches can be locked for optimized code or data and for reliability the caches 

are now covered by parity protection. 

To take advantage of cache locking software, data must be selected and specifically loaded and 

locked into cache. 

To take advantage of new features such as Write-Through mode for external IO buffers, page tables 

will need to be revisited in boot software. 

A.3.4 

Other features 

As mentioned before, the PXA250 DMA controller is highly versatile. With 16 channels it can be 

utilized as: 

• Several serial ports in parallel 

• A general-purpose memory move capability 

• A fast interface for external companion devices 



Additional software is required to access these benefits. 

A similar story is true for AC’97, I2C, GPIOs, MMC and others. The benefits are substantial, but 

new hardware and software will be necessary to effectively use the PXA250 applications 

processor. 

A.3.5 

Conclusion 

Although most application software will migrate unchanged between SA-1110 and the PXA250 

applications processors, the underlying microarchitectures are radically different. The PXA250 

applications processor being considerably more ornate and capable than the SA-1110. The majority 

of hardware and low-level software from any SA-1110 design will need to be redesigned. with a 

view to taking full advantage of the new features that the PXA250 applications processor brings to 

the handheld market. 




Example Form Factor Reference Design 

Schematic Diagrams 

B 

B.1 Notes 

The example form factor reference design schematics in this appendix have known issues and 

assumptions that need to be assessed for each board design. This appendix documents the issues 

that have been discovered and provides revision data for the schematics. This appendix also points 

out some of the design specific assumptions that were made in designing this board. 

Page 4: The schematic supports the SA1110 legacy mode for addressing the SDRAM. See 

SDRAM section of the design guidelines to explain normal vs. legacy addressing modes. 

Page 10: U26 allows the CF card to access the I 2 C interface. 

Page 11: The MMC slot has resistor jumpers to select SDCARD and/or MMC card support. If the 

users wants to support both SCARD and MMC, populate the resistor values in the SD column of 

the CARD selection table. If MMC card support only populate the resistors under the MMC 

column in the table. 

Page 11: The JTAG port on this board assumes that it is connected to a specific JTAG bridge board. 

If you follow this design guide, you should not need the bridge board. See the JTAG section of this 

document for more details on this bridge board implementation. 

Page 11: J19 pin 9 requires a 1.5 k pull down. 

Page 13: U33, U34, U35, U40, and surrounding circuits are to support a legacy sharp LCD. Refer 

to that vendor’s design guidelines if you are integrating a different LCD display. 

Page 14: U36, U37, U39, J13, and surrounding circuits including the resistor divider network in the 

upper left hand corner support a legacy Sharp LCD. Refer to that vendor’s design guidelines if you 

are integrating a different LCD display. 

Page 14: J14 is the Toshiba LCD connector. Confirm the pinout before layout. 

B.2 Schematic Diagrams 

The example form factor reference design schematics are on the following pages. 

PXA250 and PXA210 Applications Processors Design Guide B-1

8 

D D 

A A 

PXA250 Processor Reference Design 

Rev 2.07 

1 

Pg.1 

Sheet 1 of 16 

1 

7 

6 

5 

4 

3 

2 

Copyright 2002 Intel Corporation 

Example Form Factor Reference Design for PXA250 

Page Description 

C C 

1 Cover Sheet 

2-3 PXA250 Processor 

4 SDRAM, System Configuration Register 

5 Intel Flash Memory (BGA) 

6 Buffer, CPLD, Board Control Register 

7 Transceivers 

8 Audio Codec, Audio AMP 

9 Headset Jack, Microphone, Stereo Jack, Speaker, Dual Axis Accelerometer, IrDA, USB 

10 Basestation Hdr, RS232 Xcvr, CF Socket, Function Switches 

11 SD socket, Radio Header, JTAG Port 

12 Boost Buck Power , Battery Header, Battery On Jumper 

13 LCD CPLD, LCD Power, Back Light Connector 

14 LCD Connectors, 9 Channel Buffer, Touch Screen Connector 

15 Bus Connectors, 2-140 Pin 

16 Schematic Revision Page 

B B 

Size Rev 

B 

2.07 

8 

7 

6 

5 

4 

3 

Date: 

Tuesday, February 05, 2002 

2

8 

1 

7 

6 

5 

4 

3 

2 


22.1 R256 

{6,15} SA_nCS_5 

C12 

{4,5,7} SA_A20 

{9} SA_UDCP 

10K 

B12 

USB Ch 

R257 22.1 

{9} SA_UDCN 

nCS_0 

N8 

SA_nCS_0 {6,15} 

{4,5,7} SA_A21 

nCS_1_GPIO15 

T8 

SA_nCS_1 

C15 

P9 

{6} 

{9} IR_TXD 

SA_nCS_2 {6} 

R267 

22.1 R258 

IR_TXD_GPIO47 

IrDA Ch 

nCS_2_GPIO78 

{6,15} SA_nPCE_1 

{4,5,7} SA_A22 

{9} IR_RXD 

B15 

IR_RXD_GPIO46 

nCS_3_GPIO79 

T9 

SA_nCS_3 {6,15} 

100K 

R13 

R259 22.1 

nCS_4_GPIO80 

SA_nCS_4 

B14 

{6,15} 

{4,5,7} SA_A23 

{11} SA_BT_RTS BT_RTS_GPIO45 

nCS_5_GPIO33 

T13 

SA_nCS_5 

A15 

{6,15} R268 

22.1 R260 

{11} SA_BT_CTS BT_CTS_GPIO44 

BT Ch 

{6,15} SA_nPCE_2 

D13 

{4,5,7} SA_A24 

{11,15} SA_BT_TXD 

BT_TXD_GPIO43 

{11,15} SA_BT_RXD 

SA_DQM_0 {4,7} 

100K 

B13 

M8 

R261 22.1 

BT_RXD_GPIO42 

DQM_0 

{6,7} SA_A25 

DQM_1 

B1 

SA_DQM_1 

B9 

B2 

{4,7} 

SA_DQM_2 {4,7} 

R269 

22.1 

EXTCLK_GPIO27 

DQM_2 

{6,15} SA_RD_nWR 

E9 

R10 

SFRM_C_GPIO24 

DQM_3 

L7 

SA_DQM_3 {4,7} 

100K 

F9 

{11} RADIO_RI 

SCLK_C_GPIO23 

0 R9 

D9 

TXD_C_GPIO25 

F1 

SA_nSDCS_0 {4,7} 

SSP Ch 

nSDCS_0 

A9 

G6 

R281 

{11} RADIO_DTR 

RXD_C_GPIO26 

nSDCS_1 

{3,12} nCHRGR_PRESENT 

R8 0 

nSDCS_2 

G3 

SA_nSDCS_2 {6} 

100K 

D14 

F2 

{11} RADIO_DSR 

MMCCMD 

0 

MMC 

nSDCS_3 

B16 

R7 

MMCDAT 

H14 

E4 

R272 

{11} RADIO_DCD 

MMCCLK_GPIO6 

SDCKE_0 

SA_SDCKE_0 {15} 

F14 

E3 

R6 

0 

MMCCS0_GPIO8 

SDCKE_1 

SA_SDCKE_1 {4,6} {3,6,15} MBGNT_CF_IRQ 

B6 

{11} MMC_WP 

nMMCCD_GPIO12 

4.99K 

0 

SDCLK_0 

D2 

SA_SDCLK_0 {5,15} 

B10 

F5 

{10} SA_FF_RI FF_RI_GPIO38 

SA_SDCLK_1 {4,7} 

A12 

FF Ch 

SDCLK_1 

D1 

R148 

{10} SA_FF_DCD FF_DCD_GPIO36 

SDCLK_2 

SA_SDCLK_2 {6} 

B11 

{11} RADIO_RXD_C 

{10} SA_FF_DSR FF_DSR_GPIO37 

0 

F10 

E1 

SA_nSDRAS {4,6,7} 

DNI 

{10} SA_FF_DTR FF_DTR_GPIO40 

nSDRAS 

F8 

F3 

{10} SA_FF_RTS FF_RTS_GPIO41 

nSDCAS 

SA_nSDCAS {4,5,6,7} 

A14 

{10} SA_FF_CTS FF_CTS_GPIO35 

R11 

E13 

G5 

{10,15} SA_FF_TXD 

FF_TXD_GPIO39 

nOE 

SA_nOE 

A13 

G4 

{5,7} 

{11} SA_MMCMD 

{10,15} SA_FF_RXD 

FF_RXD_GPIO34 

nWE 

SA_nWE {4,5,6,7,10} 

DC3P3V 

R205 

Pg.2 

{6} SA_A0 

R237 22.1 

U1A 

{6} SA_A1 

R1 

22.1 R238 

{6,15} SA_nPWAIT 

{5,6} SA_A2 

Intel PXA250 Processor 

100K 

R239 22.1 

G1 

N4 

{5,6} SA_A3 

A_0 

D_0 

SA_D0 

H2 

M5 

{4,5,6,7} 

SA_D1 {4,5,6,7} 

R2 

22.1 R240 

A_1 

D_1 

{6,15} SA_nIOIS16 

H1 

{5,7} SA_A4 

A_2 

D_2 

L5 

SA_D2 {4,5,6,7} 

SA_D3 {4,5,6,7} 

100K 

H6 

T6 

R241 22.1 

A_3 

D_3 

J6 

{5,7} SA_A5 

A_4 

D_4 

N6 

SA_D4 

J5 

T7 

{4,5,6,7} 

SA_D5 {4,5,6,7} 

R3 

22.1 R242 

A_5 

D_5 

{15} SA_RDY 

J3 

{5,7} SA_A6 

A_6 

D_6 

M6 

SA_D6 {4,5,6,7} 

SA_D7 {4,5,6,7} 

100K 

J1 Address and Data Buses 

M7 

R243 22.1 

A_7 

D_7 

{5,7} SA_A7 

K1 

M9 

SA_D8 {4,5,6,7} 

R4 

A_8 

D_8 

K2 

T10 

22.1 R244 

A_9 

D_9 

SA_D9 {10,12,15} SA_I2C_SCL 

K5 

R9 

{4,5,6,7} 

{5,7} SA_A8 

SA_D10 {4,5,6,7} 

4.99K 

A_10 

D_10 

K6 

T11 

R245 22.1 

A_11 

D_11 

SA_D11 

L1 

{4,5,6,7} 

{5,7} SA_A9 

SA_D12 {4,5,6,7} 

R5 

A_12 

D_12 

P11 

L3 

N10 

22.1 R246 

A_13 

D_13 

SA_D13 {10,12,15} SA_I2C_SDA 

M1 

{4,5,6,7} 

{4,5,7} SA_A10 

A_14 

D_14 

T12 

SA_D14 

M3 

{4,5,6,7} 

SA_D15 {4,5,6,7} 

4.99K 

R247 22.1 

A_15 

D_15 

M10 

N3 

{4,5,7} SA_A11 

A_16 

D_16 

H3 

SA_D16 

P1 

{4,5,7} 

SA_D17 {4,5,7} 

R137 

22.1 R248 

A_17 

D_17 

H5 

{6} SA_nCS_1 

{4,5,7} SA_A12 

R1 

A_18 

D_18 

J4 

SA_D18 {4,5,7} 

100K 

P2 

R249 22.1 

A_19 

D_19 

K3 

SA_D19 

R3 

{4,5,7} 

{4,5,7} SA_A13 

A_20 

D_20 

L4 

SA_D20 

T4 

{4,5,7} 

SA_D21 {4,5,7} 

R263 

22.1 R250 

A_21 

D_21 

M2 

{6} SA_nCS_2 

R5 

{4,5,7} SA_A14 

A_22 

D_22 

N1 

SA_D22 {4,5,7} 

SA_D23 {4,5,7} 

100K 

P5 

R251 22.1 

A_23 

D_23 

T3 

T5 

{4,5,7} SA_A15 

A_24 

D_24 

P6 

SA_D24 

P4 

R7 

{4,5,7} 

SA_D25 {4,5,7} 

R264 

22.1 R252 

A_25 

D_25 

{6,15} SA_nCS_3 

{4,5,7} SA_A16 

D_26 

P7 

SA_D26 {4,5,7} 

SA_D27 {4,5,7} 

100K 

R253 22.1 

D_27 

P8 

{4,5,7} SA_A17 

D_28 

L8 

SA_D28 {4,5,7} 

SA_D29 {4,5,7} 

R265 

22.1 R254 

D_29 

P10 

{6,15} SA_nCS_4 

{4,5,7} SA_A18 

D_30 

R11 

SA_D30 {4,5,7} 

10K 

D11 

R255 22.1 

{10,12,15} SA_I2C_SCL 

SCL 

SA_D31 

I2C 

D_31 

P12 

A11 

{4,5,7} 

{4,5,7} SA_A19 

{10,12,15} SA_I2C_SDA 

SDA 

R266 

D D 

C C 

B B 

R12 47.5 

P13 

D3 

{11} SA_MMDAT 

{6,15} SA_nPOE 

nPOE_GPIO48 

RD_nWR 

SA_RD_nWR {6,15} 

47.5 R13 

{6,15} SA_nPWE 

T14 

nPWE_GPIO49 

RDY_GPIO18 

C1 

SA_RDY {15} 

{11} SA_MMCCLK 

{6,15} SA_nPIOR 

T15 

nPIOR_GPIO50 

R15 

N15 

47.5 

{6,15} SA_nPIOW 

nPIOW_GPIO51 

DVAL_0_GPIO21 

GPIO_21 {10,11} 

{11} MMC_CS0 

{6,15} SA_nPCE_1 

P14 

nPCE_1_GPIO52 

DVAL_1_GPIO22 

M12 

GPIO_22 {10,11} 

{6,15} SA_nPCE_2 

R16 

nPCE_2_GPIO53 

DREQ_0_GPIO20 

N12 

GPIO_20 

P16 

N14 

{10,11} 

{11,13} nMMC_DETECT 

{15} SA_PSKTSEL 

PSKTSEL_GPIO54 DREQ_1_GPIO19 

GPIO_19 {10,11} 

{6,15} SA_nPREG 

M13 

nPREG_GPIO55 

N16 


nPWAIT_GPIO56 

M16 

D10 

{6,15} SA_nIOIS16 

nI0IS16_GPIO57 

SA_nAC97_RESET {8} 

AC97 

nAC97_RESET 

SYNC_GPIO31 

E11 

SA_SYNC 

F15 

A10 

{8} 

NC1 

SDATA_OUT_GPIO30 

SA_SDATA_OUT {8} 

D16 

NC2 

SDATA_IN0_GPIO29 

E10 

SA_SDATA_IN {8} 

E15 

NC3 

BITCLK_GPIO28 

C9 

SA_BITCLK 

E16 

{8} PXA250 Processor Reference Design 

NC4 

F16 

NC5 

PWM_0_GPIO16 

E12 

SA_PWM_0 {13} 

A A 

8 

7 

6 

5 

4 

CARD Interface 

Memory Control 

Pulse Width 

PXA250_MBGA256 

3 

Size Rev 

B 

2.07 

Date: 


2 

Sheet 2 of 16 

1

8 

1 

Pg.3 

Sheet 3 of 16 

1 

7 

6 

5 

4 

3 

2 


U1B 

Intel PXA250 Processor 

DC3P3V DC3P3V 

DC3P3V 

L_DD_0_GPIO58 

E7 

L_DD_0 

L10 

{13} 

{10,15} 

GPIO_0 

L_DD_1_GPIO59 

D7 

L_DD_1 {13} 

{9,15} 

L12 

USB_WAKE 

GPIO_1 

L_DD_2_GPIO60 

C7 

L_DD_2 

L13 

{13} 

{10} SA_I2C_ENAB 

GPIO_2 

L_DD_3_GPIO61 

B7 

L_DD_3 

K14 

{13} 

{10,15} GFX_IRQ_CF_BVD2 

GPIO_3 

L_DD_4_GPIO62 

E6 

L_DD_4 

D {10} RS232_VALID 

J12 

{13} 

GPIO_4 

L_DD_5_GPIO63 

D6 

L_DD_5 D 

J11 

{13} 

DNI DNI DNI 

{2,12} nCHRGR_PRESENT 

GPIO_5 

L_DD_6_GPIO64 

E5 

L_DD_6 

G15 

{13} 

{8} AC97_IRQ 

GPIO_7 

L_DD_7_GPIO65 

A6 

L_DD_7 

F12 

{13} 

{10,15} SA1111_IRQ_CF_BVD1 

GPIO_9 

L_DD_8_GPIO66 

C5 

L_DD_8 

F7 

{4,13} 

{12,15} nVBATT_LOW_IRQ 

GPIO_10 

L_DD_9_GPIO67 

A5 

L_DD_9 {4,13} 

{13} 

A7 

GPIO_11 

L_DD_10_GPIO68 

D5 

L_DD_10 

{6,15} MBGNT_CF_IRQ 

B5 

{4,13} 

GPIO_13 


A4 

L_DD_11 

B4 

{4,13} 

{13,15} MBREQ_CF_DETECT 

GPIO_14 


A3 

L_DD_12 {4,13} 

{10} 

D12 

GPIO_17 


A2 

L_DD_13 {4,13} {15} BOOT_SEL_0 

{15} BOOT_SEL_1 

BOOT_SEL_2 

{10} 

A16 

GPIO_32 


C3 

L_DD_14 {4,13} 


B3 

L_DD_15 {4,13} 

LCD Port 

L_FCLK_GPIO74 

E8 

L_FCLK {13} 

L_LCLK_GPIO75 

D8 

L_LCLK 

B8 

{13} 

L_PCLK 

GPIO Port 

L_PCLK_GPIO76 

A8 

{13} 

L_BIAS_GPIO77 

L_BIAS {13} 

H12 

LAYOUT: Keep Close in 

DC3P3V 

{6,10,11,13} JTAG_TCK 

TCK 

H15 

{13} CPLD2_TDO 

TDI 

a Matrix and in an 

H16 

JTAG 

Y4 

DNI 

{10,11} SA_TDO 

Accessible location. 

{6,10,11,13} JTAG_TMS 

H13 

TMS 

1 4 

{11} JTAG_nTRST 

H11 

Y1 

Add Silk screen Box. 

R271 

2 3 

2 1 

J13 K11 

{10,11,15} nRESET_IN 

nRESET_OUT 

nRESET_OUT {6,11,13,15} 

C 681 

C 

3.6864Mhz 

3.6864MHZ 

G16 

{15} 

BOOT_SEL_0 

G13 

{15} 

BOOT_SEL_1 

F13 

DC3P3V 

BOOT_SEL_2 

BOOT_SEL_2 

nRESET_IN {10,11,15} 

{12} 

DC_PLL 

DC3P3V 

C15 

0.1UF 

C16 

0.1UF 

DC3P3V 

DC_CORE 

C123 

0.1UF 

R277 

0 

R200 

0 

R21 

100K 

R22 

100K 

Y2 

2 1 

32.768KHZ 

K15 

K16 

L16 

L15 

L11 

{12,13} SA_PWR_EN 

K12 

nBATT_FAULT 

K13 

nVDD_FAULT 

3.6Mhz 

32Khz 

{13} nVDD_FAULT 

{8,10,11,12,13,14} VBATT 

F11 

DC_CORE 

VDD_1 

VSS_1 

C16 

G7 

VDD_2 

VSS_2 

H8 

G9 

H9 

U2 

VDD_3 

VSS_3 

H10 

VDD_4 

VSS_4 

J8 

J7 

VDD_5 

VSS_5 

J9 

MAX6328 

K8 

VDD_6 

VSS_6 

T1 

1 

K10 

GND 

VDD_7 

L6 

VDD_8 

VSSN_1 

C2 

L9 

E2 

VDD_9 

3 

DC3P3V 

VIN 

Capacitors for Core 

DC3P3V 

B B 

2 

RESET 

U3 

DC3P3V 

MAX6328XR27-T-SC 

MAX811TEUS-T 

4 

VCC 

{12} PLL_SENSE 

A1 

D4 

F4 

H4 

K4 

M4 

M14 

N5 

N7 

N9 

N11 

N13 

P3 

T16 

PXTAL 

PEXTAL 

TXTAL 

TEXTAL 

VDDN_1 

VDDN_2 

VDDN_3 

VDDN_4 

VDDN_5 

VDDN_6 

VDDN_7 

VDDN_8 

VDDN_9 

VDDN_10 

VDDN_11 

VDDN_12 

VDDN_13 

VDDN_14 

S1 

VSSQ_3 

J15 

PLL_VCC 

VSSQ_4 

C14 

J16 

PLL_SENSE 

VSSQ_5 

F6 

RESET 

T2 

VCCKP 

VSSQ_6 

G8 

D15 

ADC_VCC 

VSSQ_7 

G10 

M11 

BATT_VCC 

VSSQ_8 

H7 

J10 

A DC3P3V 

VSSQ_9 

C6 

J14 

Capacitors for VDDX 

A 

VDDQ_1 

VSSQ_10 

C10 

VDDQ_2 

VSSQ_11 

K7 

C13 

VDDQ_3 

VSSQ_12 

K9 

E14 

VDDQ_4 

VSSQ_13 

L14 

G14 

VDDQ_5 BALL 12-11-00 


R262 

0 

TESTCLK 

TEST 

VSSN_2 

VSSN_3 

VSSN_4 

VSSN_5 

VSSN_6 

VSSN_7 

VSSN_8 

VSSN_9 

VSSN_10 

VSSN_11 

VSSN_12 

VSSN_13 

VSSN_14 

VSSN_15 

G11 

G12 

G2 

J2 

L2 

N2 

R2 

R4 

R6 

R8 

R10 

R12 

R14 

M15 

P15 

VSSQ_1 

C4 

VSSQ_2 

C8 

C11 

R48 

0 

R51 

0 

C125 

0.1UF 

4 

B 

1 2 

Top 

7A 

C7 

0.1UF 

C8 

0.1UF 

3 

3 

MR 

RESET 

GND 

2 

1 

R26 

1_Ohm 

C6 

0.1UF 

C9 

0.1UF 

R27 

1_Ohm 

C10 

0.1UF 

C11 

0.1UF 

C12 

0.1UF 

C13 

0.1UF 

C14 

0.1UF 

R23 

10K 

R24 

10K 

R25 

10K 

R18 

100K 

R19 

100K 

R20 

100K 

PXA250_MBGA256 

Size Rev 

B 

2.07 

8 

7 

6 

5 

4 

3 

Date: 


2

8 

1 

Sheet 4 of 16 

1 

7 

6 

5 

4 

3 

2 


C17 

0.1UF 

U4 

SDRAM 

SYSTEM CONFIGURATION REGISTER 

23 

{2,5,7} SA_A10 A0 

24 

{2,5,7} SA_A11 A1 

25 4M x 4 x 16 

DC3P3V 

{2,5,7} SA_A12 A2 

26 SDRAM 

{2,5,7} SA_A13 A3 

29 

SDRAM Bank Addressing: 

{2,5,7} SA_A14 A4 

30 

{2,5,7} SA_A15 A5 

31 

D {2,5,7} SA_A16 A6 

SDRAM Address Bus wired for 

D 

32 

{2,5,7} SA_A17 A7 

33 

SA1110 legacy compatibility mode 

DNI 

{2,5,7} SA_A18 A8 

34 

{2,5,7} SA_A19 A9 

for SDRAM Bank Addressing. 

22 

{2,5,7} SA_A20 A10 

SD_SZ_0 

{2,5,7} SA_A21 

35 

40 

R29 

A11 

NC 

{3,13} L_DD_8 

{2,5,7} SA_A24 

36 

A12 

SA_D0 {2,5,6,7} 

100K 

2 

DC3P3V 

D0 

D1 

4 

SA_D1 

{2,7} 

19 

5 

{2,5,6,7} 

SA_nSDCS_0 nCS 

D2 

SA_D2 

{2,5,6,7,10} SA_nWE 

16 

{2,5,6,7} 

D3 

7 

SA_D3 

17 

{2,5,6,7} 

{2,5,6,7} SA_nSDCAS 

nCAS 

D4 

8 

SA_D4 

18 

{2,5,6,7} 

DNI 

{2,6,7} SA_nSDRAS nRAS 

D5 

10 

SA_D5 {2,5,6,7} 

D6 

11 

SA_D6 

13 

{2,5,6,7} 

SD_SZ_1 

SA_D7 {2,5,6,7} R32 

D7 

{3,13} L_DD_9 

{2,7} SA_SDCLK_1 

38 

42 

D8 

SA_D8 {2,5,6,7} 

{2,6} SA_SDCKE_1 

SA_D9 {2,5,6,7} 

DC3P3V 

100K 

37 

D9 

44 

20 

{2,5,7} SA_A23 BS_0 

D10 

45 

SA_D10 

21 

{2,5,6,7} 

{2,5,7} SA_A22 BS_1 

D11 

47 

SA_D11 

{2,7} SA_DQM_0 

15 

{2,5,6,7} 

DC3P3V 

LDQM D12 

48 

SA_D12 {2,5,6,7} 

{2,7} SA_DQM_1 

39 

UDMQ D13 

50 

SA_D13 {2,5,6,7} 

D14 

51 

SA_D14 {2,5,6,7} 

DNI 

D15 

53 

SA_D15 

1 

{2,5,6,7} 

VDD_1 

FLASH_SZ_0 

C 14 

28 

R35 

VDD_2 VSS_1 

{3,13} L_DD_10 

C 

27 

VDD_3 VSS_2 

41 

100K 

DC3P3V 

VSS_3 

54 

3 

VDD_Q1 VSSQ_1 

6 

9 

VDD_Q2 VSSQ_2 

12 

43 

VDD_Q3 VSSQ_3 

46 

49 

VDD_Q4 VSSQ_4 

52 

DNI 

R38 

FLASH_SZ_1 

{3,13} L_DD_11 

100K 

DC3P3V 

U5 

{2,5,7} SA_A10 

23 

A0 

24 

{2,5,7} SA_A11 A1 

25 4M x 4 x 16 

DNI 

{2,5,7} SA_A12 A2 

26 SDRAM 

{2,5,7} SA_A13 A3 

29 

R41 

FLASH_TYPE 

{2,5,7} SA_A14 A4 

{3,13} L_DD_12 

{2,5,7} SA_A15 

30 

A5 

100K 

31 

DC3P3V 

{2,5,7} SA_A16 A6 

32 

{2,5,7} SA_A17 A7 

B 33 

B 

{2,5,7} SA_A18 A8 

34 

{2,5,7} SA_A19 A9 

22 

{2,5,7} SA_A20 A10 

35 

40 

DNI 

{2,5,7} SA_A21 A11 

NC 

36 

{2,5,7} SA_A24 A12 

2 

SA_D16 {2,5,7} 

R44 

D0 

{3,13} L_DD_13 

LCD_TYPE 

4 

{13} 

D1 

SA_D17 {2,5,7} 

{2,7} SA_nSDCS_0 

SA_D18 {2,5,7} 

DC3P3V 

100K 

19 

5 

nCS 

D2 

16 

{2,5,6,7,10} SA_nWE 

D3 

7 

SA_D19 {2,5,7} 

{2,5,6,7} 

17 

SA_nSDCAS nCAS 

D4 

8 

SA_D20 

18 

{2,5,7} 

{2,6,7} SA_nSDRAS nRAS 

D5 

10 

SA_D21 {2,5,7} 

D6 

11 

SA_D22 {2,5,7} 

D7 

13 

SA_D23 {2,5,7} 

{2,7} SA_SDCLK_1 

38 

42 

CLK 

D8 

SA_D24 

37 

{2,5,7} 

{2,6} SA_SDCKE_1 CKE 

D9 

44 

SA_D25 

20 

45 

{2,5,7} 

{2,5,7} SA_A23 

SA_D26 {2,5,7} 

R47 

BS_0 

D10 

{3,13} L_DD_14 

nGFX_PRESENT {13,15} 

21 

47 

{2,5,7} SA_A22 BS_1 

D11 

SA_D27 {2,5,7} 

{2,7} SA_DQM_2 

SA_D28 {2,5,7} 

100K 

15 

48 

DC3P3V 

DC3P3V 

LDQM D12 

39 

50 

{2,7} SA_DQM_3 UDMQ D13 

SA_D29 

51 

{2,5,7} 

D14 

SA_D30 

53 

{2,5,7} 

D15 

SA_D31 

1 

{2,5,7} 

VDD_1 

14 

VDD_2 VSS_1 

28 

27 

41 

A VDD_3 VSS_2 

54 

R50 

A 

VSS_3 

{3,13} L_DD_15 

nNEP_PRESENT {13,15} 

3 

VDD_Q1 VSSQ_1 

6 

100K 

9 

VDD_Q2 VSSQ_2 

12 

43 

VDD_Q3 VSSQ_3 

46 

49 

VDD_Q4 VSSQ_4 

52 


C19 

0.1UF 

C20 

0.1UF 

R49 

10K 

R46 

10K 

R45 

R42 

0 

R40 

10K 

R43 R39 R37 

R33 

0 10K 

0 10K 

0 

10K 

C18 

0.1UF 

R36 

0 

R34 

10K 

R31 

R30 

0 

R28 

10K 

Pg. 4 

Size Rev 

B 

2.07 

8 

7 

6 

5 

4 

3 

Date: 


2

8 

1 

Sheet 5 of 16 

1 

7 

6 

5 

4 

3 

2 


U6 

Flash Memory 

Intel StrataFlash 

16M x 16 

G2 

F2 

A0 

DQ0 

SA_D0 

A1 

E2 

{2,4,6,7} 

{2,6} SA_A2 A1 

DQ1 

SA_D1 

B1 

G3 

{2,4,6,7} 

{2,6} SA_A3 A2 

DQ2 

SA_D2 

C1 

E4 

{2,4,6,7} 

{2,7} SA_A4 A3 

DQ3 

SA_D3 

D1 

E5 

{2,4,6,7} 

{2,7} SA_A5 A4 

DQ4 

SA_D4 

D2 

G5 

{2,4,6,7} 

{2,7} SA_A6 A5 

DQ5 

SA_D5 

A2 

{2,4,6,7} 

D {2,7} SA_A7 A6 

DQ6 

G6 

SA_D6 Resistor StrataFlash Synchronous 

D 

C2 

{2,4,6,7} 

{2,7} SA_A8 A7 

DQ7 

H7 

SA_D7 

A3 

{2,4,6,7} 

StrataFlash 

{2,7} SA_A9 A8 

DQ8 

E1 

SA_D8 

B3 

{2,4,6,7} 

{2,4,7} SA_A10 A9 

DQ9 

E3 

SA_D9 

C3 

{2,4,6,7} 

{2,4,7} SA_A11 A10 

DQ10 

F3 

SA_D10 {2,4,6,7} 

R52 DNI IN 

{2,4,7} SA_A12 

D3 

A11 

DQ11 

F4 

SA_D11 

C4 

{2,4,6,7} 

{2,4,7} SA_A13 A12 

DQ12 

F5 

SA_D12 {2,4,6,7} 

R53 IN DNI 

A5 

{2,4,7} SA_A14 A13 

DQ13 

H5 

SA_D13 

B5 

{2,4,6,7} 

{2,4,7} SA_A15 A14 

DQ14 

G7 

SA_D14 {2,4,6,7} 

R54 DNI IN 

C5 

E7 

{2,4,7} SA_A16 

SA_D15 

DC3P3V 

A15 

DQ15 

{2,4,6,7} 

{2,4,7} SA_A17 

D7 

A16 

R56 DNI IN 

D8 

DNI 

{2,4,7} SA_A18 A17 

E8 

STS 

A7 

DC3P3V 

{2,4,7} SA_A19 A18 

R212 

R57 DNI IN 

B7 

{2,4,7} SA_A20 A19 

B6 

DU1 / NC 

C7 

C6 

{2,4,7} SA_A21 A20 DU2 / nWP 

0 R52 

R212 DNI IN 

{2,4,7} SA_A22 

C8 

D5 

A21 DU3 / VDDQ 

A8 

D6 

{2,4,7} SA_A23 A22 DU4 / VDDQ 

0 

G1 

{2,4,7} SA_A24 A23 

H8 

A24 

DC3P3V 

H2 

DNI 

DU8 / VSSQ 

D4 

{13} FLASH_nRP 

nRP 

F1 

R54 

nBYTE 

E6 

G4 

{2,15} SA_SDCLK_0 

DU5 / CLK V_DDQ 

R55 

C 0 

F6 

DU6 / ADV 

A4 

V_PEN 

C 

F7 

DU7 / WAIT 

0 

A6 

R56 

VDD_1 

F8 

H3 


{2,7} SA_nOE 

nOE VDD_2 

0 

G8 

{2,4,6,7,10} SA_nWE 

nWE 

B2 

VSS_1 

{6} nFLASH_BOOT_CS 

B4 

H4 

nCE_0 VSS_2 

B8 

H6 

CS_AWS 

nCE_1 VSS_3 

H1 

nCE_2 BGA 

Pg. 5 

DNI 

R58 

10K 

C2 

0.1UF 

U7 

Intel StrataFlash 

16M x 16 

G2 

F2 

A0 

DQ0 

SA_D16 

A1 

E2 

{2,4,7} 

{2,6} SA_A2 

A1 

DQ1 

SA_D17 

B1 

G3 

{2,4,7} 

{2,6} SA_A3 

A2 

DQ2 

SA_D18 

C1 

E4 

{2,4,7} 

{2,7} SA_A4 

A3 

DQ3 

SA_D19 

{2,7} SA_A5 

D1 

E5 

{2,4,7} 

A4 

DQ4 

SA_D20 

D2 

G5 

{2,4,7} 

{2,7} SA_A6 

A5 

DQ5 

SA_D21 

A2 

{2,4,7} 

{2,7} SA_A7 

A6 

DQ6 

G6 

SA_D22 {2,4,7} 

B C2 

B 

{2,7} SA_A8 

A7 

DQ7 

H7 

SA_D23 

A3 

{2,4,7} 

{2,7} SA_A9 

A8 

DQ8 

E1 

SA_D24 

B3 

{2,4,7} 

{2,4,7} SA_A10 

A9 

DQ9 

E3 

SA_D25 

C3 

{2,4,7} 

{2,4,7} SA_A11 

A10 

DQ10 

F3 

SA_D26 

D3 

{2,4,7} 

{2,4,7} SA_A12 

A11 

DQ11 

F4 

SA_D27 

C4 

F5 

{2,4,7} 

{2,4,7} SA_A13 

A12 

DQ12 

SA_D28 

A5 

H5 

{2,4,7} 

{2,4,7} SA_A14 

A13 

DQ13 

SA_D29 

B5 

G7 

{2,4,7} 

{2,4,7} SA_A15 

A14 

DQ14 

SA_D30 

C5 

E7 

{2,4,7} 

{2,4,7} SA_A16 

A15 

DQ15 

SA_D31 

D7 

{2,4,7} 

{2,4,7} SA_A17 

A16 

D8 

E8 

{2,4,7} SA_A18 

A17 

STS 

A7 

{2,4,7} SA_A19 

A18 

B7 

B6 

{2,4,7} SA_A20 

A19 DU1 / NC 

C7 

C6 

{2,4,7} SA_A21 

A20 DU2 / nWP 

C8 

D5 

{2,4,7} SA_A22 


A8 

D6 

{2,4,7} SA_A23 


G1 

{2,4,7} SA_A24 

A23 

H8 

A24 

H2 

DU8 / VSSQ 

D4 

nRP 

F1 

DC3P3V 

nBYTE 

E6 

DU5 / CLK 

G4 

V_DDQ 

F6 

A4 

A DU6 / ADV V_PEN 

F7 

A 

DU7 / WAIT 

A6 

VDD_1 

VDD_2 

H3 

F8 

G8 

nOE 

nWE 

B4 

nCE_0 

B8 

nCE_1 

H1 

nCE_2 

VSS_1 

VSS_2 

VSS_3 

BGA 

B2 

H4 

H6 

C23 

0.1UF 

C24 

0.1UF 

R57 

0 

C21 

0.1UF 

C22 

0.1UF 

C1 

0.1UF 

R53 

0 


Size Rev 

B 

2.07 

8 

7 

6 

5 

4 

3 

Date: 


2

8 

1 

Sheet 6 of 16 

1 

7 

6 

5 

4 

3 

2 


U8 

Pg. 6 

CF_PWR_ON 

Buffer 

{13} 

16_Bit Buffer/Line 

R59 

Driver 

100K 

74LVCH162244A 

47 

2 

{2,15} SA_nPIOW 

CF_nPIOW {10} 

R60 

1A1 

1Y1 

46 

{2,15} SA_nPOE 1A2 

1Y2 

3 

CF_nPOE {10} 

D CF_nPWE {10} 100K 

44 

{2,15} SA_nPWE 1A3 

1Y3 

5 

Board Control 

D 

43 

{2,15} SA_nPIOR 1A4 

1Y4 

6 

CF_nPIOR {10} 

CF_GFX_RESET 

Register 

{10,15} 

IRDA_FSEL {9} 

{2} SA_nSDCS_2 

41 

2A1 

2Y1 

8 

VX_nSDCS_2 {15} 

IRDA_MD0 {9} 

{2,15} SA_nPCE_2 

40 

CF_nPCE_2 {10} 

IRDA_MD1 {9} DC3P3V 

2A2 

2Y2 

9 

{2,4} SA_SDCKE_1 

38 

2A3 

2Y3 

11 

VX_SDCKE_1 {15} CF_nBUS_ON 

37 

{2} SA_SDCLK_2 2A4 

2Y4 

12 

VX_SDCLK_2 {15} 

U9 

{10} CF_nPWAIT 

36 

SA_nPWAIT {2,15} 

R61 

3A1 

3Y1 

13 

{10} CF_nIOIS16 

35 

3A2 

3Y2 

14 

SA_nIOIS16 {2,15} 

100K 


33 

3A3 

3Y3 

16 

CF_nPREG {10} 74LVCH16374A 

{2,15} SA_nPCE_1 

32 

17 

CF_nPCE_1 {10} 

R62 

3A4 

3Y4 

16-Bit Edge Triggered 

{2,5} SA_A3 

VX_A3 {10,15} 

100K 

30 

4A1 

4Y1 

19 

D-Type Flip Flop 

29 

{2,5} SA_A2 4A2 

4Y2 

20 

VX_A2 {10,15} 47 

{2,4,5,7} SA_D0 1D1 

2 

1Q1 

AUDIO_PWR_ON 

{2} SA_A1 

27 

{8} 

4A3 

4Y3 

22 

VX_A1 {10,15} {2,4,5,7} SA_D1 

46 

1D2 

3 

1Q2 

26 

{2} SA_A0 4A4 

4Y4 

23 

VX_A0 {10,15} 44 

{2,4,5,7} SA_D2 1D3 

5 

1Q3 

LIGHT_PWR_ON 

43 

{13} 

{2,4,5,7} SA_D3 1D4 

1Q4 

6 

{7} nVX_CF_OE 

1 

1nOE VSS_1 

4 

41 

{2,4,5,7} SA_D4 1D5 

1Q5 

8 

48 

10 

40 

9 

R63 

2nOE VSS_2 

{2,4,5,7} SA_D5 1D6 

1Q6 

25 

DC3P3V CF_nBUS_ON 

3nOE VSS_3 

15 

38 

{2,4,5,7} SA_D6 1D7 

1Q7 

11 

100K 

24 

4nOE VSS_4 

21 

37 

{2,4,5,7} SA_D7 1D8 

1Q8 

12 

VSS_5 

28 

7 

VDD_1 VSS_6 

34 

36 

13 

{2,4,5,7} SA_D8 2D1 

2Q1 

LCD_PWR_ON {13,14} 

C 18 

VDD_2 VSS_7 

39 

35 

14 

{2,4,5,7} SA_D9 2D2 

2Q2 

C 

31 

VDD_3 VSS_8 

45 

33 

16 

{2,4,5,7} SA_D10 2D3 

2Q3 

42 

32 

17 

R64 

VDD_4 

{2,4,5,7} SA_D11 2D4 

2Q4 

{2,4,5,7} SA_D12 

30 

2D5 

2Q5 

19 

100K 

{2,4,5,7} SA_D13 

29 

2D6 

2Q6 

20 

{2,4,5,7} SA_D14 

27 

2Q7 

22 

RS232_ON 

74LVCH162244APF 

2D7 

{10} 

{2,4,5,7} SA_D15 

26 

2D8 

2Q8 

23 

nBCR_OE 

1 

R65 

nBCR_WR 

1nOE 

48 

1CLK 

100K 

4 

DC3P3V 

VSS_1 

24 

10 

2nOE VSS_2 

25 

15 

2CLK VSS_3 

RADIO_PWR_ON 

21 

{11} 

VSS_4 

7 

VDD_1 VSS_5 

28 

18 

VDD_2 VSS_6 

34 

R66 

31 

VDD_3 VSS_7 

39 

100K 

42 

VDD_4 VSS_8 45 

RADIO_WAKE {11} 

U10 

74LVCH16374A 

DC3P3V 

CPLD 

nRED_LED 

B XCR3032XL-10VQ44C 

B 

Xilinx CPLD 

{2} SA_SDCLK_2 

42 

35 

CF_nBUS_ON 

D1 

A0_CLK 

B0 

R67 

{15} nNEP_FLASH_CS 

43 

A1 

B1 

34 

nXCV_ADD_OE {7,13} 

2 1 

{7} 

44 

XCV_DATA_DIR A2 

B2 

33 

SA_nCS_5 {2,15} 

{10,11} CPLD1_TDI 

CPLD1_TDO {11,13} 

1.5K 

1 

RED 

DC3P3V 

A3_TDI 

B3_TDO 

32 

2 

nGREEN_LED 

{3,15} MBGNT_CF_IRQ 

nBCR_OE 

A4 

B4 

31 

SA_nCS_4 

3 

{2,15} 

nBCR_WR 

A5 

B5 

30 

SA_nCS_3 

5 

{2,15} 

SA_nCS_2 {2} 

D2 

A6 

B6 

28 

{7} nVX_CF_OE 

SA_nCS_1 {2} 

R68 

6 

A7 

B7 

27 

2 1 

7 

{3,10,11,13} JTAG_TMS 

A8_TMS 

B8_TCK 

26 

JTAG_TCK {3,10,11,13} 

GRN 

{10,15} nNEP_REG_CS 

SA_nCS_0 {2,15} 1.5K 

8 

A9 

B9 

25 

10 

{2,4,5,7,10} SA_nWE 

A10 

B10 

23 

SA_A25 {2,7} 

{7} nXCV_DATA_OE 

11 

A11 

B11 

22 

VX_nOE {7,15} 

SPKR_OFF 

12 

{8} DC3P3V 

{7} XCV_ADD_DIR A12 

B12 

21 

13 

{10,15} CF_IRQ_LVL2OE 

A13 

B13 

20 

SA_nPCE_2 

14 

19 

{2,15} 

{3,11,13,15} nRESET_OUT 

SA_nPCE_1 {2,15} DC3P3V 

A14 

B14 

R69 

{5} nFLASH_BOOT_CS 

15 

A15 

B15 

18 

SA_RD_nWR {2,15} 

100K 

VDD_1 

9 

VDD_2 

17 

VDD_3 

29 

{15} SWAP_FLASH 

37 

IN0 

41 

VDD_4 

R70 

39 

A {2,4,7} SA_nSDRAS IN1 

MMC_PWR_ON {13} 

38 

4 

A 

{2} SA_nSDCS_2 IN2 

VSS_1 

0 

40 

16 


IN3 

VSS_2 

VSS_3 

24 

VSS_4 

36 

C29 

0.1UF 

C30 

0.1UF 

C31 

0.1UF 

C32 

0.1UF 

C27 

0.1UF 

C28 

0.1UF 

C25 

0.1UF 

C26 

0.1UF 


XCR3032XL 

Size Rev 

B 

2.07 

8 

7 

6 

5 

4 

3 

Date: 


2

8 

1 

Pg. 7 

Sheet 7 of 16 

1 

7 

6 

5 

4 

3 

2 


DC3P3V 

Transceivers 

NOTE: 

DIR H = A -> B 

DIR L = A

8 

1 

Sheet 8 of 16 

1 

7 

6 

5 

4 

3 

2 


XTAL_IN 

Audio CODEC 

XTAL_OUT 

U15 

24.576MHZ 

+ 

UCB1400 

XTAL_IN 

2 

Modem / Audio 

XTL_IN 

ADCSYNC 

12 

R72 

DNI 

0 

XTAL_OUT 3 

34 

XTL_OUT VREFDRV 

D D 

VREF 

C46 

L_OUT_A {9} 

100UF 

C50 

R_OUT 

{9} 

100UF 

R89 

6 

AMP5V 

1 

2 

R92 

AUDIO3P3V {9} 

1 

DNI 

AUDIO3P3V {9} 

+ 

27 

{13,15} SYSCLK 

8 

29 

DNI 

{2} SA_SDATA_IN 

SDATA_IN 

IRQOUT 

AC97_IRQ {3} 

R73 

R74 

6 

37 

{2} SA_BITCLK 

BIT_CLK 

GPIO_0 

AC97_GPIO_0 {11} 

Audio Amp 

47.5 

R75 0 

5 

39 

{2} SA_SDATA_OUT 

SDATA_OUT GPIO_1 

AC97_GPIO_1 {11} 

R76 

0 R77 

{2} SA_SYNC 

10 

40 

SYNC 

GPIO_2 

AC97_GPIO_2 {11} 

20K 

R78 0 

R79 

11 

41 

{2} SA_nAC97_RESET RESET 

GPIO_3 

AC97_GPIO_3 {11} 

0 R80 

LINE_OUT_L {11} 

43 

20K 

C141 

GPIO_4 

AC97_GPIO_4 {11} 

{9} MICIN 

21 

MICP 

R82 

0 

R14 2 1 

44 

U16 

{10} CF_AUD 

R83 

GPIO_5 

LINE_OUT_R {11} 

10K 

22 

4.7UF 

{9,11} MICGND MICGND 

100K 

45 

R84 

{11} RADIO_SPKRP 

0 

GPIO_6 

LM4881 

J1 

C45 

100K 

Dual Audio Pwr 

2 1 

23 

46 

R86 

R81 

{9} 

LINE_IN_L 

GPIO_7 

Amp w/shutdwn 

C131 

100K 

2 1 

24 

47 

R87 

0.1UF 

20K 

8 7 

LINE_IN_R 

GPIO_8 

C47 

IN_A OUT_A 

4.7UF 

J2 

48 

R124 100K 

R85 

4 

GPIO_9 

IN_B OUT_B 

5 

C C 

R88 

100K 

20K 

20 

0.1UF 

1 

{14} TSPY 

TSPY 

BYPASS VDD 

R90 0 

18 

35 

{14} TSMX 

LINE_OUT_L 

3 

TSMX 

{6} SPKR_OFF SHDN GND 

R91 0 

19 

36 

{14} TSMY 

TSMY LINE_OUT_R 

DC_CORE 

R93 0 

+ 

17 

LM4881MM 

{14} TSPX 

TSPX 

0 

R94 

AD_3 

13 

VBATT 

{3,10,11,12,13,14} 

0 

{3,10,11,12,13,14} 

14 

AD_2 

R96 

0 

15 

AD_1 

XFILT {9} 

DC5P5V 

U17 

{9} AUDIO3P3V 

16 

AD_0 

YFILT 

1 

{9} 

MIC5207-3.3BM5 

DVDD1 

9 

4 

3.3V LDO REG 

DVDD2 

DVSS1 

DVSS2 

7 

1 180ma 

5 

VIN 

VOUT 

25 

AVDD1 

32 26 

2 

AVDD2 GND 

38 

AVDD3 

AVSS2 

33 

AVSS3 

42 

3 4 

EN BYP 

B B 

LE33 

R99 28 

VADCP 

10 

C58 

0.1UF 

C55 

0.01UF 

C42 

0.1UF 

Pg. 8 

R101 

1 

R104 

2 

C71 

+ 

4.7UF 

C72 

1 

2 

C68 

+ 

4.7UF 

C67 

1 

C57 

0.1UF 

+ 

+ 

+ 

MIC5207-4.0BM5 

4.0V LDO REG 

VIN 180ma VOUT 

GND 

{6} AUDIO_PWR_ON 

3 4 

EN BYP 

LE40 

A A 

1 

1 

2 

U18 

5 

C73 

270PF 

C62 

0.1UF 

C59 

0.01UF 

R100 

1 

C66 

0.1UF 

C53 

0.01UF 

C56 

0.01UF 

30 

TEST 

VADCN 

31 

+ 

AMP5V 

C75 

+ 

4.7UF 

1 

2 

C74 

0.1UF 

0.1UF 

R102 

0 

R103 

0 

2 

C69 

4.7UF 

C70 

0.1UF 

1 

0.1UF 

R282 

0 

C63 

270PF 

2 

C64 

0.01UF 

C61 

4.7UF 

1 

C54 

0.01UF 

C52 

0.1UF 

C51 

1UF 

1 2 

2 

R71 

+ 

47.5 

33PF 

C43 

Y3 

2 

1 

22pF 

C44 

1 

10UF 

C41 


Size Rev 

B 

2.07 

8 

7 

6 

5 

4 

3 

Date: 


2

8 


1 

2 

3 

4 

5 

1 

1 

J7 

12-54819-78 

USB_WAKE {3,15} 

Sheet 9 of 16 

1 

7 

6 

5 

4 

3 

2 


R105 

{8} AUDIO3P3V 

10 

MIC_PWR 

Headset Jack 

Stereo Headphone Jack 

IrDA Transceiver 

1 0.1UF 

VCC 

J4 

AGND 

2 

1 3 

D R_OUT {8} 3 

FIR_SEL 

IRDA_FSEL {6} 

D 

MD_0 

4 

IRDA_MD0 

11 

{6} 

GND MD_1 

5 

IRDA_MD1 

Microphone 

{6} 

L_OUT_B 

NC 

6 

2 

GND 

7 

RXD 

8 

IR_RXD 

1 

{2} 

GND 

TXD 

9 

IR_TXD 

Speaker 

{2} DC3P3V 

LEDA 

10 

4 

SHA 

5 L_OUT_B 

STEREO 

HDSL-3600 # 007 

SHB 

R107 

J5 

JACK 

2 

TIP 

10 

3 

RING 

L_OUT_A {8} 3.5mm 

4 

R108 

MICGND {8,11} HEADSET 

J6 

10 

JACK 

R109 

2.5mm 

10 

MICIN {8} 

C79 

R111 

1 2 

USB_5V 

10 

C R112 

C 

4.7UF 

{2} SA_UDCN 

R149 

0 

Mini USB Jack 

RADIO_MICP {11} 

0 

DC3P3V 

+ 

J3 

2 

1 

U19 

DC3P3V 

C76 

Pg. 9 

DNI 

{2} 

R115 

SA_UDCP 

0 

{8} 

AUDIO3P3V 

Dual Axis Acelerometer 

DNI 

B B 

U20 

DC3P3V DC3P3V 

R123 

100K 

XFILT {8} 

USB_5V 

3 

U21 

MAX6348 

RESET 

VIN 

2 

R120 

YFILT {8} 

100K 

A + + 

MAX6348XR40-T 

A 

1uF 

C3 

1uF 

C4 

R117 

1 2 

237K 

C81 

0.01UF 

C82 

0.01UF 

C80 

0.1UF 

R113 

475K 

C78 

0.1UF 

ADXL202E 

Dual Axis 

Accelerometer 

8 

VDD XCAP 7 

1 

ST 

YCAP 

6 

2 

T2 XOUT 5 

3 

COM 

YOUT 

LCC8 

4 

R121 

1K 

C84 

0.1UF 

R118 

10K 

R119 

100K 

R116 

475K 

R110 

0 

2 

1 

C77 

0.1UF 

R106 

1.5K 

R114 

1.5K 

GND 

1 

Size Rev 

B 

2.07 

8 

7 

6 

5 

4 

3 

Date: 


2

8 

1 

Sheet 10 of 16 

1 

7 

6 

5 

4 

3 

2 


J8 

DC5P5V 

Momentary Switches 

CF_TYPE_II 

MIC5219BM5 

Compact Flash Type II Socket 

50 GND2 

ADJ LDO REG 

25 nCD2 

1 

DC3P3V 

S2 

{13} CF_nCD2 

D10 


5 

49 

{7,15} VX_D10 

24 nIOIS16 

2 

1 S 2 


GPIO_0 

D09 

GND 

48 

4 3 

{3,15} 

{7,15} VX_D9 

23 D02 

3 4 

D {7,15} VX_D2 

D 

D08 

{13} CF_PWR EN 

47 

ADJ 

{7,15} VX_D8 

22 D01 

LGAA 

R129 {7,15} VX_D1 

46 BVD1 

DC3P3V 

S3 

{3,15} SA1111_IRQ_CF_BVD1 

21 D00 

U24 

R130 

10K {7,15} VX_D0 


45 BVD2 

1 S 2 

GPIO_32 

20 A00 

MIC5219-3.3BM5 

{3} 

10K 

4 3 

{6,15} VX_A0 

44 nREG 

3.3V LDO REG 

{6} CF_nPREG 

19 A01 

1 

CF_VDD 

{6,15} VX_A1 

{3,8,11,12,13,14} VBATT 

500ma 

5 

nINPACK 

VIN VOUT 

43 

CF_I2C_SDA 

A02 

DC3P3V 

S4 

{6,15} VX_A2 

18 

2 

nWAIT 

GND 

42 

+ 

{6} CF_nPWAIT 

17 A03 

3 4 

{6,15} VX_A3 

GPIO_17 

RESET 

EN 

41 

BYP 

1 S 2 

R132 

4 3 

{3} 

{6,15} CF_GFX_RESET 

16 A04 

LG33 

1K {7,15} VX_A4 

CF_I2C_SCL 

40 nVS2 

15 A05 

{7,15} VX_A5 

39 nCSE 

DC3P3V 

S5 

{6,15} nNEP_REG_CS 

14 A06 

{7,15} VX_A6 

VCC2 

R15 

38 

1 S 2 

CF_VDD 

GPIO_22 

13 VCC1 

J9 

4 3 0 

Base Station Connector 

{2,11} 

37 IREQ 


12 A07 

{7,15} VX_A7 

36 nWE 

{6} CF_nPWE 

C 11 A08 

DC3P3V 

{7,15} VX_A8 

C 

35 nIOWR 

{6} CF_nPIOW 

10 A09 

DC3P3V 

{7,15} VX_A9 

34 nIORD 

20 

Three Position Switch 

{6} CF_nPIOR 

9 nOE 

19 

{6} CF_nPOE 

33 nVS1 

18 

{8} CF_AUD 

8 A10 

17 

R135 

{7,15} VX_A10 

32 nCE2 

R138 

{13} CF_nCD1 

{6} CF_nPCE_2 

nCE1 

{2,14} GPIO_21 

{6} CF_nPCE_1 

7 

100K 

31 D15 

RS_RI 

100K 

16 15 

{7,15} VX_D15 

6 D07 

R136 

{7,15} VX_D7 

R140 

D14 

RS_DCD 

{13} CF_nCD2 

{7,15} VX_D14 

30 

14 13 

SA_nWE 

5 D06 

{2,4,5,6,7} 

100K 

{7,15} VX_D6 

1.5K 

29 D13 

12 11 

DC3P3V 

{7,15} VX_D13 

D05 

{3,6,11,13} JTAG_TCK 

4 

R139 

{7,15} VX_D5 

28 D12 

RS_TX 10 

9 

RS_RX 


{7,15} VX_D12 

D04 

{7,15} VX_D4 

3 

S6 

100K 

27 D11 

RS_RTS 8 7 

{7,15} VX_D11 

2 D03 

CCW 

R141 

{7,15} VX_D3 

26 nCD1 

RS_CTS 

R142 

6 5 

{6} CF_nPWAIT 

{13} CF_nCD1 

nRESET_IN 

1 GND1 

0 

{3,11,15} 

100K 

RS_DTR 4 3 

DNI 

PUSH 

RS_DSR 2 

1 

B B 

JTAG_TMS {3,6,11,13} 

CW 

22 

CPLD1_TDI {6,11} 

U25 

R144 

C86 

21 

{12,15} IN_PWR 

SA_TDO 

C87 

{3,11} 

75 

MAX3244ECAI 

0.1UF 

0.1UF 

RS-232 XCVR 

28 

27 C88 

C1+ 

V+ 

24 

3 

C89 

C1- 

V- 

DC3P3V 

{2,14} GPIO_20 

1 

0.1UF 

C2+ 

2 

0.1UF 

C2- 

{2,14} GPIO_19 

14 

RS_TX 

{2,15} SA_FF_TXD T1 IN T1OUT 

9 

13 

RS_RTS 

U26 

DC3P3V 

{2} SA_FF_RTS T2 IN T2OUT 

10 

RS_DTR 

{2} SA_FF_DTR 

12 

T3 IN T3OUT 

11 

19 

RS_RX 

MAX4542 

{2,15} SA_FF_RXD R1OUT R1 IN 

4 

18 

RS_DCD 

2 

{2} SA_FF_DCD R2OUT R2 IN 

5 

RS_DSR 

V+ 

17 

{2} SA_FF_DSR R3OUT R3 IN 

6 

RS_RI 

{2} SA_FF_RI 

16 

R4OUT R4 IN 

7 

RS_CTS 

{2,12,15} SA_I2C_SCL 

8 

COM_1 

15 

8 

A {2} SA_FF_CTS R5OUT R5 IN 

7 

1 

A 

IN_1 

NC_1 

CF_I2C_SCL 

20 

R2OUTB INVLD 

21 

RS232_VALID {3} 

{6} RS232_ON 

22 

FORCEOFF VCC 

26 

{2,12,15} SA_I2C_SDA 

4 

COM_2 NC_2 

5 

CF_I2C_SDA 

23 

GND 

25 

FORCEON 

3 


{3} SA_I2C_ENAB 

IN_2 

6 

GND 

Size Rev 

AAAF 

B 

2.07 

C90 

0.1UF 

R145 

100K 

R146 

100K 

R153 

0 

R17 

0 

1 

2 

3 

R122 

0 

U23 

4 

5 

6 

R16 

0 

R134 

100K 

2 

R133 

100K 

4.7UF 

C85 

1 

R131 

100K 

R128 

1.5K 

R127 

100K 

R126 

953 

Pg. 10 

8 

7 

6 

5 

4 

3 

Date: 


2

8 

1 

Pg. 11 


1 

7 

6 

5 

4 

3 

2 


SD Socket 

DC3P3V 

J10 

R147 10K 

D D 

Bottom Mount 

MMC_CS0 {2} RADIO_DSR {2} 

DC3P3V 

DAT2 

9 

SA_MMCMD {2} 

LAYOUT NOTE: Place close to 

Battery Header and Codec UCB 

CD_DAT3 

1 

1400 

2 

CMD 

3 

Radio 

VSS1 

C132 

4 

MMC_PWR 

Baseband 

VDD 

{8} LINE_OUT_L 

5 

DNI IF MMC 

Connector 

SA_MMCCLK {2} 

0.1UF J20 

CLK 

C140 

VSS2 

6 

R225 

{8} LINE_OUT_R 

1 

2 

0 

DAT0 

7 

SA_MMDAT {2} 

DC3P3V 

0.1UF 

3 

4 

R226 DNI 0 

MMC 

MMC_WP {2} 19 

20 

R227 DNI 100K 

{9} RADIO_MICP 

DAT1 

8 

DC3P3V 

DNI 

5 

{2} RADIO_DTR 

{2} 

6 

SA_BT_CTS 

R150 

IF 

{2} SA_BT_RTS 

7 

8 

SD 

DNI 

SA_BT_RXD 

{2,15} 

IF 

{2,15} SA_BT_TXD 

9 

10 

RADIO_RI {2} 

C C 

SD 

47.5K 

{6} RADIO_PWR_ON 

11 

12 

RADIO_RXD_C {2} 

nMMC_DETECT {2,13} 

DC3P3V 

13 

{6} RADIO_WAKE 

14 

nRESET_IN {3,10,15} CARD Selection Resistors 

15 

16 

RADIO_SPKRN 

and Values 

DNI 

{2} RADIO_DCD 

RES SD MMC 

IF 

{8,9} 17 

MICGND 

18 

RADIO_SPKRP 

{8} 

R225 0 DNI 

21 22 

{3,6,13,15} nRESET_OUT 

R228 100K DNI 

DC5P5V 

23 24 

{3,8,10,12,13,14} VBATT 

AC97_GPIO_0 {8} 

DC5P5V 

{3,8,10,12,13,14} VBATT 

25 26 

AC97_GPIO_1 {8} 

U27 

R198 

27 28 

AC97_GPIO_2 {8} 

MIC5207-3.3BM5 

0 

3.3V LDO REG 

29 30 

MMC_PWR 

{8} AC97_GPIO_4 

AC97_GPIO_3 {8} 

1 


5 

2 

GND 

+ 

B B 

{13} 3 MMC_ON EN BYP 

4 

LE33 

R226 

0 

DC3P3V 

DC3P3V 

JTAG ICE Connector 

DNI 

R236 

DVAL_1 

{15} 

DREQ_1 {15} 

DREQ_0 {15} 

J19 

{2,10} GPIO_22 

R221 

1 

2 

{3,6,10,13} 0 R219 

JTAG_TMS 0 

{15} 

R233 0 

{3} JTAG_nTRST 

3 

4 

{2,10} GPIO_21 

{6,10} 5 

6 

CPLD1_TDI 

{6,10} 0 R218 

CPLD1_TDI DVAL_0 {15} 

DNI 

{3,6,10,13} JTAG_TMS 

7 

8 

{2,10} R234 0 

GPIO_19 

0 

R232 

{3,6,10,13} 9 

10 

JTAG_TCK 

{3,6,10,13} JTAG_TCK 11 

12 

{2,10} R235 0 

GPIO_20 

{3,10} R223 

SA_TDO 

13 

14 

{3,10} 0 R231 

SA_TDO 

0 

A A 

75 R224 

{3,10,15} nRESET_IN 

15 

16 

0 

17 

18 

R222 

100K 

R270 

10K 

2 

4.7UF 

C92 

1 

R229 

100K 

R228 

100K 

10 

11 

12 

R227 

100K 

WP 

COMM 

CD 

CHECK !! 

C91 

0.1UF 

19 

20 


Size Rev 

B 

2.07 

8 

7 

6 

5 

4 

3 

Date: 


2

8 

IN_PWR {10,15} 

D10 

1 

Pg. 12 

7 

6 

5 

4 

3 

2 


5.5 Volt Supply 

D3 

DC5P5V 

Processor Core Voltage Supply 

U28 

L1 

11-TM104-NP 

4.7uH 

LTC1878 

Battery Connector 

VBATT 

+ 

8 

{3,8,10,11,13,14} 

LPF 

1 

D and Jumper Post {3,13} SA_PWR_EN 

RUN 

+ 

D 

U29 

7 

{3,8,10,11,13,14} VBATT 

J18 

SYNC-MODE 

2 

DC_CORE 

DC3P3V 

Ith 

1 

+ 

LT1308A 

{3,8,10,11,13,14} VBATT 

6 

BATTERY 

VIN 

6 

VIN SW 

5 

2 

3 

FB 

L2 

4 

2 

J17 

4 

5 1 2 

GND FB 

GND SW 

LTNX 

R159 

1 

10uH 

3 

BATT_IN_POS 

{3,13} SA_PWR_EN 

nVBATT_LOW_IRQ {3,15} 

2 

+ 

SHDN 

8 

LBO 

0 

3 

BATT_IN_NEG 

LTC1878EMS8 

R158 

4 

SA_I2C_SDA 

1 

7 

5 

{2,10,15} 

VC LBI 

6 

47.5K 

7 

SA_SMB_MODE 

1308A 

8 

nBATT_PRESENT 

R162 R163 

9 

BATT_TEMP 

{3,8,10,11,13} VBATT 

10 

976K 61.9K 

DC3P3V 

U30 

53261-1090 

LTC1663 

C 4 

VCC 

C 

VOUT 

3 

1 

{2,10,15} SA_I2C_SDA 

SDA 

GND 

2 

5 

{2,10,15} SA_I2C_SCL 

SCL 

C100 

0.1UF 

SA_I2C_SCL {2,10,15} DC_PLL {3} 

Battery Charger 

3.3 Volt Supply 

DC3P3V 

DC5P5V 

U31 

B B 

MIC5207-BM5 

+ 

ADJ LDO REG 

1 180ma 

5 

D7 

U43 

VIN VOUT 

GRN D8 

2 

RED 

GND 

PLL Voltage Supply 

3 

DC_CORE 

nCHRG SENSE 

9 

3 4 

EN BYP 

R211 

10 

Q1 

LEAA 

DC3P3V 

{2,3} nCHRGR_PRESENT nACPR 

0 

7 4 

U42 

DRV 

4 

TIMER 

DC3P3V 

MIC5207-BM5 

6 

1 

BATTERY 

ADJ LDO REG 

PROG BAT 

1 180ma 

5 

U32 

VIN VOUT 

2 

GND 

DNI 

LTC1732 

{3,8,10,11,13,14} VBATT 

ADP3335 

3 4 

{3,13} SA_PWR_EN 

BYP 

+ 

7 

5 

LEAA 

IN_1 

NR 

+ 

8 

A IN_2 

OUT_1 

1 

PLL_SENSE {3} 

A 

6 

SHUTDOWN 

22UF 

C103 

2 

OUT_2 

C104 

0.1UF 

R169 

200K 

5 

2 

C137 

2 1 

0.33F 

0.1UF 

R276 

20K 

GND 

SEL 

R168 

160K 

2 1 

2 1 

Vcc 

8 

R165 

887K 

R164 

487K 

R161 

100K 

2 

C99 

22pF 

R160 

196K 

1 

220pF 

C98 

R155 

100K 

22UF 

C97 

2 

C94 

0.1UF 

C95 

100UF 

1 

DNI 

R170 

8 

100K 

C139 

470PF 

R203 

4.99K 

33uF 

C138 

R95 

0 

R201 

357K 

C142 

R206 

5 

6 

7 

8 

0 

3 

2 

1 

R209 

C144 

1uF 

1K 

C102 

100PF 

D4 

2 1 

RED 

C101 

R166 

100UF 

1K 

R157 

150K 

R156 

100K 

LTEP 

LTC1663CS5 

R274 

1 

C143 

4.7uF 

R167 

100K 

R210 

1K 

R275 

0.1 

12 

22UF 

C96 

R220 

100K 

R154 

357K 

4 

GND 

OUT_3 

3 

LFE 

ADP3335ARM-3.3 

7 

6 

DNI 

5 

4 

3 


Size Rev 

B 

2.07 

Date: 



2 

1

8 

INDUCTOR 

1 


1 

7 

6 

5 

4 

3 

2 


LCD CPLD 

D5 

U33 

2 

R216 

DCNEG14V 

U40 

1 

{14} 

XCR3128XL-10VQ100C 

3 

100K 

Xilinx CPLD 

2 

40 

{14} LCD_G4 A0 

E0_CLK1 

MAX633ACSA 

D6 

1 

{14} LCD_G5 A2 

E2 

41 

CF_nCD1 {10} 

Adj Step-up 

100 

D {14} LCD_SPS A4 

E4 

42 

nNEP_PRESENT {4,15} 

Sw Reg 

D 

99 

LCD_DC5V 

{14} LCD_CLS A5 

E5 

44 

CF_PWR_ON {6} 

1 

8 

ZENER_3P3V 

LBI COMP 

98 

{14} LCD_LP A7 

E7 

45 

CF_PWR {10} 

DC_15V {14,15} 

DCNEG11P7V {14} 

97 

46 

{14} LCD_SPL A8 

E8 

GPIO_11 

96 

47 

{3} 

2 

7 

LBO 

VFB 

{14} LCD_G0 A10 

E10 

{14} LCD_G1 

94 

A12 

E12 

48 

nXCV_ADD_OE {6,7} 

3 6 

93 

49 

L3 

GND CP 

{14} LCD_G2 A13 

E13 

92 

50 

{14} LCD_G3 A15_CLK3 

E15 

MBREQ_CF_DETECT {3,15} 

4 

5 

LX 

VOUT 

SYSCLK {8,15} VBATT 

14 

{14} LCD_SPR B0 

F0 

52 

nGFX_PRESENT {4,15} 

470UH 

REV {4} LCD_TYPE 

13 

53 

L_DD_0 {3} 

+ 

C129 

B2 

F2 

12 

54 

L_DD_1 {3} 

MAX633ACSA 

B4 

F4 

4.7UF 

10 

{14} LCD_R2 B5 

F5 

55 

L_DD_2 

9 

{3} 

{14} LCD_R3 B7 

F7 

56 

L_DD_3 

8 

{3} 

{14} LCD_R4 B8 

F8 

57 

L_DD_4 {3} 

{14} LCD_R5 

7 

B10 

F10 

58 

L_DD_5 

6 

{3} 

{14} LCD_LBR B12 

F12 

60 

L_DD_6 

5 

{3} 

{14} LCD_PS B13 

F13 

61 

L_DD_7 

4 

{3} 

{6} CPLD1_TDO B15_TDI 

F15_TCK 

62 

JTAG_TCK {3,6,10,11,14} 

25 

{6} MMC_PWR_ON 

C0 

G0 

63 

L_DD_8 

24 

{3,4} 

{2,11} nMMC_DETECT 

C2 

G2 

64 

L_DD_9 

23 

{3,4} 

{11} MMC_ON C4 

G4 

65 

L_DD_10 

22 

{3,4} {14} SHARP_LCD_PWR_ON 

C5 

G5 

67 

L_DD_11 

C 21 

{3,4} 

{14} LCD_R0 C7 

G7 

68 

L_DD_12 {3,4} 

C 

20 

{14} LCD_R1 C8 

G8 

69 

L_DD_13 

19 

{3,4} 

{14} LCD_B1 C10 

G10 

70 

L_DD_14 

17 

{3,4} 

{14} LCD_B0 C12 

G12 

71 

L_DD_15 {14} LCD_CLK 16 

{3,4} 

C13 

G13 

72 

L_LCLK 

15 

{3} 

{3,6,10,11,14} JTAG_TMS 

C15_TMS G15_TDO 

73 

CPLD2_TDO {3} 

R213 

37 

D0_CLK2 

H0 

75 

L_FCLK 

36 

76 

{3} 

100K 

{3} nVDD_FAULT 

D2 

H2 

L_BIAS 

35 

{3} 

LCD_DC5V 

{15} VDD_FAULT D4 

H4 

77 

33 

U44 

D5 

H5 

78 

LCD_PWR_ON {6,14} 

{14} LCD_ENAB 

32 

D7 

H7 

79 

SA_PWR_EN {3,12} 

Note: On 

31 

80 

R214 

{14} LCD_NCLK D8 

H8 

nRESET_OUT {3,6,11,15} 

30 

HBL-0204 

{14} LCD_B5 D10 

H10 

81 

FLASH_nRP {5} 

A1 

VCC 

board Back 

29 

83 

H CN2-1 

{14} LCD_B2 

LCD_MODE {14} 

A2 

100K 

D12 

H12 

{3,8,10,11,12,14} 

VIN 

28 

A3 

Light Inverter 

{14} LCD_B3 D13 

H13 

84 

{14} LCD_B4 

LCD_UBL {14} 

R207 

ON_OFF 

27 

L CN2-2 

D15 

H15 

85 

{2} SA_PWM_0 

A4 

GND 

for Toshiba 

0 

87 

DNI 

PIEZOELECTRIC INVERTER Display 

{3} L_PCLK IN0_CLK0 

89 

R171 

IN1 

88 

IN2 

{10} CF_nCD2 

90 

100K 

IN3 

DC3P3V 

3 

VDD_1 

VSS_1 

11 

B 18 

26 

B 

VDD_2 

VSS_2 

34 

VDD_3 

VSS_3 

38 

39 

VDD_4 

VSS_4 

43 

51 

59 

DNI 

Back Light 

VDD_5 

VSS_5 

66 

74 

R151 

VDD_6 

VSS_6 

82 

86 

Header for 

VDD_7 

VSS_7 

{2} SA_PWM_0 

91 

VDD_8 

VSS_8 

95 

4.99K 

Off Board 

Sharp Back 

XCR3128XL-10VQ100C 

Light Inverter 

LCD_DC5V 

R172 

LCD_DC5V 

{14} VCOM 

U35 

U34 

R173 

10 

J11 

SN74HCT04D 

DC5P5V 

{14} PVEE 

SN74HCT04D 

10 

Hex Inv 

1 

C109 

Hex Inv 

R175 

1 

1A 

14 

2 

VDD 

LCD_DC4V {14} {6} LIGHT_PWR_ON 

1 

1A 

14 

2 

2 

3 

VDD 

1Y 

REV 

R152 

2 

13 

4 

1Y 

REV 

10K 

15UF 

6A 

13 

3 

12 

nREV 

2A 6Y 

0 

5 

6A 

AB_SW {14} 

{3,8,10,11,12,14} VBATT 

3 

+ 

2A 

12 

4 

6Y 

2Y 

4 

11 

A 2Y 

5A 

11 

10 

Layout Note: 

A 

5A 

5Y 

10 

5 

VBATT ADD WIDE 

53261-0590 

5Y 

3A 

5 

6 

9 

ETCH 

3A 

3Y 4A 

6 

9 

4Y 

8 

3Y 4A 

8 

V0 {14} 

7 

4Y 

GND 

7 


GND 

C111 

SN74HCT04PWR 

SN74HCT04PWR 

{14} DCNEG14V 

Size Rev 

15UF 

B 

2.07 

R177 

15K 

2 

1 

R176 

27.4K 

4.7UF 

C110 

1 

R174 

5K 

3 

C107 

0.1UF 

C108 

0.1UF 

C105 

0.1UF 

C106 

0.1UF 

+ 

+ 

R208 

+ 

0 

22UF 

C120 

C122 

0.1UF 

C126 

C127 

0.1UF 

R202 

9.76K 

1 2 

C121 

22UF 

+ 

+ 

C93 

0.1UF C128 

22UF 

0.1UF 

1 

2 

3 

Pg. 13 

8 

7 

6 

5 

4 

3 

Date: 


2

8 

C C 

1 

7 

6 

5 

4 

3 

2 


LCD Power 

3 4 

3 4 

D {6,13} LCD_PWR_ON 

EN BYP 

{6,13} LCD_PWR_ON 

EN BYP 

D 

L_DC3P3V 

L_DC3P1V 

L_DC2P6V 

L_DC3P6V 

L_DC2P3V 

LEAA 

LE50 

L_DC2P1V 

L_DC1P15V 

L_DC1P9V 

L_DC0P5V 

L_DC2P35V 

L_DC1P6V 

{13} LCD_DC4V 

L_DC2P0V 

L_DC0P9V 

L_DC1P75V 

L_DC1P45V 

DC5P5V 

MIC5207-3.3BM5 

5 

LCD_DC5V U38 

3.3V LDO REG 

1 

MIC5207-4.0BM5 

{3,8,10,11,12,13} VBATT 

180ma 

5 

VIN 

VOUT 

LCD_DC3P3V 

4.0V LDO REG 

2 

GND 

+ 

1 180ma 

VIN VOUT 

3 EN BYP 

4 

2 

GND 

LE33 

{13} SHARP_LCD_PWR_ON 

3 4 

EN BYP 

LE40 

J13 

1 

2 

U41 

MIC5207-BM5 

ADJ LDO REG 


GND 

U36 

Sharp LCD Connector 

5 

DC5P5V U37 

LCD_DC5V 

1 

2 

MIC5207-5.0BM5 

5.0V LDO REG 


GND 

5 

100UF 

+ 

C116 

Pg. 14 

LCD_DC4V {13} 

(50) 

1 

AGND 

(49) V9 

2 

V9 

LCD Grey Scale 

(48) 

Touch Screen 

V8 

3 

V8 

(47) V7 

4 

V7 

Level Buffer 

(46) 

Connector 

V6 

5 

V6 

(45) V5 

6 

U39 

V5 

(44) V4 

7 

V4 

LCD_DC5V 

(43) V3 

8 

J21 

V3 

(42) V2 

9 

V2 

LMC6009 

1 

TSPY {8} (41) V1 

10 

V1 

9 Ch Buf Amp 

2 

TSMX {8} 

(40) V0 

11 

V0 {13} for TFT-LCD 

3 

TSMY {8} 

(39) VSHA 

12 

4 

LCD_SPR {13} 

L_DC3P3V 

A1A 

4 

TSPX {8} 

(38) 

13 

5 

42 

SPR 

L_DC0P5V 

A1B 

A1 OUT 

V1 

(37) 

14 

LCD_LBR {13} 

L_DC3P1V 

6 

LBR 

A2A 

(36) DCLK 

15 

LCD_CLK {13} L_DC0P9V 

7 

41 

V2 

487951-4 

A2B 

A2 OUT 

(35) LP 16 

LCD_LP {13} 

8 

LCD_PS 

Toshiba LCD Connector 

{13} L_DC2P6V 

A3A 

(34) PS 17 

L_DC1P45V 

9 

40 

A3B 

A3 OUT 

V3 

(33) DGND 

18 

L_DC2P35V 

10 

A4A 

(32) VSHD 

19 

LCD_DC3P3V 

L_DC1P75V 

11 

39 

V4 

J14 

A4B 

A4 OUT 

(31) B5 

20 

LCD_B5 {13} 

L_DC2P1V 

12 

A5A 

(30) B4 

21 

LCD_B4 {13} 

L_DC2P0V 

13 

36 

A5B 

A5 OUT 

V5 

B B 

(29) B3 

22 

LCD_B3 {13} L_DC1P9V 

14 

A6A 

1 

(28) B2 

23 

LCD_B2 {13} 

L_DC2P3V 

15 

35 

A6B 

A6 OUT 

V6 

2 

{13} LCD_NCLK 

(27) B1 

24 

LCD_B1 {13} 16 

L_DC1P6V 

A7A 

3 

(26) B0 

25 

LCD_B0 {13} 

17 

34 

L_DC2P6V 

A7B 

A7 OUT 

V7 

4 

{13} LCD_R0 

(25) G5 

26 

LCD_G5 {13} 

18 

L_DC1P15V 

A8A 

5 

LCD_R1 {13} 

(24) G4 

27 

LCD_G4 {13} 

19 

33 

L_DC3P3V 

A8B 

A8 OUT 

V8 

6 

{13} LCD_R2 

(23) G3 

28 

LCD_G3 {13} 

L_DC0P5V 

20 

A9A 

7 

LCD_R3 {13} 

(22) G2 

29 

LCD_G2 {13} L_DC3P6V 

21 

32 

A9B 

A9 OUT 

V9 

8 

{13} LCD_R4 

(21) G1 

30 

LCD_G1 

9 

{13} LCD_R5 {13} 

(20) G0 

31 

LCD_G0 {13} 

29 

{13} AB_SW A_B_SWITCH 

10 

(19) R5 

32 

LCD_R5 

11 

{13} 

LCD_G0 {13} 

(18) R4 

33 

LCD_R4 {13} 

1 

26 

NC1 

NC8 

12 

{13} LCD_G1 

(17) R3 

34 

LCD_R3 {13} 2 

27 

NC2 

NC9 

13 

LCD_G2 {13} 

(16) R2 

35 

LCD_R2 {13} 

3 

28 

NC3 

NC10 

14 

{13} LCD_G3 

(15) R1 

36 

LCD_R1 {13} 

22 

45 

LCD_G4 {13} 

(14) R0 

37 

LCD_R0 {13} 23 NC4 

NC11 

15 

46 

NC5 

NC12 

16 

{13} LCD_G5 

(13) 

38 

SPL 

LCD_SPL {13} 

24 

47 

NC6 

NC13 

17 

(12) VCOM1 

39 

VCOM {13} 

25 

48 

NC7 

NC14 

18 

{13} LCD_B0 

(11) VCOM2 

40 

VCOM 

19 

{13} 

LCD_B1 {13} 

(10) VEE2 41 

PVEE {13} 44 

43 

{13} LCD_DC4V VDD1 

GND1 

20 

{13} LCD_B2 

(9) VEE1 42 

PVEE {13} 

38 

37 

VDD2 

GND2 

21 

LCD_B3 {13} 

(8) VSS1 43 

DCNEG14V {13} 

30 

31 

VDD3 

GND3 

{13} LCD_B4 

22 

(7) CLS 

44 

LCD_CLS 

23 

{13} 

A LCD_B5 {13} 

(6) SPS 

45 

LCD_SPS 

24 

{13} 

A 

{13} LCD_ENAB 

(5) UL 

46 

LCD_UBL 

25 

{13} (4) MOD2 

47 

LCD_MODE {13} 

26 

LCD_DC3P3V 

(3) MOD1 

48 

LCD_MODE {13} 

27 

LCD_DC3P3V 

(2) VCC1 

49 

DCNEG11P7V {13} 

(1) VDD1 50 

DC_15V 

JAE 

{13,15} 


C119 

0.1UF 

R193 

28.7K 

R194 

12.4K 

R195 

40.2K 

R196 

22.6K 

R197 

36.5K 

2 

2 

C112 

C117 

0.1UF 

4.7UF 

4.7UF 

R188 

23.7K 

R189 

34.8K 

R190 

18.7K 

R191 

27.4K 

R192 

7.32K 

C113 

0.1UF 

1 

R183 

30.1K 

R184 

30.1K 

R185 

6.19K 

R186 

40.2K 

R187 

13.7K 

R204 

150K 

2 

R178 

17.4K 

R179 

22.6K 

R180 

34.8K 

R181 

9.76K 

R182 

42.2K 

R199 

100K 

C114 

0.1UF 

4.7UF 

+ 

C115 

1 

+ 

C118 

1 

IL-FHJ-27S-HF 

Molex 

TOP_CONN_50 

Size Rev 

B 

2.07 

8 

7 

6 

54104-5090 

5 

4 

3 

Date: 


2 


1

8 

1 

7 

6 

5 

4 

3 

2 


J15 

RCPT AMP 

J16 

RCPT AMP 

2 

1 

2 

1 

Pg. 15 

4 

{6,10} VX_A0 

C1 

3 

VX_A1 {6,10} 

4 

{6,10} VX_A0 

C1 

3 

VX_A1 

C2 

C1 

C2 

C1 

{6,10} 

6 

{6,10} VX_A2 

C2 

5 

VX_A3 {6,10} 

6 

VX_A5 {7,10} 

{6,10} VX_A2 

C2 

5 

VX_A3 

8 

7 

8 

7 

{6,10} 

{7,10} VX_A4 

{7,10} VX_A4 

VX_A5 

10 

{7,10} 

{7,10} VX_A6 

C3 

9 

VX_A7 {7,10} 

10 

{7,10} VX_A6 

C3 

9 

VX_A7 

C4 

C3 

C4 

C3 

{7,10} 

12 

{7,10} VX_A8 

C4 

11 

VX_A9 {7,10} 

12 

VX_A11 {7} 

{7,10} VX_A8 

C4 

11 

VX_A9 

14 

13 

14 

13 

{7,10} 

{7,10} VX_A10 

D {7} VX_A12 

VX_A13 {7} 

{7,10} VX_A10 

VX_A11 

16 

15 

16 

15 

{7} 

VX_A13 D 

DC3P3V 

{7} VX_A12 

18 

17 

{7} VX_A14 

VX_A15 {7} 

DC3P3V 

18 

17 

{7} 

VX_A15 {7} DC3P3V 

{7} VX_A16 

VX_A17 {7} 

{7} VX_A14 

20 

19 

DC3P3V 

20 

19 

VX_A19 {7} 

{7} VX_A16 

VX_A17 

22 

21 

22 

21 

{7} 

{7} VX_A18 

{7} VX_A20 

VX_A21 {7} 

{7} VX_A18 

VX_A19 

24 

{7} 

C5 

23 

24 

{7} VX_A20 

C5 

23 

VX_A21 

C6 

C5 

C6 

C5 

{7} 

26 

{7} VX_A22 

C6 

25 

VX_A23 {7} 

26 

{7} VX_A24 

VX_A25 {7} 

{7} VX_A22 

C6 

25 

VX_A23 

28 

27 

28 

27 

{7} 

{7} VX_A24 

VX_A25 

30 

{7} 

C7 

29 

30 

C7 

29 

C8 

C7 

C8 

C7 

{7} VX_nSDCS_0 

32 

C8 

31 

VX_nSDCS_2 {6} 

{7} VX_nSDCS_0 

32 

C8 

31 

VX_nSDCS_2 

{7} 

34 

33 

VX_nSDCAS 

VX_DQM_3 {7} 

34 

33 

{6} 

{7} VX_nSDCAS 

VX_DQM_3 {7} VX_nSDRAS 36 

35 

VX_DQM_2 {7} 

36 

35 

{7} 

VX_DQM_1 {7} 

{7} VX_nSDRAS 

VX_DQM_2 

38 

37 

38 

37 

{7} 


{2} SA_SDCKE_0 

VX_DQM_0 {7} 


VX_DQM_1 

40 

39 

40 

39 

{7} 

{2} SA_SDCKE_0 

VX_DQM_0 {7} 


42 

41 


42 

41 

{6} VX_SDCKE_1 

44 

C9 

43 

SA_SDCLK_0 {2,5} 

{6} VX_SDCKE_1 

44 

C9 

43 

SA_SDCLK_0 

C10 

C9 

C10 

C9 

{2,5} 

46 

C10 

45 

46 

C10 

45 

48 

47 

{7} VX_SDCLK_1 

VX_SDCLK_2 {6} 

48 

47 

{7} VX_SDCLK_1 

VX_SDCLK_2 

50 

{6} 

C11 

49 

50 

C11 

49 

C12 

C11 

C12 

C11 


52 

C12 

51 



52 

C12 

51 


{4,13} 

54 

53 

nGFX_PRESENT 

MBGNT_CF_IRQ {3,6} 

{4,13} 

54 

53 

nGFX_PRESENT 

MBGNT_CF_IRQ {3,6} 

C 56 

55 


DREQ_1 {11} 

56 

55 

C 

nJTAG_TRST 

VX_D1 {7,10} 


DREQ_1 

58 

57 

58 

57 

{11} 

VX_D1 

LCD_DC5V 

nJTAG_TRST 

60 

59 

{7,10} 

{7,10} VX_D0 

VX_D3 {7,10} LCD_DC5V 

60 

59 

{7,10} VX_D2 

VX_D5 {7,10} 

{7,10} VX_D0 

VX_D3 {7,10} LCD_DC5V 

62 

61 

{7,10} VX_D2 

62 

61 

VX_D5 

{7,10} VX_D4 

64 

{7,10} 

C13 

63 

VX_D7 {7,10} 

{7,10} VX_D4 

64 

C13 

63 

VX_D7 

C14 

C13 

LCD_DC5V 

C14 

C13 

{7,10} 

{7,10} VX_D6 

66 

C14 

65 

VX_D9 {7,10} 

{7,10} VX_D6 

66 

C14 

65 

VX_D9 

68 

67 

{7,10} 

{7,10} VX_D8 

VX_D11 {7,10} 

68 

67 

VX_D11 {7,10} DC3P3V 

{7,10} VX_D10 

VX_D13 {7,10} 

{7,10} VX_D8 

70 

DC3P3V 

C15 

69 

70 

{7,10} VX_D10 

C15 

69 

VX_D13 

C16 

C15 

C16 

C15 

{7,10} 

72 

{7,10} VX_D12 

C16 

71 

VX_D15 {7,10} 

72 

{7,10} VX_D12 

C16 

71 

VX_D15 {7,10} 

{7,10} VX_D14 

74 

73 

{7,10} VX_D14 

74 

73 

76 

75 

{7} VX_D16 

VX_D17 {7} 

76 

75 

{7} VX_D18 

VX_D19 {7} 

{7} VX_D16 

VX_D17 

78 

77 

78 

77 

{7} 

VX_D19 {7} 

{7} VX_D20 

VX_D21 {7} 

{7} VX_D18 

80 

79 

80 

79 

VX_D21 {7} 

{7} VX_D22 

VX_D23 {7} 

{7} VX_D20 

82 

81 

82 

81 

VX_D23 {7} 

{7} VX_D24 

VX_D25 {7} 

{7} VX_D22 

84 

C17 

83 

{7} VX_D24 

84 

C17 

83 

VX_D25 

C18 

C17 

C18 

C17 

{7} 

86 

{7} VX_D26 

C18 

85 

VX_D27 {7} 

{7} 

86 

{7} VX_D28 

VX_D29 {7} 

VX_D26 

C18 

85 

VX_D27 

88 

87 

88 

87 

{7} 

{7} VX_D30 

VX_D31 {7} 

{7} VX_D28 

VX_D29 

90 

{7} 

C19 

89 

90 

{7} VX_D30 

C19 

89 

VX_D31 

C20 

C19 

C20 

C19 

{7} 

{4,13} nNEP_PRESENT 

92 

C20 

91 

IN_PWR {10,12} 

{4,13} nNEP_PRESENT 

92 

C20 

91 

IN_PWR 

94 

93 

{10,12} 

{2} SA_RDY 

SA_nCS_5 {2,6} DC3P3V 

94 

93 

SA_nCS_5 {2,6} 

B B 

{7} VX_nWE 

SA_nCS_4 {2,6} 

{7} {2} 

VX_nWE 

SA_RDY 

96 

95 

96 

95 

SA_nCS_4 

DC3P3V 

{2,6} 

{6,7} VX_nOE 

98 

97 

SA_nCS_3 {2,6} 

DC3P3V 

{6,7} VX_nOE 

98 

97 

SA_nCS_3 {2,6} DC3P3V 

{13,14} 

100 

99 

DC_15V 

nNEP_REG_CS {6,10} 

{13,14} DC_15V 

100 

99 

nNEP_REG_CS {6,10} 

{3,10,11} 

102 

101 

nRESET_IN 

nNEP_FLASH_CS {6} 

{3,10,11} nRESET_IN 

102 

101 

nNEP_FLASH_CS {6} 

{3,6,11,13} nRESET_OUT 

104 

C21 

103 

SA_nCS_0 {2,6} 

{3,6,11,13} nRESET_OUT 

104 

C21 

103 

SA_nCS_0 {2,6} 

C22 

C21 

C22 

C21 


106 

C22 

105 


106 

C22 

105 


108 

107 

SYSCLK {8,13} {3,10} GFX_IRQ_CF_BVD2 

108 

107 

SYSCLK {8,13} 

110 

110 

{13} VDD_FAULT C23 

109 

{13} VDD_FAULT C23 

109 

C24 

C23 

C24 

C23 

112 

{3,10} SA1111_IRQ_CF_BVD1 

C24 

111 

SA_nPOE {2,6} 

112 

{10,12} IN_PWR 

SA_nPWE {2,6} 

{3,10} SA1111_IRQ_CF_BVD1 

C24 

111 

SA_nPOE 

114 

113 

114 

113 

{2,6} 

{2,6} SA_nIOIS16 

SA_nPIOW {2,6} 

{10,12} IN_PWR 

SA_nPWE 

116 

115 

116 

115 

{2,6} 

{2,6} SA_nIOIS16 

SA_nPIOW 

118 

117 

{2,6} 


SA_nPIOR {2,6} 

118 

117 


SA_nPIOR 

120 

119 

{2,6} 


SA_nPCE_1 {2,6} 

120 

119 


SA_nPCE_1 {2,6} 


122 

121 

SA_nPCE_2 {2,6} 


122 

121 

SA_nPCE_2 {2,6} 

124 

C25 

123 

124 

C25 

123 

C26 

C25 

C26 

C25 

126 

{11} DVAL_1 

C26 

125 

SA_BT_RXD {2,11} 

126 

SA_BT_RXD {2,11} 

{11} DVAL_0 

SA_BT_TXD {2,11} 

{11} DVAL_1 

C26 

125 

128 

127 

128 

127 

{11} DVAL_0 

SA_BT_TXD {2,11} 

130 

{11} DREQ_0 

C27 

129 

SWAP_FLASH {6} 

130 

{11} DREQ_0 

C27 

129 

SWAP_FLASH 

C28 

C27 

C28 

C27 

{6} 

{3,10} GPIO_0 

132 

C28 

131 

SA_FF_TXD {2,10} 

{3,10} GPIO_0 

132 

C28 

131 

SA_FF_TXD 

134 

133 

{2,10} 

A {3,9} USB_WAKE 

SA_FF_RXD {2,10} 

134 

133 

{3,9} USB_WAKE 

SA_FF_RXD 

136 

135 

136 

135 

{2,10} 

A 

{2,10,12} SA_I2C_SDA 

138 

137 

{2,10,12} SA_I2C_SCL 

nVBATT_LOW_IRQ {3,12} 

{2,10,12} SA_I2C_SDA 

138 

137 

{2,10,12} SA_I2C_SCL 

nVBATT_LOW_IRQ 

140 

139 

140 

139 

{3,12} 

536279-6 

536279-6 


8 

Expansion 

Header 1 

7 

6 

5 

4 

Expansion 

Header 2 

3 

Size Rev 

B 

2.07 

Date: 



2 

1

8 

B B 

A A 


1 

Pg. 16 


1 

7 

6 

5 

4 

3 

2 


Revision Tracking Changes 

R 2.00 - 09-21-01 - Inital Release 

R 2.01 - 09-25-01 - CHRGR_PRESENT signal changed to nCHRGR_PRESENT to properly represent active low signal - Pages 2, 3 & 12 

R 2.01 - 09-25-01 - R281, nCHRGR_PRESENT 100k pull-up added - Page 2 

R 2.01 - 09-25-01 - R262, PLL_SENSE pull-down, removed from DNI list - Page 3 

R 2.01 - 09-25-01 - C60, C65, R97 & R98 Removed from schematics - Page 8 

D D 

R 2.01 - 09-25-01 - C3 & C4 values changed to 1uF - Page 9 

R 2.01 - 09-25-01 - U20 powered from AUDIO3P3V instead of DC3P3V - Page 9 

R 2.01 - 09-25-01 - C138 Added to DNI List - Page 12 

R 2.02 - 09-28-01 - U10, XCR3032C CPLD, replaced with newer XPLA3 XCR3032XL - Page 6 

R 2.02 - 09-28-01 - Changed U43 part description to properly reflect part - Page 12 

R 2.02 - 09-28-01 - R276 9.76k resistor replaced with 19.6k resistor - Page 12 

R 2.02 - 09-28-01 - R276 .15 ohm resistor replaced with .1 ohm resistor - Page 12 

R 2.02 - 09-28-01 - U33, XCR3128 CPLD, replaced with newer XPLA3 XCR3128XL - Page 13 

R 2.03 - 10-10-01 - Y4, Changed component vendor - Page 3 

R 2.03 - 10-10-01 - R275, Changed component vendor - Page 12 

R 2.03 - 10-10-01 - R276, 19.6k resistor, replaced with 20k resistor - Page 12 

R 2.04 - 10-12-01 - Q1, P-channel MOSFET, replaced with a higher power dissipating component - Page 12 

R 2.05 - 10-16-01 - C53,C54,C55 & C56 Moved to prevent coupling with the UCB1400 - Page 8 

R 2.05 - 10-16-01 - R282, 0 ohm resistor, Added UCB1400 power test point- Page 8 

R 2.05 - 10-16-01 - R99, 0 ohm resistor, replaced with 10 ohm resistor - Page 8 

R 2.05 - 10-16-01 - R99 connected to AUDIO3P3V - Page 8 

R 2.06 - 11-09-01 - Y4, Changed component vendor - Page 3 

R 2.06 - 11-09-01 - R275, Changed component vendor - Page 12 

R 2.06 - 11-09-01 - Changed C143 part description to properly reflect part- Page 12 

R 2.07 - 02-05-02 - U2, 3.1V Reset Supervisor, replaced with 2.7V Reset Supervisor - Page 3 

R 2.07 - 02-05-02 - R112 & R115, 27.4 ohm resistor, replaced with 0 ohm resistor- Page 9 

R 2.07 - 02-05-02 - R168, 150K resistor, replaced with a 160K resistor - Page 12 

R 2.07 - 02-05-02 - R170, 100K resistor, added to DNI list - Page 12 

C R 2.07 - 02-05-02 - R210, 1K resistor, disconnected from IN_PWR net and connected to DC3P3V instead - Page 12 

C 

Size Rev 

B 

2.07 

8 

7 

6 

5 

4 

3 

Date: 


2

Example Form Factor Reference Design Schematic Diagrams 

B-18 PXA250 and PXA210 Applications Processors Design Guide

BBPXA2xx Development Baseboard 

Schematic Diagram 

C 

C.1 Schematic Diagram 

The BBPXA2xx schematic is on the following pages. 

PXA250 and PXA210 Applications Processors Design Guide C-1

Page Function Page Function Page Function 

BBPXA2xx 

Table of Contents 

2 Top level block diagram 

18 SWITCHES 

34 LOGIC ANALYZER 

3 Processor Card Connector 

4 Data Buffers/Transceivers 

5 Data Buffers/Transceivers 

6 Address BUFFERS/TRANSCEIVERS 

7 SPX ADDRESS BUFFERS 

8 CONTROL BUFFERS/TRANSCEIVERS 

9 X ADDRESS BUFFERS 

10 BFR ADDRESS BUFFERS 

11 SRAM 

12 FLASH 

13 ROM 

14 REGISTER & CONTROL 

15 HEX DISPLAY HIGH 

16 HEX DISPLAY LOW 

17 LEDs & HEX SWITCHES 

19 SPII SPROM 

20 SA-1111 INTERFACE 

21 CF & PCMCIA I/O 

22 CF & PCMCIA PU 

23 SA-1111 USB KB/MS 

24 BUFFER CONTROL LOGIC 

25 LCD BUFFERS 

26 IrDA & FF SERIAL & USB 

27 CS4201 CODEC 

28 UCB1400 CODEC 

29 BB TOUCH SCREEN & GPIO HEADER 

30 CODEC MUX & SPII 2.5V 

31 SDCARD & BT SERIAL 

32 10Mbps ETHERNET 

33 XPANSION PORT 

35 RESET & FAULT SWITCHES 

36 3.3V & 5V SUPPLY 

37 POWER SUPPLY INPUT 

38 SPARES

BBPXA2xx Development Baseboard Schematic Diagram 

C-40 PXA250 and PXA210 Applications Processors Design Guide

PXA250 Processor Card Schematic 

Diagram 

D 

D.1 Schematic Diagram 

The DCPXA250 processor card schematic is on the following pages. 

PXA250 and PXA210 Applications Processors Design Guide D-1

DCPXA250 Processor Card 

32-bit version 

TABLE OF CONTENTS 

PAGE FUNCTION 

2 PROCESSOR --- PXA250 32-BIT 

3 SDRAM 

4 CONNECTOR (MEMORY and I/O SIGNALS) 

5 CLOCKS 

6 JTAG CONNECTOR & 

PLL and CORE VOLTAGE REGULATORS 

7 VOLTAGE REGULATOR CONTROL 

CPLD AND I/O EXPANDER 

8 Visibility 

9-11 Bus Terminators

PXA210 Processor Card Schematic 

Diagram 

E 

E.1 Schematic Diagram 

The DCPXA210 processor card schematic is on the following pages. 

PXA250 and PXA210 Applications Processors Design Guide E-1

DCPXA210 Processor Card 

4 CONNECTOR (MEMORY and I/O SIGNALS) 

6 JTAG CONNECTOR & 

PLL and CORE VOLTAGE REGULATORS 

9-13 Bus Terminators and Signal MUX 

16-bit version 

TABLE OF CONTENTS 

PAGE FUNCTION 

2 PROCESSOR --- PXA210 16-BIT 

3 SDRAM 

5 CLOCKS 

7 VOLTAGE REGULATOR CONTROL 

CPLD AND I/O EXPANDER 

8 Visibility

PXA210 Processor Card Schematic Diagram 

PXA250 and PXA210 Applications Processors Design Guide E-3

Intel PXA250 and PXA210 Applications Processors

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