Intel PXA250 and PXA210 Applications Processors
Intel PXA250 and PXA210 Applications Processors
Intel PXA250 and PXA210 Applications Processors
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<strong>Intel</strong> ® <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong><br />
<strong>Applications</strong> <strong>Processors</strong><br />
Design Guide<br />
February, 2002<br />
Order Number: 278523-001
Information in this document is provided in connection with <strong>Intel</strong> ® products. No license, express or implied, by estoppel or otherwise, to any intellectual<br />
property rights is granted by this document. Except as provided in <strong>Intel</strong>’s Terms <strong>and</strong> Conditions of Sale for such products, <strong>Intel</strong> assumes no liability<br />
whatsoever, <strong>and</strong> <strong>Intel</strong> disclaims any express or implied warranty, relating to sale <strong>and</strong>/or use of <strong>Intel</strong> products including liability or warranties relating to<br />
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. <strong>Intel</strong> products are not<br />
intended for use in medical, life saving, or life sustaining applications.<br />
<strong>Intel</strong> may make changes to specifications <strong>and</strong> product descriptions at any time, without notice.<br />
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” <strong>Intel</strong> reserves these for<br />
future definition <strong>and</strong> shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.<br />
The <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> applications processors may contain design defects or errors known as errata which may cause the product to deviate from<br />
published specifications. Current characterized errata are available on request.<br />
MPEG is an international st<strong>and</strong>ard for video compression/decompression promoted by ISO. Implementations of MPEG CODECs, or MPEG enabled<br />
platforms may require licenses from various entities, including <strong>Intel</strong> Corporation.<br />
This document <strong>and</strong> the software described in it are furnished under license <strong>and</strong> may only be used or copied in accordance with the terms of the<br />
license. The information in this document is furnished for informational use only, is subject to change without notice, <strong>and</strong> should not be construed as a<br />
commitment by <strong>Intel</strong> Corporation. <strong>Intel</strong> Corporation assumes no responsibility or liability for any errors or inaccuracies that may appear in this<br />
document or any software that may be provided in association with this document. Except as permitted by such license, no part of this document may<br />
be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of <strong>Intel</strong> Corporation.<br />
Contact your local <strong>Intel</strong> sales office or your distributor to obtain the latest specifications <strong>and</strong> before placing your product order.<br />
Copies of documents which have an ordering number <strong>and</strong> are referenced in this document, or other <strong>Intel</strong> literature may be obtained by calling<br />
1-800-548-4725 or by visiting <strong>Intel</strong>'s website at http://www.intel.com.<br />
Copyright © <strong>Intel</strong> Corporation, 2002<br />
AlertVIEW, i960, AnyPoint, AppChoice, BoardWatch, BunnyPeople, CablePort, Celeron, Chips, Commerce Cart, CT Connect, CT Media, Dialogic,<br />
DM3, EtherExpress, ETOX, FlashFile, GatherRound, i386, i486, iCat, iCOMP, Insight960, InstantIP, <strong>Intel</strong>, <strong>Intel</strong> logo, <strong>Intel</strong>386, <strong>Intel</strong>486, <strong>Intel</strong>740,<br />
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logo, OverDrive, Paragon, PC Dads, PC Parents, Pentium, Pentium II Xeon, Pentium III Xeon, Performance at Your Comm<strong>and</strong>, ProShare,<br />
RemoteExpress, Screamline, Shiva, SmartDie, Solutions960, Sound Mark, StorageExpress, The Computer Inside, The Journey Inside, This Way In,<br />
TokenExpress, Trillium, Vivonic, <strong>and</strong> VTune are trademarks or registered trademarks of <strong>Intel</strong> Corporation or its subsidiaries in the United States <strong>and</strong><br />
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*Other names <strong>and</strong> br<strong>and</strong>s may be claimed as the property of others.<br />
ii<br />
<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide
Contents<br />
Contents<br />
1 Introduction.................................................................................................................................1-1<br />
1.1 Functional Overview ..........................................................................................................1-1<br />
1.2 Package Information..........................................................................................................1-2<br />
1.2.1 Package Introduction ............................................................................................1-2<br />
1.2.2 Signal Pin Descriptions.........................................................................................1-4<br />
2 System Memory Interface ..........................................................................................................2-1<br />
2.1 Overview............................................................................................................................2-1<br />
2.2 SDRAM Interface...............................................................................................................2-3<br />
2.3 SDRAM memory wiring diagram .......................................................................................2-3<br />
2.4 SDRAM Support ................................................................................................................2-5<br />
2.5 SDRAM Address Mapping.................................................................................................2-6<br />
2.6 Static Memory....................................................................................................................2-7<br />
2.6.1 Overview...............................................................................................................2-7<br />
2.6.2 Boot Time Defaults ...............................................................................................2-8<br />
2.6.3 SRAM / ROM / Flash / Synchronous Fast Flash Memory Options .......................2-9<br />
2.6.4 Variable Latency I/O Interface Overview ..............................................................2-9<br />
2.6.5 External Logic for PCMCIA Implementation .......................................................2-11<br />
2.6.6 DMA / Companion Chip Interface .......................................................................2-14<br />
2.7 System Memory Layout Guidelines .................................................................................2-17<br />
2.7.1 System Memory Topologies (Min <strong>and</strong> Max Simulated Loading).........................2-17<br />
2.7.2 System Memory Recommended Trace Lengths.................................................2-18<br />
3 LCD Display Controller ..............................................................................................................3-1<br />
3.1 LCD Display Overview.......................................................................................................3-1<br />
3.2 Passive (DSTN) Displays ..................................................................................................3-1<br />
3.2.1 Typical Connections for Passive Panel Displays..................................................3-2<br />
3.2.1.1 Passive Monochrome Single Panel Displays........................................3-2<br />
3.2.1.2 Passive Monochrome Single Panel Displays, Double-Pixel Data.........3-3<br />
3.2.1.3 Passive Monochrome Dual Panel Displays ..........................................3-3<br />
3.2.1.4 Passive Color Single Panel Displays ....................................................3-4<br />
3.2.1.5 Passive Color Dual Panel Displays.......................................................3-4<br />
3.3 Active (TFT) Displays ........................................................................................................3-5<br />
3.3.1 Typical connections for Active Panel Displays......................................................3-6<br />
3.4 <strong>PXA250</strong> Pinout ..................................................................................................................3-7<br />
3.5 Additional Design Considerations......................................................................................3-8<br />
3.5.1 Contrast Voltage ...................................................................................................3-8<br />
3.5.2 Backlight Inverter ..................................................................................................3-8<br />
3.5.3 Signal Routing <strong>and</strong> Buffering ................................................................................3-8<br />
3.5.4 Panel Connector ...................................................................................................3-9<br />
4 USB Interface ..............................................................................................................................4-1<br />
4.1 Self Powered Device .........................................................................................................4-1<br />
4.1.1 Operation if GPIOn <strong>and</strong> GPIOx are Different Pins................................................4-1<br />
4.1.2 Operation if GPIOn <strong>and</strong> GPIOx are the Same Pin................................................4-2<br />
4.2 Bus Powered Device .........................................................................................................4-2<br />
<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide<br />
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Contents<br />
5 MultiMediaCard (MMC)...............................................................................................................5-1<br />
5.1 Schematics ........................................................................................................................5-1<br />
5.1.1 Signal Description.................................................................................................5-1<br />
5.1.2 How to Wire ..........................................................................................................5-2<br />
5.1.2.1 SDCard Socket .....................................................................................5-4<br />
5.1.2.2 MMC Socket .........................................................................................5-4<br />
5.1.3 Simplified Schematic ............................................................................................5-5<br />
5.1.4 Pull-up <strong>and</strong> Pull-down...........................................................................................5-6<br />
5.2 Utilized Features................................................................................................................5-6<br />
6 AC97 ............................................................................................................................................6-1<br />
6.1 Schematics ........................................................................................................................6-1<br />
6.2 Layout................................................................................................................................6-2<br />
7 I2C................................................................................................................................................7-1<br />
7.1 Schematics ........................................................................................................................7-1<br />
7.1.1 Signal Description.................................................................................................7-1<br />
7.1.2 Digital-to-Analog Converter (DAC) .......................................................................7-2<br />
7.1.3 Other Uses of I2C .................................................................................................7-2<br />
7.1.4 Pull-Ups <strong>and</strong> Pull-Downs ......................................................................................7-3<br />
7.2 Utilized Features................................................................................................................7-4<br />
8 Power <strong>and</strong> Clocking ...................................................................................................................8-1<br />
8.1 Operating Conditions.........................................................................................................8-1<br />
8.2 Electrical Specifications .....................................................................................................8-2<br />
8.3 Power Consumption Specifications ...................................................................................8-2<br />
8.4 Oscillator Electrical Specifications .....................................................................................8-4<br />
8.4.1 32.768 kHz Oscillator Specifications ....................................................................8-4<br />
8.4.2 3.6864 MHz Oscillator Specifications ...................................................................8-5<br />
8.5 Reset <strong>and</strong> Power AC Timing Specifications ......................................................................8-6<br />
8.5.1 Power Supply Connectivity ...................................................................................8-6<br />
8.5.2 Power On Timing ................................................................................................8-11<br />
8.5.3 Hardware Reset Timing ......................................................................................8-12<br />
8.5.4 Watchdog Reset Timing .....................................................................................8-13<br />
8.5.5 GPIO Reset Timing.............................................................................................8-13<br />
8.5.6 Sleep Mode Timing.............................................................................................8-14<br />
8.6 Memory Bus <strong>and</strong> PCMCIA AC Specifications .................................................................8-15<br />
8.7 Example Form Factor Reference Design Power Delivery Example ................................8-20<br />
8.7.1 Power System.....................................................................................................8-20<br />
8.7.1.1 Power System Configuration ..............................................................8-21<br />
8.7.2 CORE Power ......................................................................................................8-22<br />
8.7.3 PLL Power ..........................................................................................................8-22<br />
8.7.4 I/O 3.3 V Power ..................................................................................................8-23<br />
8.7.5 Peripheral 5.5 V Power.......................................................................................8-23<br />
9 JTAG/Debug Port........................................................................................................................9-1<br />
9.1 Description.........................................................................................................................9-1<br />
9.2 Schematics ........................................................................................................................9-1<br />
9.3 Layout................................................................................................................................9-2<br />
A SA-1110/<strong>Applications</strong> Processor Migration ............................................................................ A-1<br />
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A.1 SA-1110 Hardware Migration Issues ................................................................................ A-2<br />
A.1.1 Hardware Compatibility........................................................................................ A-2<br />
A.1.2 Signal Changes ................................................................................................... A-2<br />
A.1.3 Power Delivery..................................................................................................... A-4<br />
A.1.4 Package............................................................................................................... A-4<br />
A.1.5 Clocks .................................................................................................................. A-4<br />
A.1.6 UCB1300 ............................................................................................................. A-5<br />
A.2 SA-1110 to <strong>PXA250</strong> Software Migration Issues ............................................................... A-5<br />
A.2.1 Software Compatibility ......................................................................................... A-6<br />
A.2.2 Address space ..................................................................................................... A-6<br />
A.2.3 Page Table Changes ........................................................................................... A-6<br />
A.2.4 Configuration registers......................................................................................... A-6<br />
A.2.5 DMA..................................................................................................................... A-7<br />
A.3 Using New <strong>PXA250</strong> Features ........................................................................................... A-7<br />
A.3.1 <strong>Intel</strong>® XScale Microarchitecture....................................................................... A-8<br />
A.3.2 Debugging ........................................................................................................... A-8<br />
A.3.3 Cache Attributes .................................................................................................. A-8<br />
A.3.4 Other features...................................................................................................... A-8<br />
A.3.5 Conclusion ........................................................................................................... A-9<br />
B Example Form Factor Reference Design Schematic Diagrams ............................................ B-1<br />
B.1 Notes ................................................................................................................................ B-1<br />
B.2 Schematic Diagrams......................................................................................................... B-1<br />
C BBPXA2xx Development Baseboard Schematic Diagram .................................................... C-1<br />
C.1 Schematic Diagram .......................................................................................................... C-1<br />
D <strong>PXA250</strong> Processor Card Schematic Diagram ......................................................................... D-1<br />
D.1 Schematic Diagram .......................................................................................................... D-1<br />
E <strong>PXA210</strong> Processor Card Schematic Diagram ......................................................................... E-1<br />
E.1 Schematic Diagram .......................................................................................................... E-1<br />
<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide<br />
v
Contents<br />
Figures<br />
1-1 <strong>Applications</strong> Processor Block Diagram......................................................................................1-2<br />
1-2 <strong>PXA250</strong> <strong>Applications</strong> Processor..............................................................................................1-11<br />
1-3 <strong>PXA210</strong> <strong>Applications</strong> Processor..............................................................................................1-15<br />
2-1 General Memory Interface Configuration ..................................................................................2-2<br />
2-2 SDRAM Memory System Example............................................................................................2-4<br />
2-3 32-Bit Variable Latency I/O Read Timing (Burst-of-Four, One Wait Cycle Per Beat)..............2-10<br />
2-4 Expansion Card External Logic for a Two-Socket Configuration.............................................2-12<br />
2-5 Expansion Card External Logic for a One-Socket Configuration.............................................2-13<br />
2-6 Alternate Bus Master Mode .....................................................................................................2-15<br />
2-7 Variable Latency I/O ................................................................................................................2-16<br />
2-8 CS, CKE, DQM, CLK, MA minimum loading topology.............................................................2-17<br />
2-9 CS, CKE, DQM, CLK, MA Maximum Loading Topology .........................................................2-17<br />
2-10MD Minimum Loading Topology..............................................................................................2-17<br />
2-11MD maximum loading topology ...............................................................................................2-18<br />
3-1 Single Panel Monochrome Passive Display Typical Connection ..............................................3-3<br />
3-2 Passive Monochrome Single Panel Displays, Double-Pixel Data Typical Connection..............3-3<br />
3-3 Passive Monochrome Dual Panel Displays Typical Connection ...............................................3-4<br />
3-4 Passive Color Single Panel Displays Typical Connection .........................................................3-4<br />
3-5 Passive Color Dual Panel Displays Typical Connection............................................................3-5<br />
3-6 Active Color Display Typical Connection...................................................................................3-7<br />
4-1 Self Powered Device .................................................................................................................4-1<br />
5-1 <strong>Applications</strong> Processor MMC <strong>and</strong> SDCard Signal Connections................................................5-3<br />
5-2 <strong>Applications</strong> Processor MMC to SDCard Simplified Signal Connection....................................5-5<br />
6-1 AC97 connection .......................................................................................................................6-1<br />
7-1 Linear Technology DAC with I2C Interface ...............................................................................7-2<br />
7-2 Using an Analog Switch to Allow a Second CF Card ................................................................7-3<br />
7-3 I 2 C Pull-Ups <strong>and</strong> Pull-Downs.....................................................................................................7-3<br />
8-1 Power-On Reset Timing ..........................................................................................................8-12<br />
8-2 Hardware Reset Timing...........................................................................................................8-13<br />
8-3 GPIO Reset Timing .................................................................................................................8-13<br />
8-4 Sleep Mode Timing..................................................................................................................8-14<br />
8-5 Example Form Factor Reference Design Power System Design............................................8-22<br />
9-1 JTAG/Debug Port Wiring Diagram ............................................................................................9-1<br />
Tables<br />
1-1 Revision History.........................................................................................................................1-1<br />
1-2 Related Documentation .............................................................................................................1-1<br />
1-3 Signal Pin Descriptions..............................................................................................................1-4<br />
1-4 <strong>PXA250</strong> <strong>Applications</strong> Processor Pinout — Ballpad Number Order .........................................1-12<br />
1-5 <strong>PXA210</strong> <strong>Applications</strong> Processor Pinout — Ballpad Number Order .........................................1-16<br />
2-1 Memory Address Map ...............................................................................................................2-3<br />
2-2 SDRAM Memory Types Supported by the <strong>Applications</strong> Processor...........................................2-5<br />
2-3 Normal Mode Memory Address Mapping ..................................................................................2-6<br />
2-4 <strong>Applications</strong> Processor Compatibility Mode Address Line Mapping..........................................2-7<br />
2-5 Valid Booting Configurations Based on Package Type .............................................................2-8<br />
2-6 BOOT_SEL Definitions..............................................................................................................2-8<br />
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Contents<br />
2-7 SRAM / ROM / Flash / Synchronous Fast Flash AC Specifications ..........................................2-9<br />
2-8 Variable Latency I/O Interface AC Specifications ....................................................................2-10<br />
2-9 Card Interface (PCMCIA or Compact Flash) AC Specifications ..............................................2-13<br />
2-10Minimum <strong>and</strong> Maximum Trace Lengths for the SDRAM Signals.............................................2-18<br />
3-1 LCD Controller Data Pin Utilization............................................................................................3-1<br />
3-2 Passive Display Pins Required..................................................................................................3-2<br />
3-3 Active Display Pins Required.....................................................................................................3-6<br />
3-4 <strong>PXA250</strong> LCD Controller Ball Positions ......................................................................................3-7<br />
5-1 MMC Signal Description ............................................................................................................5-1<br />
5-2 SDCard Socket Signals .............................................................................................................5-2<br />
5-3 MMC Controller Supported Sockets <strong>and</strong> Devices .....................................................................5-2<br />
5-4 SDCard Pull-up <strong>and</strong> Pull-down Resistors ..................................................................................5-6<br />
5-5 MMC Pull-up <strong>and</strong> Pull-down Resistors ......................................................................................5-6<br />
7-1 I2C Signal Description ...............................................................................................................7-1<br />
8-1 Voltage, Temperature, <strong>and</strong> Frequency Electrical Specifications ...............................................8-1<br />
8-2 Absolute Maximum Ratings .......................................................................................................8-2<br />
8-3 Power Consumption Specifications ...........................................................................................8-3<br />
8-4 32.768 kHz Oscillator Specifications .........................................................................................8-4<br />
8-5 3.6864 MHz Oscillator Specifications ........................................................................................8-5<br />
8-6 <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> VCCN vs. VCCQ ....................................................................................8-6<br />
8-7 Power-On Timing Specifications..............................................................................................8-12<br />
8-8 Hardware Reset Timing Specifications....................................................................................8-13<br />
8-9 GPIO Reset Timing Specifications ..........................................................................................8-14<br />
8-10Sleep Mode Timing Specifications...........................................................................................8-14<br />
8-11SRAM / ROM / Flash / Synchronous Fast Flash AC Specifications (3.3 V) ............................8-15<br />
8-12Variable Latency I/O Interface AC Specifications (3.3 V) ........................................................8-16<br />
8-13Card Interface (PCMCIA or Compact Flash) AC Specifications (3.3 V) ..................................8-16<br />
8-14Synchronous Memory Interface AC Specifications (3.3 V)......................................................8-17<br />
8-15SRAM / ROM / Flash / Synchronous Fast Flash AC Specifications (2.5 V) ............................8-18<br />
8-16Variable Latency I/O Interface AC Specifications (2.5 V) ........................................................8-19<br />
8-17Card Interface (PCMCIA or Compact Flash) AC Specifications (2.5 V) ..................................8-19<br />
8-18Synchronous Memory Interface AC Specifications (2.5 V)......................................................8-20<br />
<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide<br />
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Contents<br />
viii<br />
<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide
Introduction 1<br />
Table 1-1.<br />
Revision History<br />
Date Revision Description<br />
Nov 2000 0.1 Initial Release: RS-<strong>Intel</strong> ® <strong>PXA250</strong> Platform Design Guide<br />
Nov 2000 0.2 Second draft<br />
Jan 2001 0.3<br />
Corrected name of FFRTS in Table 1-4.<br />
Reorganized Table 1-4 <strong>and</strong> Table 1-5 for readability.<br />
May 2001 0.6 Added reference to <strong>PXA210</strong> <strong>and</strong> performed editorial clean-up.<br />
February 2002 1.0 Public Release<br />
This document presents design recommendations, board schematics, <strong>and</strong> debug recommendations<br />
for the <strong>Intel</strong>® <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> applications processors. The <strong>PXA250</strong> applications processor<br />
is the 32-bit version of the device <strong>and</strong> the <strong>PXA210</strong> applications processor is the 16-bit version.<br />
This document refers to both versions as the applications processor. When differences are<br />
discussed, the specific applications processor is called by name.<br />
The guidelines presented in this document ensure maximum flexibility for board designers, while<br />
reducing the risk of board-related issues. Use the schematics in Appendix B, “Example Form<br />
Factor Reference Design Schematic Diagrams” as a reference for your own design. While the<br />
included schematics cover a specific design, the core schematics remain the same for most<br />
<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> applications processor based platforms. Consult the debug<br />
recommendations when debugging an applications processor based system. To ensure the correct<br />
implementation of the debug port (refer to Section 9 for more information), these debug<br />
recommendations should be understood before completing board design, in addition to other debug<br />
features.<br />
Table 1-2. Related Documentation<br />
Document Title<br />
Order Number<br />
<strong>Intel</strong>® <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Developer’s Manual 278522<br />
<strong>Intel</strong>® <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Electrical, Mechanical,<br />
<strong>and</strong> Thermal Specification<br />
278524<br />
1.1 Functional Overview<br />
The <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> applications processors are the first integrated-system-on-a-chip design<br />
based on the <strong>Intel</strong>® XScale microarchitecture. The <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> applications<br />
processors integrate the <strong>Intel</strong>® XScale microarchitecture core with many peripherals to let you<br />
design products for the h<strong>and</strong>held market.<br />
Figure 1-1 on page 1-2 is a block diagram of the applications processor.<br />
<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide 1-1
Introduction<br />
s<br />
Figure 1-1. <strong>Applications</strong> Processor Block Diagram<br />
RTC<br />
OS Timer<br />
PWM(2)<br />
Color or<br />
Grayscale<br />
LCD<br />
Controller<br />
Memory<br />
Controller<br />
General Purpose I/O<br />
Int.<br />
Controller<br />
Clocks &<br />
Power Man.<br />
I 2 S<br />
I 2 C<br />
AC97<br />
UART1<br />
UART2<br />
Slow IrDA<br />
Fast IrDA<br />
Peripheral Bus<br />
DMA Controller<br />
<strong>and</strong> Bridge<br />
System Bus<br />
Megacell<br />
Core<br />
Variable<br />
Latency I/O<br />
Control<br />
PCMCIA<br />
& CF<br />
Control<br />
Dynamic<br />
Memory<br />
Control<br />
Static<br />
Memory<br />
Control<br />
ASIC<br />
XCVR<br />
SDRAM/<br />
SMROM<br />
4 banks<br />
ROM/<br />
Flash/<br />
SRAM<br />
4 banks<br />
Socket 0<br />
Socket 1<br />
SSP<br />
USB<br />
Client<br />
MMC<br />
3.6864<br />
MHz<br />
Osc<br />
32.768<br />
KHz<br />
Osc<br />
A8651-01<br />
The <strong>PXA250</strong> applications processor package is: 256 pin, 17x17 mBGA – 32-bit functionality. The<br />
<strong>PXA210</strong> applications processor package is: 225 pin, 13x13 MMAP – 16-bit functionality, a subset<br />
of the <strong>PXA250</strong> applications processor feature set.<br />
Section 1.2.1, “Package Introduction” contains a breakdown of the features supported by the two<br />
different packages.<br />
1.2 Package Information<br />
This section describes the package types, pinouts, <strong>and</strong> signal descriptions.<br />
1.2.1 Package Introduction<br />
Package features of the <strong>PXA250</strong> applications processor are:<br />
• Core frequencies supported - 100 MHz - 400 MHz<br />
1-2 <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide
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• System memory interface<br />
—100MHz SDRAM<br />
— 4 MB to 256 MB of SDRAM memory<br />
— Support for 16, 64, 128, or 256 Mbit DRAM technologies<br />
— 4 Banks of SDRAM, each supporting 64 MB of memory<br />
— Clock enable (1 CKE pin is provided to put the entire SDRAM interface into self refresh)<br />
— Supports as many as 6 static memory devices (SRAM, Flash, or VLIO)<br />
• PCMCIA/Compact Flash card control pins<br />
• LCD Controller pins<br />
• Full Function UART<br />
• Bluetooth UART<br />
• MMC Controller pins<br />
• SSP Pins<br />
• USB Client Pins<br />
• AC’97 Controller Pins<br />
• St<strong>and</strong>ard UART Pins<br />
• I 2 C Controller pins<br />
• PWM pins<br />
• 15 dedicated GPIOs pins<br />
• Integrated JTAG support<br />
Package features of the <strong>PXA210</strong> applications processor are:<br />
• Core frequencies supported – 100 MHz, 133 MHz, 200 MHzSystem memory interface<br />
— 100 MHz SDRAM, 16-bit only<br />
— 2 MB to 128 MB of SDRAM memory<br />
— Support for 16, 64, 128, or 256 Mbit DRAM technologies<br />
— 2 Banks of SDRAM, each supporting 64 MB of memory<br />
— Supports as many as 6 static memory devices (SRAM, Flash, or VLIO)<br />
• Clock enable (1 CKE pin is provided to put the entire SDRAM interface into self refresh)<br />
• LCD Controller pins<br />
• Bluetooth UART<br />
• MMC Controller pins<br />
• SSP Pins<br />
• USB Client Pins<br />
• AC97 Controller Pins<br />
• St<strong>and</strong>ard UART Pins<br />
<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide 1-3
Introduction<br />
• I 2 C Controller pins<br />
• PWM pins<br />
• 2 dedicated GPIOs pins<br />
• Integrated JTAG support<br />
1.2.2 Signal Pin Descriptions<br />
Table 1-3 defines the signal descriptions for the applications processor.<br />
Table 1-3. Signal Pin Descriptions (Sheet 1 of 7)<br />
Name Type Description<br />
Memory Controller Pins<br />
MA[25:0] OCZ Memory address bus. This bus signals the address requested for memory accesses.<br />
MD[15:0] ICOCZ Memory data bus. D[15:0] are used for 16-bit <strong>and</strong> 32-bit data modes.<br />
MD[31:16]<br />
nOE<br />
ICOCZ<br />
OCZ<br />
Memory data bus. D[31:16]: These signals are the upper memory data bus address<br />
bits.<br />
See Note [1]<br />
Memory output enable. Connect this signal to the output enables of memory devices<br />
to control their data bus drivers.<br />
nWE OCZ Memory write enable. Connect this signal to the write enables of memory devices.<br />
nSDCS[3:0]<br />
DQM[3:0]<br />
nSDRAS<br />
nSDCAS<br />
SDCKE[0]<br />
SDCKE[1]<br />
SDCLK[2:0]<br />
OCZ<br />
OCZ<br />
OCZ<br />
OCZ<br />
OC<br />
OC<br />
OCZ<br />
SDRAM CS for banks 0 through 3. Connect these signals to the chip select (CS) pins<br />
for SDRAM. nSDCS0 is a three-state signal, while nSDCS1-3 are not three-state.<br />
SDRAM DQM for data bytes 0 through 3. Connect these signals to the data output<br />
mask enables (DQM) for SDRAM.<br />
SDRAM RAS. Connect this signal to the row address strobe (RAS) pins for all banks<br />
of SDRAM.<br />
SDRAM CAS. Connect this signal to the column address strobe (CAS) pins for all<br />
banks of SDRAM.<br />
SDRAM <strong>and</strong>/or Synchronous Static Memory/SDRAM-like synchronous Flash clock<br />
enable clock enable.<br />
ConnectSDCKE[0] to the CKE pins of SMROM <strong>and</strong> SDRAM-timing Synchronous<br />
Flash.<br />
The memory controller provides control register bits for deassertion of each SDCKE<br />
pin.<br />
SDRAM device clock enable.<br />
Connect SDCKE[1] to the clock enable pins of SDRAM. It is de-asserted (held low)<br />
during sleep. SDCKE[1] is always deasserted upon reset.<br />
The memory controller provides control register bits for deassertion of each SDCKE<br />
pin.<br />
See Note [1]<br />
Use these clocks to clock synchronous memory devices:<br />
SDCLK0 - connected to either SMROM or synchronous Flash devices<br />
SDCLK1 - connected to SDRAM banks 0/1<br />
SDCLK2 - connected to SDRAM banks 2/3<br />
See Note [1]<br />
1-4 <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide
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Table 1-3. Signal Pin Descriptions (Sheet 2 of 7)<br />
Name Type Description<br />
nCS[5]/<br />
GPIO[33]<br />
nCS[4]/<br />
GPIO[80]<br />
nCS[3]/<br />
GPIO[79]<br />
nCS[2]/<br />
GPIO[78]<br />
nCS[1]/<br />
GPIO[15]<br />
nCS[0]<br />
ICOCZ<br />
ICOCZ<br />
ICOCZ<br />
ICOCZ<br />
ICOCZ<br />
ICOCZ<br />
Static chip selects. These signals are chip selects to static memory devices such as<br />
ROM <strong>and</strong> Flash. They are individually programmable in the memory configuration<br />
registers. nCS[5:3] may be used with variable data latency variable latency I/O<br />
devices.<br />
See Note [2]<br />
Static chip select 0. This is the chip select for the boot memory. nCS[0] is a dedicated<br />
pin.<br />
RD/nWR OCZ Read/Write for static interface. Intended for use as a steering signal for buffering logic<br />
RDY/<br />
GPIO[18]<br />
MBGNT/GP[13]<br />
MBREQ/GP[14]<br />
ICOCZ<br />
ICOCZ<br />
ICOCZ<br />
Variable Latency I/O Ready pin (input)<br />
See Note [2]<br />
Memory Controller grant. (output) Notifies an external device that it has been granted<br />
the system bus.<br />
Memory Controller alternate bus master request. (input) Allows an external device to<br />
request the system bus from the Memory Controller.<br />
PCMCIA/CF Control Pins - <strong>PXA250</strong> <strong>Applications</strong> Processor only<br />
nPOE/ GPIO[48]<br />
nPWE/<br />
GPIO[49]<br />
nPIOW/<br />
GPIO[51]<br />
nPIOR/<br />
GPIO[50]<br />
nPCE[2:1]/<br />
GPIO[53, 52]<br />
nIOIS16/<br />
GPIO[57]<br />
nPWAIT/<br />
GPIO[56]<br />
nPSKTSEL/<br />
GPIO[54]<br />
ICOCZ<br />
ICOCZ<br />
ICOCZ<br />
ICOCZ<br />
ICOCZ<br />
ICOCZ<br />
ICOCZ<br />
ICOCZ<br />
PCMCIA output enable. Output PCMCIA signal that performs reads from memory <strong>and</strong><br />
attribute space.<br />
See Note [2]<br />
PCMCIA write enable. Output signal that performs writes to memory <strong>and</strong> attribute<br />
space.<br />
See Note [2]<br />
PCMCIA I/O write. Output signal that performs write transactions to the PCMCIA I/O<br />
space.<br />
See Note [2]<br />
PCMCIA I/O read. Output signal that performs read transactions from the PCMCIA I/O<br />
space.<br />
See Note [2]<br />
PCMCIA card enable. Output signals that selects a PCMCIA card. Bit one enables the<br />
high byte lane <strong>and</strong> bit zero enables the low byte lane.<br />
See Note [2]<br />
I/O Select 16. Input signal from the PCMCIA card that indicates the current address is<br />
a valid 16 bit wide I/O address.<br />
See Note [2]<br />
PCMCIA wait. Input signal that is driven low by the PCMCIA card to extend the length<br />
of the transfers to/from the applications processor.<br />
See Note [2]<br />
PCMCIA socket select. Output signal used by external steering logic to route control,<br />
address, <strong>and</strong> data signals to one of the two PCMCIA sockets. When PSKTSEL is low,<br />
socket zero is selected. When PSKTSEL is high, socket one is selected. This signal<br />
has the same timing as address.<br />
See Note [2]<br />
<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide 1-5
Introduction<br />
Table 1-3. Signal Pin Descriptions (Sheet 3 of 7)<br />
Name Type Description<br />
nPREG/<br />
GPIO[55]<br />
LCD Controller Pins<br />
L_DD(15:0)/<br />
GPIO[73:58]<br />
L_FCLK/<br />
GPIO[74]<br />
L_LCLK/<br />
GPIO[75]<br />
L_PCLK/<br />
GPIO[76]<br />
L_BIAS/<br />
GPIO[77]<br />
ICOCZ<br />
ICOCZ<br />
ICOCZ<br />
ICOCZ<br />
ICOCZ<br />
ICOCZ<br />
PCMCIA register select. Output signal that indicates the target address is attribute<br />
space, on a memory transaction. This signal has the same timing as address.<br />
See Note [2]<br />
LCD Controller display data<br />
See Note [2]<br />
LCD Frame clock<br />
See Note [2]<br />
LCD Line clock<br />
See Note [2]<br />
LCD pixel clock<br />
See Note [2]<br />
AC Bias Drive<br />
See Note [2]<br />
Full Function UART Pins<br />
FFRXD/<br />
GPIO[34]<br />
FFTXD/<br />
GPIO[39]<br />
FFCTS/<br />
GPIO[35]<br />
FFDCD/<br />
GPIO[36]<br />
FFDSR/<br />
GPIO[37]<br />
FFRI/<br />
GPIO[38]<br />
FFDTR/<br />
GPIO[40]<br />
FFRTS/<br />
GPIO[41]<br />
Bluetooth UART Pins<br />
BTRXD/<br />
GPIO[42]<br />
BTTXD/<br />
GPIO[43]<br />
BTCTS/<br />
GPIO[44]<br />
BTRTS/<br />
GPIO[45]<br />
MMC Controller Pins<br />
ICOCZ<br />
ICOCZ<br />
ICOCZ<br />
ICOCZ<br />
ICOCZ<br />
ICOCZ<br />
ICOCZ<br />
ICOCZ<br />
ICOCZ<br />
ICOCZ<br />
ICOCZ<br />
ICOCZ<br />
Full Function UART Receive pin<br />
See Note [2]<br />
Full Function UART Transmit pin<br />
See Note [2]<br />
Full Function UART Clear-to-Send pin<br />
See Note [2]<br />
Full Function UART Data-Carrier-Detect Pin<br />
See Note [2]<br />
Full Function UART Data-Set-Ready Pin:<br />
See Note [2]<br />
Full Function UART Ring Indicator Pin<br />
See Note [2]<br />
Full Function UART Data-Terminal-Ready pin<br />
See Note [2]<br />
Full Function UART Ready-to-Send pin<br />
See Note [2]<br />
Bluetooth UART Receive pin<br />
See Note [2]<br />
Bluetooth UART Transmit pin<br />
See Note [2]<br />
Bluetooth UART Clear-to-Send pin<br />
See Note [2]<br />
Bluetooth UART Data-Terminal-Ready pin<br />
See Note [2]<br />
MMCMD ICOCZ Multimedia Card Comm<strong>and</strong> pin (I/O)<br />
1-6 <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide
Introduction<br />
Table 1-3. Signal Pin Descriptions (Sheet 4 of 7)<br />
Name Type Description<br />
MMDAT ICOCZ Multimedia Card Data Pin (I/O)<br />
MMCCLK/GP[6] ICOCZ MMC clock. (output) Clock signal for the MMC Controller.<br />
MMCCS0/GP[8] ICOCZ MMC chip select 0. (output) Chip select 0 for the MMC Controller.<br />
MMCCS1/GP[9] ICOCZ MMC chip select 1. (output) Chip select 1 for the MMC Controller.<br />
SSP Pins<br />
SSPSCLK/<br />
GPIO[23]<br />
SSPSFRM/<br />
GPIO[24]<br />
SSPTXD/<br />
GPIO[25]<br />
SSPRXD/<br />
GPIO[26]<br />
SSPEXTCLK/<br />
GPIO[27]<br />
USB Client Pins<br />
ICOCZ<br />
ICOCZ<br />
ICOCZ<br />
ICOCZ<br />
ICOCZ<br />
Synchronous Serial Port Clock (output)<br />
See Note [2]<br />
Synchronous serial port Frame Signal (output)<br />
See Note [2]<br />
Synchronous serial port transmit (output)<br />
See Note [2]<br />
Synchronous serial port receive (input)<br />
See Note [2]<br />
Synchronous Serial port external clock (input)<br />
See Note [2]<br />
USB_P IAOA USB Client port positive Pin of differential pair.<br />
USB_N IAOA USB Client port negative Pin of differential pair.<br />
AC97 Controller Pins<br />
BITCLK/<br />
GPIO[28]<br />
SDATA_IN0/<br />
GPIO[29]<br />
SDATA_IN1/<br />
GPIO[32]<br />
SDATA_OUT/<br />
GPIO[30]<br />
SYNC/<br />
GPIO[31]<br />
nACRESET<br />
ICOCZ<br />
ICOCZ<br />
ICOCZ<br />
ICOCZ<br />
ICOCZ<br />
OC<br />
AC97 Audio Port bit clock (output)<br />
See Note [2]<br />
AC97 Audio Port data in (input)<br />
See Note [2]<br />
AC97 Audio Port data in (input)<br />
See Note [2]<br />
AC97 Audio Port data out (output)<br />
See Note [2]<br />
AC97 Audio Port sync signal (output)<br />
See Note [2]<br />
AC97 Audio Port reset signal (output)<br />
This pin is a dedicated output.<br />
St<strong>and</strong>ard UART <strong>and</strong> ICP Pins<br />
IRRXD/<br />
GPIO[46]<br />
IRTXD/<br />
GPIO[47]<br />
I 2 C Controller Pins<br />
SCL<br />
ICOCZ<br />
ICOCZ<br />
ICOCZ<br />
IrDA Receive signal (input).<br />
See Note [2]<br />
IrDA Transmit signal (output).<br />
Transmit pin for both the SIR <strong>and</strong> FIR functions.<br />
See Note [2]<br />
I2C clock (Bidirectional)<br />
Bidirectional signal. When it is driving, it functions as an open collector device <strong>and</strong><br />
requires a pull up resistor. As an input, it expects st<strong>and</strong>ard CMOS levels.<br />
<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide 1-7
Introduction<br />
Table 1-3. Signal Pin Descriptions (Sheet 5 of 7)<br />
Name Type Description<br />
SDA<br />
PWM Pins<br />
PWM[1:0]/<br />
GPIO[17,16]<br />
Dedicated GPIO Pins<br />
GPIO[1:0]<br />
GPIO[14:2])<br />
GPIO[22:21]<br />
Crystal Pins<br />
ICOCZ<br />
ICOCZ<br />
ICOCZ<br />
ICOCZ<br />
ICOCZ<br />
I2C Data signal (bidirectional).<br />
Bidirectional signal. When it is driving, it functions as an open collector device <strong>and</strong><br />
requires a pull up resistor. As an input, it expects st<strong>and</strong>ard CMOS levels.<br />
Pulse Width Modulation channels 0 <strong>and</strong> 1 (outputs)<br />
See Note [2]<br />
General Purpose I/O: These two pins are contained in both the <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong><br />
applications processors. They are preconfigured at a hard reset (nRESET) as wakeup<br />
sources for both rising <strong>and</strong> falling edge detects.<br />
These GPIOs do not have alternate functions <strong>and</strong> are intended to be used as the main<br />
external sleep wakeup stimulus.<br />
General Purpose I/O<br />
See Note [1]<br />
See Note [2]<br />
General Purpose I/O<br />
Additional general purpose I/O pins.<br />
PXTAL IA Input connection for 3.6864 Mhz crystal<br />
PEXTAL OA Output connection for 3.6864 Mhz crystal<br />
TXTAL IA Input connection for 32.768 khz crystal<br />
TEXTAL OA Output connection for 32.768 khz crystal<br />
48MHz/GP[7] ICOCZ 48 MHz clock. (output) Peripheral clock output derived from the PLL.<br />
RTCCLK/GP[10] ICOCZ Real time clock. (output) HZ output derived from the 32kHz or 3.6864MHz output.<br />
3.6MHz/GP[11] ICOCZ 3.6864 MHz clock. (output) Output from 3.6864 MHz oscillator.<br />
32kHz/GP[12] ICOCZ 32 kHz clock. (output) Output from the 32 kHz oscillator.<br />
Miscellaneous Pins<br />
BOOT_SEL<br />
[2:0]<br />
PWR_EN<br />
nBATT_FAULT<br />
IC<br />
OCZ<br />
IC<br />
Boot programming select pins. These pins are sampled to indicate the type of boot<br />
device present per the following table;<br />
BOOT_SEL[2:0] Description<br />
000Asynchronous 32-bit ROM<br />
001Asynchronous 16-bit ROM<br />
100One 32-bit SMROM<br />
101One 16 bit SMROM<br />
110Two 16 bit SMROMs (32 bit bus)<br />
111Reserved<br />
Power Enable. Active high Output.<br />
PWR_EN enables the external power supply. Negating it signals the power supply<br />
that the system is going into sleep mode <strong>and</strong> that the VDD power supply should be<br />
removed.<br />
Battery Fault. Active low input.<br />
The assertion of nBATT_FAULT causes the applications processor to enter Sleep<br />
Mode.The applications processor will not recognize a wakeup event while this signal<br />
is asserted. Use nBATT_FAULT signal to flag a critical power failure, such as the main<br />
battery being removed. Minimum assertion time for nBATT_FAULT is 1ms.<br />
1-8 <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide
Introduction<br />
Table 1-3. Signal Pin Descriptions (Sheet 6 of 7)<br />
Name Type Description<br />
nVDD_FAULT<br />
nRESET<br />
nRESET_OUT<br />
JTAG Pins<br />
nTRST<br />
IC<br />
IC<br />
OC<br />
IC<br />
VDD Fault. Active low input.<br />
nVDD_FAULT causes the applications processor to enter Sleep Mode. nVDD_FAULT<br />
is ignored after a wakeup event until the power supply timer completes (approximately<br />
10 ms). use the nVDD_FAULT signal to flag a low battery. Minimum assertion time for<br />
nVDD_FAULT is 1 ms.<br />
Hard reset. Active low input.<br />
nRESET is a level sensitive input which starts the processor from a known address. A<br />
LOW level causes the current instruction to terminate abnormally, <strong>and</strong> all on-chip state<br />
to be reset. When nRESET is driven HIGH, the processor re-starts from address 0.<br />
nRESET must remain LOW until the power supply is stable <strong>and</strong> the internal 3.6864<br />
MHz oscillator has come up to speed. While nRESET is LOW the processor performs<br />
idle cycles.<br />
Reset Out. Active low output.<br />
This signal is asserted when nRESET is asserted <strong>and</strong> de-asserts after nRESET is<br />
negated but before the first instruction fetch. nRESET_OUT is also asserted for “soft”<br />
reset events (sleep, watchdog reset, GPIO reset)<br />
JTAG Test Interface Reset. Resets the JTAG/Debug port. If JTAG/Debug is used,<br />
drive nTRST from low to high either before or at the same time as nRESET. If JTAG is<br />
not used, nTRST must be either tied to nRESET or tied low. <strong>Intel</strong> recommends that a<br />
JTAG/Debug port be added to all systems for debug <strong>and</strong> download. See Chapter 9 for<br />
details.<br />
TDI IC JTAG test interface data input. Note this pin has an internal pullup resistor.<br />
TDO<br />
OCZ<br />
JTAG test interface data output. Note this pin does NOT have an internal pullup<br />
resistor.<br />
TMS IC JTAG test interface mode select. Note this pin has an internal pullup resistor.<br />
TCK<br />
IC<br />
JTAG test interface reference Clock. TCK is the reference clock for all transfers on the<br />
JTAG test interface.<br />
NOTE: This pin needs an external pulldown resistor.<br />
TEST IC Test Mode. You should ground this pin. This pin is for manufacturing purposes only.<br />
TESTCLK IC Test Clock. Use this pin for test purposes only. An end user should ground this pin.<br />
Power <strong>and</strong> Ground Pins<br />
VCC<br />
VSS<br />
SUP<br />
SUP<br />
Positive supply for the internal logic. Connect this supply to the low voltage (.85 -<br />
1.65v) supply on the PCB.<br />
Ground supply for the internal logic. Connect these pins to the common ground plane<br />
on the PCB.<br />
PLL_VCC SUP Positive supply for PLLs <strong>and</strong> oscillators must be shorted to VCC.<br />
PLL_VSS SUP Ground supply for the PLL. Must be connected to common ground plane on the PCB.<br />
VCCQ<br />
VSSQ<br />
VCCN<br />
SUP<br />
SUP<br />
SUP<br />
Positive supply for all CMOS I/O except memory bus <strong>and</strong> PCMCIA pins. Connect<br />
these pins to the common 3.3v supply on the PCB.<br />
Ground supply for all CMOS I/O except memory bus <strong>and</strong> PCMCIA pins. Connect<br />
these pins to the common ground plane on the PCB.<br />
Positive supply for memory bus <strong>and</strong> PCMCIA pins. Connect these pins to the common<br />
3.3 V or 2.5 V supply on the PCB.<br />
<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide 1-9
Introduction<br />
VSSN<br />
Table 1-3. Signal Pin Descriptions (Sheet 7 of 7)<br />
Name Type Description<br />
SUP<br />
Ground supply for memory bus <strong>and</strong> PCMCIA pins. Connect these pins to the common<br />
ground plane on the PCB.<br />
BATT_VCC SUP<br />
Backup battery connection. Connect this pin to the backup battery supply. If a backup<br />
battery is not required then this pin may be connected to the common 3.3v supply on<br />
the PCB.<br />
NOTES:<br />
1. Not pinned out for the <strong>PXA210</strong> applications processor.<br />
2. GPIO Reset Operation: After any reset, these pins are configured as GPIO inputs by default. The input buffers for these pins<br />
are disabled to prevent current drain <strong>and</strong> must be enabled prior to use by clearing the Read Disable Hold (RDH) bit.<br />
To use a GPIO pin as an alternate function, follow this sequence:<br />
1) Program the pin to the desired direction (input or output) using the GPIO Pin Direction Registers (GPDR).<br />
2) Enable the input buffer by clearing the RDH bit, described above.<br />
3) If needed, select the desired alternate function by programming the proper bits in the GPIO Alternate Function<br />
Register (GAFR).<br />
1-10 <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide
Introduction<br />
Figure 1-2. <strong>PXA250</strong> <strong>Applications</strong> Processor<br />
<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide 1-11
Introduction<br />
Table 1-4. <strong>PXA250</strong> <strong>Applications</strong> Processor Pinout — Ballpad Number Order (Sheet 1 of 3)<br />
Ball # Signal Ball # Signal Ball # Signal<br />
A1 VCCN F7 GPIO[10] L13 GPIO[2]<br />
A2 L_DD[13]/GPIO[71] F8 FFRTS/GPIO[41] L14 VSSQ<br />
A3 L_DD[12]/GPIO[70] F9 SSPSCLK/GPIO[23] L15 TEXTAL<br />
A4 L_DD[11]/GPIO[69] F10 FFDTR/GPIO[40] L16 TXTAL<br />
A5 L_DD[9]/GPIO[67] F11 VCC M1 MA[14]<br />
A6 L_DD[7]/GPIO[65] F12 GPIO[9] M2 MD[21]<br />
A7 GPIO[11] F13 BOOT_SEL[2] M3 MA[15]<br />
A8 L_BIAS/GPIO[77] F14 GPIO[8] M4 VCCN<br />
A9 SSPRXD/GPIO[26] F15 VSSQ M5 MD[1]<br />
A10 SDATA_OUT/GPIO[30] F16 VSSQ M6 MD[6]<br />
A11 SDA G1 MA[0] M7 MD[7]<br />
A12 FFDCD/GPIO[36] G2 VSSN M8 DQM[0]<br />
A13 FFRXD/GPIO[34] G3 nSDCS[2] M9 MD[8]<br />
A14 FFCTS/GPIO[35] G4 nWE M10 MD[15]<br />
A15 BTCTS/GPIO[44] G5 nOE M11 BATT_VCC<br />
A16 SDATA_IN1/GPIO[32] G6 nSDCS[1] M12 GPIO[22]<br />
B1 DQM[1] G7 VCC M13 nPREG/GPIO[55]<br />
B2 DQM[2] G8 VSSQ M14 VCCN<br />
B3 L_DD[15]/GPIO[73] G9 VCC M15 VSSN<br />
B4 GPIO[14] G10 VSSQ M16 nIOIS16/GPIO[57]<br />
B5 GPIO[13] G11 TESTCLK N1 MD[22]<br />
B6 GPIO[12] G12 TEST N2 VSSN<br />
B7 L_DD[3]/GPIO[61] G13 BOOT_SEL[1] N3 MA[16]<br />
B8 L_PCLK/GPIO[76] G14 VCCQ N4 MD[0]<br />
B9 SSPEXTCLK/GPIO[27] G15 GPIO[7] N5 VCCN<br />
B10 FFRI/GPIO[38] G16 BOOT_SEL[0] N6 MD[4]<br />
B11 FFDSR/GPIO[37] H1 MA[2] N7 VCCN<br />
B12 USB_N H2 MA[1] N8 nCS[0]<br />
B13 BTRXD/GPIO[42] H3 MD[16] N9 VCCN<br />
B14 BTRTS/GPIO[45] H4 VCCN N10 MD[13]<br />
B15 IRRXD/GPIO[46] H5 MD[17] N11 VCCN<br />
B16 MMDAT H6 MA[3] N12 DREQ[0]/GPIO[20]<br />
C1 RDY/GPIO[18] H7 VSSQ N13 VCCN<br />
C2 VSSN H8 VSS N14 DREQ[1]/GPIO[19]<br />
C3 L_DD[14]/GPIO[72] H9 VSS N15 GPIO[21]<br />
C4 VSSQ H10 VCC N16 nPWAIT/GPIO[56]<br />
C5 L_DD[8]/GPIO[66] H11 nTRST P1 MA[17]<br />
1-12 <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide
Introduction<br />
Table 1-4. <strong>PXA250</strong> <strong>Applications</strong> Processor Pinout — Ballpad Number Order (Sheet 2 of 3)<br />
Ball # Signal Ball # Signal Ball # Signal<br />
C6 VCCQ H12 TCK P2 MA[19]<br />
C7 L_DD[2]/GPIO[60] H13 TMS P3 VCCN<br />
C8 VSSQ H14 GPIO[6] P4 MA[25]<br />
C9 BITCLK/GPIO[28] H15 TDI P5 MA[23]<br />
C10 VCCQ H16 TDO P6 MD[24]<br />
C11 VSSQ J1 MA[7] P7 MD[26]<br />
C12 USB_P J2 VSSN P8 MD[27]<br />
C13 VCCQ J3 MA[6] P9 nCS[2]/GPIO[78]<br />
C14 VSSQ J4 MD[18] P10 MD[29]<br />
C15 IRTXD/GPIO[47] J5 MA[5] P11 MD[12]<br />
C16 VSS J6 MA[4] P12 MD[31]<br />
D1 SDCLK[2] J7 VCC P13 nPOE/GPIO[48]<br />
D2 SDCLK[0] J8 VSS P14 nPCE[1]/GPIO[52]<br />
D3 RDnWR J9 VSS P15 VSSN<br />
D4 VCCN J10 VSSQ P16 nPSKTSEL/GPIO[54]<br />
D5 L_DD[10]/GPIO[68] J11 GPIO[5] R1 MA[18]<br />
D6 L_DD[5]/GPIO[63] J12 GPIO[4] R2 VSSN<br />
D7 L_DD[1]/GPIO[59] J13 nRESET R3 MA[20]<br />
D8 L_LCLK/GPIO[75] J14 VSSQ R4 VSSN<br />
D9 SSPTXD/GPIO[25] J15 PLL_VCC R5 MA[22]<br />
D10 nACRESET J16 PLL_VSS R6 VSSN<br />
D11 SCL K1 MA[8] R7 MD[25]<br />
D12 PWM[1]/GPIO[17] K2 MA[9] R8 VSSN<br />
D13 BTTXD/GPIO[43] K3 MD[19] R9 MD[10]<br />
D14 MMCMD K4 VCCN R10 VSSN<br />
D15 VCCQ K5 MA[10] R11 MD[30]<br />
D16 VSSQ K6 MA[11] R12 VSSN<br />
E1 nSDRAS K7 VSSQ R13 nCS[4]/GPIO[80]<br />
E2 VSSN K8 VCC R14 VSSN<br />
E3 SDCKE[1] K9 VSSQ R15 nPIOW/GPIO[51]<br />
E4 SDCKE[0] K10 VCC R16 nPCE[2]/GPIO[53]<br />
E5 L_DD[6]/GPIO[64] K11 nRESET_OUT T1 VSS<br />
E6 L_DD[4]/GPIO[62] K12 nBATT_FAULT T2 VCCN<br />
E7 L_DD[0]/GPIO[58] K13 nVDD_FAULT T3 MD[23]<br />
E8 L_FCLK/GPIO[74] K14 GPIO[3] T4 MA[21]<br />
E9 SSPSFRM/GPIO[24] K15 PXTAL T5 MA[24]<br />
E10 SDATA_IN0/GPIO[29] K16 PEXTAL T6 MD[3]<br />
E11 SYNC/GPIO[31] L1 MA[12] T7 MD[5]<br />
<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide 1-13
Introduction<br />
Table 1-4. <strong>PXA250</strong> <strong>Applications</strong> Processor Pinout — Ballpad Number Order (Sheet 3 of 3)<br />
Ball # Signal Ball # Signal Ball # Signal<br />
E12 PWM[0]/GPIO[16] L2 VSSN T8 nCS[1]/GPIO[15]<br />
E13 FFTXD/GPIO[39] L3 MA[13] T9 nCS[3]/GPIO[79]<br />
E14 VCCQ L4 MD[20] T10 MD[9]<br />
E15 VSSQ L5 MD[2] T11 MD[11]<br />
E16 VSSQ L6 VCC T12 MD[14]<br />
F1 nSDCS[0] L7 DQM[3] T13 nCS[5]/GPIO[33]<br />
F2 nSDCS[3] L8 MD[28] T14 nPWE/GPIO[49]<br />
F3 nSDCAS L9 VCC T15 nPIOR/GPIO[50]<br />
F4 VCCN L10 GPIO[0] T16 VCCN<br />
F5 SDCLK[1] L11 PWR_EN<br />
F6 VSSQ L12 GPIO[1]<br />
1-14 <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide
Introduction<br />
Figure 1-3. <strong>PXA210</strong> <strong>Applications</strong> Processor<br />
φ<br />
<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide 1-15
Introduction<br />
Table 1-5. <strong>PXA210</strong> <strong>Applications</strong> Processor Pinout — Ballpad Number Order (Sheet 1 of 2)<br />
Ball # Signal Ball # Signal Ball # Signal<br />
A1 DQM[1] F1 VSSN L1 VSSN<br />
A2 L_DD[14]/GPIO[72] F2 nSDCS[0] L2 VCCN<br />
A3 L_DD[10]/GPIO[68] F3 nSDRAS L3 MA[12]<br />
A4 VSSQ F4 nSDCS[1] L4 MA[13]<br />
A5 L_DD[6]/GPIO[64] F5 VCC L5 MA[11]<br />
A6 L_DD[2]/GPIO[60] F6 L_DD[8]/GPIO[66] L6 VSSQ<br />
A7 L_LCLK/GPIO[75] F7 L_FCLK/GPIO[74] L7 MD[2]<br />
A8 SPPSCLK/GPIO[23] F8 SSPRXD/GPIO[26] L8 MD[6]<br />
A9 SPPEXTCLK/GPIO[27] F9 VCC L9 VSSN<br />
A10 nACRESET F10 FFTXD/GPIO[39] L10 MD[11]<br />
A11 PWM[1]/GPIO[17] F11 VCC L11 BATT_VCC<br />
A12 VSSQ F12 VSSQ L12 GPIO[54]<br />
A13 FFRXD/GPIO[34] F13 TESTCLK L13 GPIO[55]<br />
A14 BTCTS/GPIO[44] F14 BOOT_SEL[0] L14 GPIO[57]<br />
A15 IRRXD/GPIO[46] F15 TEST L15 GPIO[0]<br />
B1 RDY/GPIO[18] G1 MA[0] M1 MA[14]<br />
B2 VSSN G2 nOE M2 MA[15]<br />
B3 L_DD[13]/GPIO[71] G3 nWE M3 VCCN<br />
B4 L_DD[9]/GPIO[67] G4 VCCN M4 MA[16]<br />
B5 VSSQ G5 VSSN M5 VCCN<br />
B6 L_DD[3]/GPIO[61] G6 RDnWR M6 VSSN<br />
B7 L_PCLK/GPIO[76] G7 VSS M7 MD[3]<br />
B8 VSSQ G8 VSS M8 MD[7]<br />
B9 BITCLK/GPIO[28] G9 VSS M9 nCS[1]/GPIO[15]<br />
B10 SDA G10 BTRXD/GPIO[42] M10 MD[10]<br />
B11 VSSQ G11 nTRST M11 MD[13]<br />
B12 USB_N G12 TDI M12 GPIO[48]<br />
B13 BTRTS/GPIO[45] G13 TCK M13 GPIO[52]<br />
B14 IRTXD/GPIO[47] G14 TMS M14 VSSN<br />
B15 MMDAT G15 TDO M15 GPIO[56]<br />
C1 SDCKE[1] H1 VCCN N1 VSSN<br />
C2 SDCKE[0] H2 VSSN N2 MA[18]<br />
C3 VCCN H3 MA[2] N3 VSS1<br />
C4 L_DD[12]/GPIO[70] H4 MA[1] N4 MA[22]<br />
C5 VCCQ H5 VCC N5 MA[24]<br />
C6 L_DD[4]/GPIO[62] H6 VSSQ N6 VCCN<br />
C7 L_BIAS/GPIO[77] H7 VSS N7 VCC<br />
1-16 <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide
Introduction<br />
Table 1-5. <strong>PXA210</strong> <strong>Applications</strong> Processor Pinout — Ballpad Number Order (Sheet 2 of 2)<br />
Ball # Signal Ball # Signal Ball # Signal<br />
C8 VCCQ H8 VSS N8 VSSN<br />
C9 SDATA_IN0/GPIO[29] H9 VSS N9 DQM[0]<br />
C10 PWM[0]/GPIO[16] H10 VSSQ N10 VCCN<br />
C11 USB_P H11 VCC N11 MD[12]<br />
C12 BTTXD/GPIO[43] H12 VSSQ N12 VSSN<br />
C13 VSSQ H13 VCC N13 nCS[5]/GPIO[33]<br />
C14 VSS H14 PLL_VCC N14 GPIO[53]<br />
C15 VCCQ H15 PLL_VSS N15 VCCN<br />
D1 VCC J1 MA[5] P1 MA[17]<br />
D2 VSSQ J2 MA[6] P2 VSSN<br />
D3 SDCLK[1] J3 VSSN P3 VCCN<br />
D4 L_DD[15]/GPIO[73] J4 MA[4] P4 MA[23]<br />
D5 VCC J5 MA[3] P5 MD[0]<br />
D6 L_DD[5]/GPIO[63] J6 VSSQ P6 VSSN<br />
D7 L_DD[0]/GPIO[58] J7 VSS1 P7 MD[4]<br />
D8 SPPSFRM/GPIO[24] J8 VSS1 P8 VCCN<br />
D9 SDATA_OUT/GPIO[30] J9 VSS1 P9 nCS[2]/GPIO[78]<br />
D10 SCL J10 VSSQ P10 MD[8]<br />
D11 SDATA_IN1/GPIO[32] J11 nRESET P11 VCCn<br />
D12 BOOT_SEL[1] J12 nRESET_OUT P12 MD[15]<br />
D13 VSSQ J13 PWR_EN P13 VCCN<br />
D14 VSSQ J14 nVDD_FAULT P14 GPIO[50]<br />
D15 VSSQ J15 nBATT_FAULT P15 VSSQ<br />
E1 nSDCAS K1 MA[8] R1 MA[19]<br />
E2 VCCN K2 MA[9] R2 MA[20]<br />
E3 VSSN K3 MA[10] R3 MA[21]<br />
E4 SDCLK[0] K4 MA[7] R4 MA[25]<br />
E5 L_DD[11]/GPIO[69] K5 VCCN R5 MD[1]<br />
E6 L_DD[7]/GPIO[65] K6 VCC R6 VCCN<br />
E7 L_DD[1]/GPIO[59] K7 VSSQ R7 MD[5]<br />
E8 SSPTXD/GPIO[25] K8 VCC R8 nCS[0]<br />
E9 SYNC/GPIO[31] K9 VSSQ R9 nCS[3]/GPIO[79]<br />
E10 VCCQ K10 VCC R10 MD[9]<br />
E11 MMCMD K11 GPIO[1] R11 VSSN<br />
E12 VCCQ K12 TEXTAL R12 MD[14]<br />
E13 VSSQ K13 TXTAL R13 nCS[4]/GPIO[80]<br />
E14 VSSQ K14 PEXTAL R14 nPWE/GPIO[49]<br />
E15 BOOT_SEL[2] K15 PXTAL R15 GPIO[51]<br />
<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide 1-17
Introduction<br />
1-18 <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide
System Memory Interface 2<br />
This section is the design guidelines for the system memory interface.<br />
2.1 Overview<br />
The external memory bus interface for the applications processor supports:<br />
• 100 MHz SDRAM at 3.3 V<br />
• 100 MHz SDRAM at 2.5 V<br />
• Synchronous <strong>and</strong> asynchronous Burst mode <strong>and</strong> Page mode Flash<br />
• Synchronous Mask ROM (SMROM)<br />
• Page Mode ROM<br />
• SRAM<br />
• SRAM-like Variable Latency I/O (VLIO)<br />
• PCMCIA expansion memory<br />
• Compact Flash<br />
Use the memory interface configuration registers to program the memory types. Refer to<br />
Figure 1-1, “<strong>Applications</strong> Processor Block Diagram” on page 1-2 for the block diagram of the<br />
Memory Controller configuration. Refer to Figure 2-1, “Memory Address Map” on page 2-3 for<br />
the applications processor memory map. Refer to Table 2-3, “Normal Mode Memory Address<br />
Mapping” on page 2-6 for alternate mode address mapping.<br />
<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide 2-1
System Memory Interface<br />
Figure 2-1. General Memory Interface Configuration<br />
nSDCS<br />
nSDCS<br />
SDCLK, SDCKE<br />
nSDCS<br />
nSDCS<br />
SDCLK, SDCKE<br />
SDRAM Partition 0<br />
SDRAM Partition 1<br />
SDRAM Partition 2<br />
SDRAM Partition 3<br />
SDRAM Memory Interface<br />
Up to 4 partitions of SDRAM<br />
memory (16- or 32-bit wide)<br />
DQM<br />
nSDRAS, nSDCAS<br />
<strong>PXA250</strong><br />
Memory<br />
Controller<br />
Interface<br />
MD<br />
MA<br />
Card Control<br />
Buffers <strong>and</strong><br />
Transceivers<br />
Card Memory Interface<br />
Up to 2-socket support.<br />
Requires some<br />
external buffering.<br />
nCS<br />
nCS<br />
nCS<br />
SDCLK, SDCKE<br />
Static Bank 0<br />
Static Bank 1<br />
Static Bank 2<br />
Static Memory or<br />
Variable Latency I/O Interface<br />
Up to 6 banks of ROM, Flash,<br />
SRAM, Variable Latency I/O,<br />
(16- or 32-bit wide)<br />
NOTE:<br />
Static Bank 0 must be populated by<br />
“bootable” memory<br />
nCS<br />
nCS<br />
nCS<br />
RDY<br />
Static Bank 3<br />
Static Bank 4<br />
Static Bank 5<br />
Synchronous Static Memory Interface<br />
Up to 4 banks of synchronous<br />
static memory (nCS).<br />
(16- or 32-bit wide)<br />
NOTE:<br />
Static Bank 0 must be populated by<br />
“bootable” memory<br />
2-2 <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide
System Memory Interface<br />
Table 2-1. Memory Address Map<br />
0x6000 0000 Reserved Address Space<br />
0x5C00 0000 Reserved Address Space<br />
0x5800 0000 Reserved Address Space<br />
0x5400 0000 Reserved Address Space<br />
0x5000 0000 Reserved Address Space<br />
0x4C00 0000 Reserved Address Space<br />
0x4800 0000 Memory Mapped Registers (Memory Ctl)<br />
0x4400 0000 Memory Mapped Registers (LCD)<br />
0x4000 0000 Memory Mapped Registers (Peripherals)<br />
0x3000 0000 PCMCIA/CF – Slot 1<br />
0x2000 0000 PCMCIA/CF – Slot 0<br />
0x1C00 0000 Reserved Address Space<br />
0x1800 0000 Reserved Address Space<br />
0x1400 0000 Static Chip Select 5<br />
0x1000 0000 Static Chip Select 4<br />
0x0C00 0000 Static Chip Select 3<br />
0x0800 0000 Static Chip Select 2<br />
0x0400 0000 Static Chip Select 1<br />
0x0000 0000 Static Chip Select 0<br />
2.2 SDRAM Interface<br />
The applications processor supports an SDRAM interface at a maximum frequency of 100 MHz.<br />
The SDRAM Interface supports four 16-bit or 32-bit wide partitions of SDRAM. Each partition is<br />
allocated 64 MBytes of the internal memory map. However, the actual size of each partition is<br />
dependent on the particular SDRAM configuration used. The four partitions are divided into two<br />
partition pairs: the 0/1 pair <strong>and</strong> the 2/3 pair. Both partitions within a pair (for example, partition 0<br />
<strong>and</strong> partition 1) must be identical in size <strong>and</strong> configuration; however, the two pairs can be different.<br />
For example, the 0/1 pair can be 100 MHz SDRAM on a 32-bit data bus, while the 2/3 pair can be<br />
50 MHz SDRAM on a 16-bit data bus.<br />
Note:<br />
For proper SDRAM operation above 50 MHz, 22 ohm series resistors must be placed on the<br />
memory address lines.<br />
2.3 SDRAM memory wiring diagram<br />
Figure 2-2, “SDRAM Memory System Example” on page 2-4 is a wiring diagram example that<br />
shows a system using 1Mword x 16-bit x 4-bank SDRAM devices for a total of 48 Mbytes. Refer<br />
to Section 2.5, “SDRAM Address Mapping” on page 2-6 to determine the individual SDRAM<br />
component address.<br />
<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide 2-3
System Memory Interface<br />
Figure 2-2. SDRAM Memory System Example<br />
nSDCS(3:0)<br />
nSDRAS, nSDCAS, nWE, CKE(1)<br />
SDCLK(2:1)<br />
MA(23:10)<br />
4Mx16<br />
SDRAM<br />
4Mx16<br />
SDRAM<br />
4Mx16<br />
SDRAM<br />
0<br />
nCS<br />
1<br />
nCS<br />
2<br />
nCS<br />
nRAS<br />
nRAS<br />
nRAS<br />
nCAS<br />
nCAS<br />
nCAS<br />
nWE<br />
nWE<br />
nWE<br />
1<br />
CKE<br />
CLK<br />
1<br />
CKE<br />
CLK<br />
2<br />
CKE<br />
CLK<br />
addr(11:0)<br />
addr(11:0)<br />
addr(11:0)<br />
0<br />
1<br />
BA(1:0)<br />
DQML<br />
DQMH<br />
BA(1:0)<br />
DQML<br />
DQMH<br />
BA(1:0)<br />
DQML<br />
DQMH<br />
15:0<br />
DQ(15:0)<br />
DQ(15:0)<br />
DQ(15:0)<br />
MD(31:0)<br />
DQM(3:0)<br />
4Mx16<br />
SDRAM<br />
4Mx16<br />
SDRAM<br />
4Mx16<br />
SDRAM<br />
0<br />
nCS<br />
1<br />
nCS<br />
2<br />
nCS<br />
nRAS<br />
nRAS<br />
nRAS<br />
nCAS<br />
nCAS<br />
nCAS<br />
nWE<br />
nWE<br />
nWE<br />
31:16<br />
1<br />
2<br />
3<br />
CKE<br />
CLK<br />
addr(11:0)<br />
BA(1:0)<br />
DQML<br />
DQMH<br />
DQ(15:0)<br />
1<br />
CKE<br />
CLK<br />
addr(11:0)<br />
BA(1:0)<br />
DQML<br />
DQMH<br />
DQ(15:0)<br />
2<br />
21:10<br />
23:22<br />
CKE<br />
CLK<br />
addr(11:0)<br />
BA(1:0)<br />
DQML<br />
DQMH<br />
DQ(15:0)<br />
2-4 <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide
.<br />
System Memory Interface<br />
2.4 SDRAM Support<br />
Table 2-2 shows the SDRAM memory types <strong>and</strong> densities that are supported by the applications<br />
processor.<br />
Table 2-2. SDRAM Memory Types Supported by the <strong>Applications</strong> Processor<br />
Partition Size<br />
(Mbyte/Partition)<br />
16-bit<br />
Bus<br />
32-bit<br />
Bus<br />
SDRAM<br />
Configuration<br />
(Words x<br />
Bits)<br />
Chip<br />
Size<br />
Number Chips/<br />
Partition<br />
16-bit<br />
Bus<br />
32-bit<br />
bus<br />
Bank Bits x<br />
Row bits x<br />
Column<br />
Bits<br />
Maximum<br />
Memory<br />
(4 Partitions)<br />
16-bit<br />
Bus<br />
32-bit<br />
Bus<br />
Total Number<br />
of Chips<br />
16-bit<br />
Bus<br />
32-bit<br />
Bus<br />
2 Mbyte 4 Mbyte 1M x 16 16 Mbit 1 2 1 x 11 x 8 8 Mbyte 16 Mbyte 4 8<br />
4 Mbyte 8 Mbyte 2 M x 8 16 Mbit 2 4 1 x 11 x 9 16 Mbyte 32 Mbyte 8 16<br />
8 Mbyte 16 Mbyte 4 M x 4 16 Mbit 4 8 1 x 11 x 10 32 Mbyte 64 Mbyte 16 32<br />
N/A 8 Mbyte 2 M x 32 64 Mbit N/A 1 2 x 11 x 8 N/A 32 Mbyte N/A 4<br />
8 Mbyte 16 Mbyte 4 M x 16 64 Mbit 1 2<br />
1 x 13 x 8<br />
2 x 12 x 8<br />
32 Mbyte 64 Mbyte 4 8<br />
16 Mbyte 32 Mbyte 8 M x 8 64 Mbit 2 4<br />
1 x 13 x 9<br />
2 x 12 x 9<br />
64 Mbyte<br />
128<br />
Mbyte<br />
8 16<br />
32 Mbyte 64 Mbyte 16 M x 4 64 Mbit 4 8<br />
1 x 13 x 10<br />
2 x 12 x 10<br />
128<br />
Mbyte<br />
256<br />
Mbyte<br />
16 32<br />
16 Mbyte 32 Mbyte 8 M x 16 128 Mbit 1 2 2 x 12 x 9 64 Mbyte<br />
128<br />
Mbyte<br />
4 8<br />
32 Mbyte 64 Mbyte 16 M x 8 128 Mbit 2 4 2 x 12 x 10<br />
128<br />
Mbyte<br />
256<br />
Mbyte<br />
8 16<br />
64 Mbyte N/A 32 M x 4 128 Mbit 4 8 2 x 12 x 11<br />
256<br />
Mbyte<br />
N/A 16 32<br />
32 Mbyte 64 Mbyte<br />
16 M x<br />
16<br />
256 Mbit 1 2 2 x 13 x 9<br />
128<br />
Mbyte<br />
256<br />
Mbyte<br />
4 8<br />
64 Mbyte N/A 32 M x 8 256 Mbit 2 4 2 x 13 x 10<br />
256<br />
Mbyte<br />
N/A 8 16<br />
<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide 2-5
System Memory Interface<br />
2.5 SDRAM Address Mapping<br />
SDRAM Address Mapping is shown in Table 2-3 <strong>and</strong> Table 2-4.<br />
Table 2-3. Normal Mode Memory Address Mapping<br />
SDRAM<br />
# Bits<br />
Bank x<br />
Row x<br />
Col<br />
The applications processor pin mapping to SDRAM devices<br />
(The address lines at the top of the columns are the processor address lines)<br />
Device Technology A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10<br />
1Mx16 16Mbit 1x11x8 BS0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0<br />
2Mx8 16Mbit 1x11x9 BS0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0<br />
4Mx4 16Mbit 1x11x10 BS0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0<br />
1x12x8 BS0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0<br />
1x12x9 BS0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0<br />
1x12x10 BS0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0<br />
1x12x11 BS0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0<br />
1x13x8 BS0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0<br />
1x13x9 BS0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0<br />
1x13x10 BS0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0<br />
1x13x11 BS0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0<br />
2Mx32 64Mbit 2x11x8 BS1 BS0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0<br />
2x11x9 BS1 BS0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0<br />
2x11x10 BS1 BS0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0<br />
4Mx16/4Mx32 64Mbit/128Mbit 2x12x8 BS1 BS0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0<br />
8Mx8/8Mx16 64Mbit/128Mbit 2x12x9 BS1 BS0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0<br />
16Mx4/16Mx8 64Mbit/128Mbit 2x12x10 BS1 BS0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0<br />
32Mx4 128Mbit 2x12x11 BS1 BS0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0<br />
8Mx32 256Mbit 2x13x8 BS1 BS0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0<br />
16Mx16 256Mbit 2x13x9 BS1 BS1 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0<br />
2-6 <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide
System Memory Interface<br />
Table 2-4. <strong>Applications</strong> Processor Compatibility Mode Address Line Mapping<br />
SDRAM<br />
# Bits<br />
Bank x<br />
Row x<br />
Col<br />
The applications processor pin mapping to SDRAM devices<br />
(The address lines at the top of the columns are the processor address lines)<br />
Device Technology A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10<br />
1Mx16 16Mbit 1x11x8 BS0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0<br />
2Mx8 16Mbit 1x11x9 BS0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0<br />
4Mx4 16Mbit 1x11x10 BS0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0<br />
1x12x8 A11 BS0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0<br />
1x12x9 A11 BS0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0<br />
1x12x10 A11 BS0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0<br />
1x12x11 A11 BS0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0<br />
1x13x8 A12 A11 BS0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0<br />
1x13x9 A12 A11 BS0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0<br />
1x13x10 A12 A11 BS0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0<br />
1x13x11 A12 A11 BS0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0<br />
2Mx32 64Mbit 2x11x8 BS1 BS0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0<br />
2x11x9 BS1 BS0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0<br />
2x11x10 BS1 BS0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0<br />
4Mx16/4Mx32 64Mbit/128Mbit 2x12x8 BS1 BS0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0<br />
8Mx8/8Mx16 64Mbit/128Mbit 2x12x9 BS1 BS0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0<br />
16Mx4/16Mx8 64Mbit/128Mbit 2x12x10 BS1 BS0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0<br />
32Mx4 128Mbit 2x12x11 BS1 BS0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0<br />
8Mx32 256Mbit 2x13x8 A12 BS1 BS0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0<br />
16Mx16 256Mbit 2x13x9 A12 BS1 BS0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0<br />
2.6 Static Memory<br />
2.6.1 Overview<br />
The applications processor external memory bus interface supports the following static memory<br />
types:<br />
• Synchronous <strong>and</strong> asynchronous Burst mode <strong>and</strong> Page mode Flash<br />
• Synchronous Mask ROM (SMROM)<br />
• Page Mode ROM<br />
• SRAM<br />
• SRAM-like Variable Latency I/O (VLIO)<br />
• PCMCIA expansion memory<br />
• Compact Flash<br />
<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide 2-7
System Memory Interface<br />
Memory types are programmable through the memory interface configuration registers.<br />
Six chip selects control the static memory interface, nCS. All are configurable for nonburst<br />
ROM or Flash memory, burst ROM or Flash, SRAM, or SRAM-like variable latency I/O devices.<br />
The variable latency I/O interface differs from SRAM in that it allows the data ready input signal<br />
(RDY) to insert a variable number of memory-cycle-wait states. The data bus width for each chip<br />
select region may be programmed to be 16-bit or 32-bit. nCS are also configurable for<br />
Synchronous Static Memory.<br />
For SRAM <strong>and</strong> variable latency I/O implementations, DQM signals are used for the write<br />
byte enables, where DQM corresponds to the MSB. The applications processor supplies 26-<br />
bits of byte address for access of up to 64 Mbytes per chip select. However, when the address is<br />
sent out on the MA pins, MA reflects the actual address, not the byte address. The lower one or two<br />
internal address bits are truncated appropriately.<br />
2.6.2 Boot Time Defaults<br />
Booting configuration is device specific. For example, you cannot use a 32-bit memory booting<br />
configuration with a <strong>PXA210</strong> applications processor. Table 2-5 shows valid booting configurations<br />
based on processor type, while Table 2-6 shows boot selection definitions. See Section 7.10.2,<br />
“Boot-Time Configurations” in the <strong>Intel</strong>® <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong><br />
Developer’s Manual for more detailed descriptions of these Boot Time Configurations.<br />
Table 2-5. Valid Booting Configurations Based on Package Type<br />
Processor Type<br />
0 (<strong>PXA210</strong><br />
applications<br />
processor)<br />
Valid Booting Configurations<br />
001<br />
101<br />
111<br />
000<br />
1 (<strong>PXA250</strong><br />
applications<br />
processor)<br />
001<br />
100<br />
101<br />
110<br />
111<br />
Table 2-6. BOOT_SEL Definitions (Sheet 1 of 2)<br />
BOOT_SEL<br />
2 1 0<br />
Boot From . . .<br />
0 0 0 Asynchronous 32-bit ROM<br />
0 0 1 Asynchronous 16-bit ROM<br />
1 0 0<br />
1 32-bit Synchronous Mask ROM (64 Mbits)<br />
2 16-bit Synchronous Mask ROMs = 32-bits (32 Mbits each)<br />
2-8 <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide
System Memory Interface<br />
Table 2-6. BOOT_SEL Definitions (Sheet 2 of 2)<br />
BOOT_SEL<br />
2 1 0<br />
Boot From . . .<br />
1 0 1 1 16-bit Synchronous Mask ROM (64 Mbits)<br />
1 1 0 2 16-bit Synchronous Mask ROMs = 32-bits (64 Mbits each)<br />
1 1 1 1 16-bit Synchronous Mask ROM (64 Mbits)<br />
2.6.3 SRAM / ROM / Flash / Synchronous Fast Flash Memory<br />
Options<br />
Table 2-7 contains the AC specification for SRAM / ROM / Flash / Synchronous Fast Flash.<br />
Table 2-7. SRAM / ROM / Flash / Synchronous Fast Flash AC Specifications<br />
Symbol<br />
Description<br />
MEMCKLK<br />
99.5 118.0 132.7 147.5 165.9<br />
Units<br />
Notes<br />
SRAM / ROM / Flash / Synchronous Fast Flash (WRITES) (Asynchronous)<br />
tromAS<br />
MA(25:0) setup to nOE, nSDCAS (as<br />
nADV) asserted<br />
10 8.5 7.5 6.8 6 ns, 1<br />
tromAH<br />
MA(25:0) hold after nCS, nOE,<br />
nSDCAS (as nADV) de-asserted<br />
10 8.5 7.5 6.8 6 ns, 1<br />
tromASW MA(25:0) setup to nWE asserted 30 25.5 22.5 20.4 18 ns, 3<br />
tromAHW MA(25:0) hold after nWE de-asserted 10 8.5 7.5 6.8 6 ns, 1<br />
tromCES nCS setup to nWE asserted 20 17 15 13.6 12 ns, 2<br />
tromCEH nCS hold after nWE de-asserted 10 8.5 7.5 6.8 6 ns, 1<br />
tromDS<br />
tromDSWH<br />
tromDH<br />
tromNWE<br />
MD(31:0), DQM(3:0) write data setup to<br />
nWE asserted<br />
MD(31:0), DQM(3:0) write data setup to<br />
nWE de-asserted<br />
MD(31:0), DQM(3:0) write data hold<br />
after nWE de-asserted<br />
nWE high time between beats of write<br />
data<br />
NOTES:<br />
1. This number represents 1 MEMCLK period<br />
2. This number represents 2 MEMCLK periods<br />
10 8.5 7.5 6.8 6 ns, 1<br />
20 17 15 13.6 12 ns, 2<br />
10 8.5 7.5 6.8 6 ns, 1<br />
20 17 15 13.6 12 ns, 2<br />
2.6.4 Variable Latency I/O Interface Overview<br />
Both reads <strong>and</strong> writes for VLIO differ from SRAM in that the <strong>PXA250</strong> applications processor<br />
samples the data-ready input, RDY. The RDY signal is level sensitive <strong>and</strong> goes through a two-stage<br />
synchronizer on input. When the internal RDY signal is high, the I/O device is ready for data<br />
transfer. This means that for a transaction to complete at the minimum assertion time for either<br />
nOE or nPWE (RDF+1), the RDY signal must be high two clocks prior to the minimum assertion<br />
time for either nOE or nPWE (RDF-1). Data will be latched on the rising edge of memclk once the<br />
internal RDY signal is high <strong>and</strong> the minimum assertion time of RDF+1 has been reached. Once the<br />
<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide 2-9
System Memory Interface<br />
data has been latched, the address may change on the next rising edge of MEMCLK or any cycles<br />
thereafter. The nOE or nPWE signal de-asserts one MEMCLK after data is latched. Before a<br />
subsequent data beat, nOE or nPWE remains deasserted for RDN+1 memory cycles. The chip<br />
select <strong>and</strong> byte selects, DQM[3:0], remain asserted for one memory cycle after the burst’s final<br />
nOE or nPWE deassertion. Refer to Figure 2-3 for 32-Bit Variable Latency I/O read timing <strong>and</strong><br />
Figure 2-8 for Variable Latency I/O Interface AC Specifications<br />
Figure 2-3. 32-Bit Variable Latency I/O Read Timing (Burst-of-Four, One Wait Cycle Per Beat)<br />
0ns 100ns 200ns 300ns<br />
memlk<br />
nCS[0]<br />
MA[25:2]<br />
MA[1:0]<br />
tAS<br />
0 1 2 3<br />
"00"<br />
nOE<br />
tASRW0<br />
tCES<br />
tAH<br />
RDN+1<br />
tASWN<br />
RDF+1+Waits<br />
tCEH<br />
RRR+1<br />
nPWE<br />
RDnWR<br />
RDY<br />
MD[31:0]<br />
DQM[3:0]<br />
"0000"<br />
nCS[1]<br />
A8867-01<br />
Table 2-8. Variable Latency I/O Interface AC Specifications (Sheet 1 of 2)<br />
Symbol<br />
Description<br />
MEMCKLK<br />
99.5 118.0 132.7 147.5 165.9<br />
Units<br />
Notes<br />
Variable Latency IO Interface (VLIO) (Asynchronous)<br />
tvlioAS MA(25:0) setup to nCS asserted 10 8.5 7.5 6.8 6 ns, 1<br />
tvlioASRW<br />
MA(25:0) setup to nOE or nPWE<br />
asserted<br />
10 8.5 7.5 6.8 6 ns, 1<br />
tvlioAH<br />
MA(25:0) hold after nOE or nPWE deasserted<br />
10 8.5 7.5 6.8 6 ns, 1<br />
tvlioCES nCS setup to nOE or nPWE asserted 20 17 15 13.6 12 ns, 2<br />
tvlioCEH<br />
nCS hold after nOE or nPWE deasserted<br />
10 8.5 7.5 6.8 6 ns, 1<br />
2-10 <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide
System Memory Interface<br />
Table 2-8. Variable Latency I/O Interface AC Specifications (Sheet 2 of 2)<br />
Symbol<br />
Description<br />
MEMCKLK<br />
99.5 118.0 132.7 147.5 165.9<br />
Units<br />
Notes<br />
tvlioDSW<br />
tvlioDSWH<br />
tvlioDHW<br />
tvlioDHR<br />
tvlioRDYH<br />
MD(31:0), DQM(3:0) write data setup to<br />
nPWE asserted<br />
MD(31:0), DQM(3:0) write data setup to<br />
nPWE de-asserted<br />
MD(31:0), DQM(3:0) hold after nPWE<br />
de-asserted<br />
MD(31:0) read data hold after nOE deasserted<br />
RDY hold after nOE, nPWE deasserted<br />
nPWE, nOE high time between beats of<br />
tvlioNPWE<br />
write or read data<br />
NOTES:<br />
1. This number represents 1 MEMCLK period<br />
2. This number represents 2 MEMCLK periods<br />
10 8.5 7.5 6.8 6 ns, 1<br />
20 17 15 13.6 12 ns, 2<br />
10 8.5 7.5 6.8 6 ns, 1<br />
0 0 0 0 0 ns<br />
0 0 0 0 0 ns<br />
20 17 15 13.6 12 ns, 2<br />
2.6.5 External Logic for PCMCIA Implementation<br />
The <strong>PXA250</strong> applications processor requires external glue logic to complete the PCMCIA socket<br />
interface. Figure 2-4, “Expansion Card External Logic for a Two-Socket Configuration” on page 2-<br />
12 <strong>and</strong> Figure 2-5, “Expansion Card External Logic for a One-Socket Configuration” on page 2-13<br />
show general solutions for one <strong>and</strong> two socket configurations. Use GPIO or memory-mapped<br />
external registers to control the PCMCIA interface’s reset, power selection (V CC <strong>and</strong> V PP ), <strong>and</strong><br />
drive enables. These diagrams show the logical connections necessary to support hot insertion<br />
capability. For dual-voltage support, level shifting buffers are required for all the applications<br />
processor input signals. Hot insertion capability requires each socket be electrically isolated from<br />
the other <strong>and</strong> from the remainder of the memory system. If one or both of these features are not<br />
required, you may eliminate some of the logic shown in these diagrams. The applications processor<br />
allows either 1-socket or 2-socket solutions. In the 1-socket solution, only minimal glue logic is<br />
required (typically for the data transceivers, address buffers, <strong>and</strong> level shifting buffers.) To achieve<br />
this some of the signals are routed through dual-duty GPIO pins. The nOE of the transceivers is<br />
driven through the PSKTSEL pin, which is not needed in the one-socket solution. The DIR pin of<br />
the transceiver is driven through the RDnWR pin. A GPIO is used for the three-state signal of the<br />
address <strong>and</strong> nPWE lines. These signals are used for memories other than the card interface <strong>and</strong><br />
must be three-stated.<br />
Note:<br />
Note:<br />
For 2.5 V VCCN, 5 V to 2.5 V level shifters are required.<br />
PCMCIA is only implemented on the <strong>PXA250</strong> applications processor.<br />
In the 2-socket solution, all pins assume their normal duties <strong>and</strong> glue logic is necessary for proper<br />
operation of the system. The pull-ups shown are included for compliance with PC Card St<strong>and</strong>ard -<br />
Volume 2 - Electrical Specification. Remove power from these pull-ups during sleep to avoid<br />
unnecessary power consumption. Refer to Table 2-9 for the PCMCIA or compact Flash card<br />
interface AC specifications.<br />
<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide 2-11
System Memory Interface<br />
Figure 2-4. Expansion Card External Logic for a Two-Socket Configuration<br />
<strong>PXA250</strong><br />
<strong>Applications</strong><br />
Processor<br />
D(15:0)<br />
Socket 0<br />
D(15:0)<br />
nPCEx<br />
DIR OE#<br />
Socket 1<br />
D(15:0)<br />
nPOE<br />
nPIOR<br />
nPCEx<br />
DIR OE#<br />
GPIO(w)<br />
CD1#<br />
CD2#<br />
GPIO(x)<br />
CD1#<br />
CD2#<br />
GPIO(y)<br />
RDY/BSY#<br />
GPIO(z)<br />
RDY/BSY#<br />
PSKTSEL<br />
MA(25:0)<br />
nPREG<br />
A(25:0)<br />
REG#<br />
nPCE(1:2)<br />
nPOE,<br />
nPWE<br />
nPIOW,<br />
nPIOR<br />
6 6<br />
6<br />
CE(1:2)#<br />
OE#<br />
WE#<br />
IOR#<br />
IOW#<br />
WAIT#<br />
A(25:0)<br />
REG#<br />
CE(1:2)#<br />
OE#<br />
WE#<br />
IOR#<br />
IOW#<br />
nPWAIT<br />
WAIT#<br />
IOIS1616#<br />
nPIOIS16<br />
IOIS1616#<br />
A8863-02<br />
2-12 <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide
System Memory Interface<br />
Figure 2-5. Expansion Card External Logic for a One-Socket Configuration<br />
<strong>PXA250</strong> Socket 0<br />
MD<br />
D<br />
DIR<br />
nOE<br />
RD/nWR<br />
GPIO<br />
GPIO<br />
PSKTSEL<br />
GPIO<br />
GPIO<br />
MA<br />
nPCD0<br />
nPCD1<br />
PRDY_BSY0<br />
PADDR_EN0<br />
nCD<br />
nCD<br />
RDY/nBSY<br />
A<br />
nPWE<br />
nWE<br />
nPREG<br />
nPCE<br />
nPOE<br />
nPIOR<br />
nPIOW<br />
nPWAIT<br />
nIOIS16<br />
5V to 3.3V<br />
5V to 3.3V<br />
nREG<br />
nCE<br />
nOE<br />
nIOR<br />
nIOW<br />
nWAIT<br />
nIOIS16<br />
Table 2-9. Card Interface (PCMCIA or Compact Flash) AC Specifications (Sheet 1 of 2)<br />
Symbol<br />
Description<br />
MEMCKLK<br />
99.5 118.0 132.7 147.5 165.9<br />
Units<br />
Notes<br />
Card Interface (PCMCIA or Compact Flash) (Asynchronous)<br />
tcardAS<br />
tcardAH<br />
tcardDS<br />
MA(25:0), nPREG, PSKTSEL, nPCE<br />
setup to nPWE, nPOE, nPIOW, or<br />
nPIOR asserted<br />
MA(25:0), nPREG, PSKTSEL, nPCE<br />
hold after nPWE, nPOE, nPIOW, or<br />
nPIOR de-asserted<br />
MD(31:0) setup to nPWE, nPOE,<br />
nPIOW, or NPIOR asserted<br />
20 17 15 13.6 12 ns, 1<br />
10 8.5 7.5 6.8 6 ns, 1<br />
10 8.5 7.5 6.8 6 ns, 1<br />
<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide 2-13
System Memory Interface<br />
Table 2-9. Card Interface (PCMCIA or Compact Flash) AC Specifications (Sheet 2 of 2)<br />
Symbol<br />
Description<br />
MEMCKLK<br />
99.5 118.0 132.7 147.5 165.9<br />
Units<br />
Notes<br />
tcardDH<br />
tcardCMD<br />
MD(31:0) hold after nPWE, nPOE,<br />
nPIOW, or NPIOR de-asserted<br />
nPWE, nPOE, nPIOW, or nPIOR<br />
comm<strong>and</strong> assertion<br />
10 8.5 7.5 6.8 6 ns, 1<br />
30 25.5 22.5 20.4 18 ns, 1<br />
NOTE:<br />
1. These numbers are minmums. They can be much larger based on the programmable Card Interface<br />
timing registers.<br />
2.6.6 DMA / Companion Chip Interface<br />
Connect a companion chip to the applications processor via:<br />
• Alternate Bus Master Mode<br />
• Variable Latency I/O<br />
• Flow through DMA<br />
These connections are illustrated in Figure 2-6 <strong>and</strong> Figure 2-7.<br />
2-14 <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide
System Memory Interface<br />
Figure 2-6. Alternate Bus Master Mode<br />
<strong>PXA250</strong><br />
EXTERNAL SYSTEM<br />
SDCKE<br />
<strong>PXA250</strong><br />
Memory<br />
Controller<br />
SDCLK<br />
nSDCS(0)<br />
nSDRAS<br />
nSDCAS<br />
nWE<br />
MA<br />
External<br />
SDRAM<br />
Bank 0<br />
DQM<br />
MD<br />
MBREQ<br />
MBGNT<br />
<strong>PXA250</strong><br />
GPIO<br />
Block<br />
GPIO (MBGNT)<br />
GPIO (MBREQ)<br />
Companion<br />
Chip<br />
<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide 2-15
System Memory Interface<br />
Figure 2-7. Variable Latency I/O<br />
<strong>PXA250</strong><br />
<strong>PXA250</strong><br />
Memory<br />
Controller<br />
EXTERNAL SYSTEM<br />
nCS(0,1,2,3,4,5)<br />
nOE<br />
nPWE<br />
MA<br />
DQM<br />
Companion<br />
Chip<br />
MD<br />
RDY<br />
2-16 <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide
System Memory Interface<br />
2.7 System Memory Layout Guidelines<br />
2.7.1 System Memory Topologies (Min <strong>and</strong> Max Simulated<br />
Loading)<br />
Figure 2-8, Figure 2-9, Figure 2-10, <strong>and</strong> Figure 2-11 are the topologies that where simulated to<br />
develop the trace length recommendations in Section 2.7.2. These topologies are for reference<br />
only.<br />
Figure 2-8. CS, CKE, DQM, CLK, MA minimum loading topology<br />
CS, CKE, DQM,<br />
CLK, MA<br />
SDRAM<br />
Figure 2-9. CS, CKE, DQM, CLK, MA Maximum Loading Topology<br />
SDRAM<br />
CS, CKE, DQM,<br />
CLK, MA<br />
SDRAM<br />
SDRAM<br />
SDRAM<br />
Figure 2-10. MD Minimum Loading Topology<br />
MD<br />
SDRAM<br />
<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide 2-17
System Memory Interface<br />
Figure 2-11. MD maximum loading topology<br />
SDRAM<br />
SDRAM<br />
MD<br />
AUX<br />
AUX<br />
AUX<br />
AUX<br />
2.7.2 System Memory Recommended Trace Lengths<br />
Table 2-10 details the minimum <strong>and</strong> maximum trace lengths that were simulated for the<br />
applications processor. These trace lengths are not the absolute trace lengths that will work given<br />
the loading conditions. The trace lengths in Table 2-10 are measured from the applications<br />
processor to the individual component pins. The board impedance for the simulations was 60ohm<br />
+/- 10%.<br />
Table 2-10. Minimum <strong>and</strong> Maximum Trace Lengths for the SDRAM Signals<br />
Signal<br />
Min<br />
Trace Length<br />
Max<br />
Trace Length<br />
CS, CKE, DQM 0.75 in 4.5 in<br />
CLK 1.0 in 4.25 in<br />
MA 1.0 in 4.5 in<br />
MD 1.0 in 4.25 in<br />
2-18 <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide
LCD Display Controller 3<br />
This chapter describes sample hardware connections from the <strong>PXA250</strong> applications processor to<br />
various types of LCD controllers. Active (TFT) as well as passive (DSTN) displays are discussed<br />
as well as single <strong>and</strong> dual panel displays. These should not be considered the only possible ways to<br />
connect an LCD panel to the <strong>PXA250</strong> applications processor, but should serve as a reference to<br />
assist with hardware design considerations. Other panels, for example panels without L_FCLK or<br />
L_LCLK, have been successfully connected to the <strong>PXA250</strong>.<br />
3.1 LCD Display Overview<br />
The <strong>PXA250</strong> applications processor supports both active <strong>and</strong> passive LCD displays. Active<br />
displays generally produce better looking images, but at a higher cost. Passive displays are<br />
generally less expensive, but their displays are inferior to active displays. However, recent<br />
advances in dithering technology are closing the quality gap between passive <strong>and</strong> active displays.<br />
Note:<br />
Names used for “LCD Panel Pin” are representative names <strong>and</strong> may not match those on all LCD<br />
panels. Refer to the LCD panel reference documentation for the actual name.<br />
3.2 Passive (DSTN) Displays<br />
Several different types of passive displays are available in both color <strong>and</strong> monochrome. These<br />
maybe single or dual panel displays. Additionally, some monochrome displays use double-pixel<br />
data mode (twice the number of pixels as a normal monochrome display). With the exception of the<br />
number of data pins required, all of these choices affect the software configuration <strong>and</strong> support, not<br />
the system hardware design. In fact, most passive displays use a single interconnection scheme. For<br />
information on the software changes <strong>and</strong> performance considerations of the various display<br />
options, refer to the <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Developer’s Manual.<br />
Passive displays drive dithered data to the LCD panel - which means that for each pixel clock cycle<br />
a single data line drives an ON/OFF signal for one color of a single pixel.<br />
Table 3-1 describes the number of L_DD pins required for the various types of passive displays, as<br />
well as which LCD data pins are used for which panel (upper or lower).<br />
Table 3-1. LCD Controller Data Pin Utilization (Sheet 1 of 2)<br />
Color/<br />
Monochrome<br />
Panel<br />
Single/<br />
Dual Panel<br />
Double-Pixel<br />
Mode<br />
Screen Portion<br />
Pins<br />
Monochrome Single No Whole L_DD<br />
Monochrome Single Yes Whole L_DD 1<br />
Top<br />
L_DD<br />
Monochrome Dual No<br />
Bottom<br />
L_DD<br />
Color Single N/A Whole L_DD<br />
<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> Processor Design Guide 3-1
LCD Display Controller<br />
Table 3-1. LCD Controller Data Pin Utilization (Sheet 2 of 2)<br />
Color/<br />
Monochrome<br />
Panel<br />
Single/<br />
Dual Panel<br />
Double-Pixel<br />
Mode<br />
Screen Portion<br />
Pins<br />
Color Dual N/A<br />
NOTE: 1. Double pixel data mode (DPD)=1.<br />
Top<br />
Bottom<br />
L_DD<br />
L_DD<br />
For passive displays, the pins described in Table 3-2 are required connections between the <strong>PXA250</strong><br />
applications processor <strong>and</strong> your LCD panel.<br />
Table 3-2. Passive Display Pins Required<br />
<strong>PXA250</strong> Pin LCD Panel Pin PIn Type 1 Definition<br />
L_DD DU_x, DL_x Output<br />
Data lines used to transmit either four or eight data values at a time to<br />
the LCD display. For monochrome displays, each pin value represents<br />
a single pixel; for passive color, groupings of three pin values represent<br />
one pixel (red, green, <strong>and</strong> blue data values). Either the bottom four pins<br />
(L_DD), the bottom 8 pins (L_DD) or all 16 pixel data pins<br />
(L_DD)will be used as shown in Table 3-1<br />
L_PCLK Pixel_Clock Output<br />
L_LCLK Line_Clock Output<br />
L_FCLK Frame_Clock Output<br />
L_BIAS Bias Output<br />
N/A Vcon 2 N/A<br />
Pixel Clock - used by the LCD display to clock the pixel data into the<br />
line shift register.<br />
Line Clock - used by the LCD display to signal the end of a line of pixels<br />
that transfers the line data from the shift register to the screen <strong>and</strong><br />
increment the line pointers.<br />
Frame Clock - used by the LCD displays to signal the start of a new<br />
frame of pixels that resets the line pointers to the top of the screen.<br />
AC bias used to signal the LCD display to switch the polarity of the<br />
power supplies to the row <strong>and</strong> column axis of the screen to counteract<br />
DC offset.<br />
Contrast Voltage - Adjustable voltage input to LCD panel - external<br />
voltage circuitry is required (no pin available on <strong>PXA250</strong>).<br />
NOTES:<br />
1. “Pin Type” is in reference to the <strong>PXA250</strong> applications processor. Therefore, outputs are pins that drive a signal from the processor to another<br />
device.<br />
2. Vcon is a signal external to the <strong>PXA250</strong> applications processor. Please refer to “Contrast Voltage” on page 8<br />
3.2.1 Typical Connections for Passive Panel Displays<br />
The following diagrams are typical connections <strong>and</strong> serve a guide for designing systems which<br />
contain passive LCD displays. Panels differ on which is the panel’s lest significant bit (Refer to the<br />
LCD panel reference documentation for the lest significant bit.) Each figure indicates the top-left<br />
pixel (1,1) bit. While dual panels indicates the top-left pixel (1,n/2) of the upper <strong>and</strong> lower panels<br />
<strong>and</strong> color passive panels show the top-left-pixel color bits.<br />
3.2.1.1 Passive Monochrome Single Panel Displays<br />
Figure 3-1 is a typical single-panel-monochrome passive display connection.<br />
3-2 <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> Processor Design Guide
LCD Display Controller<br />
Figure 3-1. Single Panel Monochrome Passive Display Typical Connection<br />
L_DD0 - Top left<br />
L_DD1<br />
L_DD2<br />
L_DD3<br />
D0<br />
D1<br />
D2<br />
D3<br />
<strong>PXA250</strong> Processor<br />
LCD Display<br />
L_PCLK<br />
L_LCLK<br />
L_FCLK<br />
L_BIAS<br />
Pixel_Clock<br />
Line_Clock<br />
Frame_Clock<br />
Bias<br />
3.2.1.2 Passive Monochrome Single Panel Displays, Double-Pixel Data<br />
Figure 3-2 shows typical connections for a single-panel-monochrome passive display using<br />
double-pixel data mode.<br />
Figure 3-2. Passive Monochrome Single Panel Displays, Double-Pixel Data Typical<br />
Connection<br />
<strong>PXA250</strong> Processor<br />
L_DD0 - Top left<br />
L_DD1<br />
L_DD2<br />
L_DD3<br />
L_DD4<br />
L_DD5<br />
L_DD6<br />
L_DD7<br />
D0<br />
D1<br />
D2<br />
D3<br />
D4<br />
D5<br />
D6<br />
D7<br />
LCD Display<br />
L_PCLK<br />
L_LCLK<br />
L_FCLK<br />
L_BIAS<br />
Pixel_Clock<br />
Line_Clock<br />
Frame_Clock<br />
Bias<br />
3.2.1.3 Passive Monochrome Dual Panel Displays<br />
Figure 3-3 is a typical dual-panel-monochrome passive display connection.<br />
<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> Processor Design Guide 3-3
LCD Display Controller<br />
Figure 3-3. Passive Monochrome Dual Panel Displays Typical Connection<br />
L_DD0 - Top left for upper panel<br />
L_DD1<br />
L_DD2<br />
L_DD3<br />
DU_0<br />
DU_1<br />
DU_2<br />
DU_3<br />
Upper Panel<br />
<strong>PXA250</strong> Processor<br />
L_PCLK<br />
L_LCLK<br />
L_FCLK<br />
L_BIAS<br />
Pixel_Clock<br />
Line_Clock<br />
Frame_Clock<br />
Bias<br />
LCD Display<br />
L_DD4 - Top left for lower panel<br />
L_DD5<br />
L_DD6<br />
L_DD7<br />
DL_0<br />
DL_1<br />
DL_2<br />
DL_3<br />
Lower Panel<br />
3.2.1.4 Passive Color Single Panel Displays<br />
Figure 3-4 is a typical single-panel-color passive display connection.<br />
Figure 3-4. Passive Color Single Panel Displays Typical Connection<br />
<strong>PXA250</strong> Processor<br />
L_DD0<br />
L_DD1<br />
L_DD2<br />
L_DD3<br />
L_DD4<br />
L_DD5 - Top left Blue<br />
L_DD6 - Top left Green<br />
L_DD7 - Top left Red<br />
D0<br />
D1<br />
D2<br />
D3<br />
D4<br />
D5<br />
D6<br />
D7<br />
LCD Display<br />
L_PCLK<br />
L_LCLK<br />
L_FCLK<br />
L_BIAS<br />
Pixel_Clock<br />
Line_Clock<br />
Frame_Clock<br />
Bias<br />
3.2.1.5 Passive Color Dual Panel Displays<br />
Figure 3-5 is a typical dual-panel-color passive display connection.<br />
3-4 <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> Processor Design Guide
LCD Display Controller<br />
Figure 3-5. Passive Color Dual Panel Displays Typical Connection<br />
<strong>PXA250</strong> Processor<br />
L_DD0<br />
L_DD1<br />
L_DD2<br />
L_DD3<br />
L_DD4<br />
L_DD5 - Top left Blue for upper panel<br />
L_DD6 - Top left Green for upper panel<br />
L_DD7 - Top left Red for upper panel<br />
L_PCLK<br />
L_LCLK<br />
L_FCLK<br />
L_BIAS<br />
DU_0<br />
DU_1<br />
DU_2<br />
DU_3<br />
DU_4<br />
DU_5<br />
DU_6<br />
DU_7<br />
Pixel_Clock<br />
Line_Clock<br />
Frame_Clock<br />
Bias<br />
Upper Panel<br />
LCD Display<br />
L_DD8<br />
L_DD9<br />
L_DD10<br />
L_DD11<br />
L_DD12<br />
L_DD13 - Top left Blue for lower panel<br />
L_DD14 - Top left Green for lower panel<br />
L_DD15 - Top left Red for lower panel<br />
DL_0<br />
DL_1<br />
DL_2<br />
DL_3<br />
DL_4<br />
DL_5<br />
DL_6<br />
DL_7<br />
Lower Panel<br />
3.3 Active (TFT) Displays<br />
Because data is sent to the panel as raw 16-bit pixel data, active displays require16 data pins in<br />
order to transfer the pixel data from the controller. All 16 data lines are also required to drive one<br />
pixel value. The 16 bits of data describe the intensity level of the red, green <strong>and</strong> blue for each pixel.<br />
Typically, this is formatted as 5 bits for red, 6 bits for green <strong>and</strong> 5 bits for blue, but this can vary by<br />
display <strong>and</strong> is controlled by the software writing to the frame buffer. Refer to the display datasheet<br />
to ensure that the correct the <strong>PXA250</strong> applications processor LCD data lines are connected to the<br />
correct LCD panel data lines.<br />
Many active displays actually have more than 16 data lines - usually 18 (6 of each color). For these<br />
panels it is recommended that the most significant lines of the panel lines are connected to the data<br />
lines from the <strong>PXA250</strong> applications processor. This maintains the panel’s full range of colors but<br />
increases the granularity of the color spectrum with an insufficient number of data lines. All unused<br />
panel data lines can be tied either high or low. Other options include tying the LSB of red <strong>and</strong> blue<br />
to the next bit, R1 or B1.<br />
For active displays, connect the pins described in Table 3-3 between the <strong>PXA250</strong> applications<br />
processor <strong>and</strong> the LCD panel.<br />
<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> Processor Design Guide 3-5
LCD Display Controller<br />
Table 3-3. Active Display Pins Required<br />
<strong>PXA250</strong> Pin LCD Panel Pin PIn Type 1 Definition<br />
L_DD<br />
R,G,<br />
B<br />
Output<br />
L_PCLK Clock Output<br />
L_LCLK Horizontal Sync Output<br />
L_FCLK Vertical Sync Output<br />
L_BIAS<br />
DE (Data<br />
Enable)<br />
Output<br />
N/A Vcon 2 N/A<br />
Data lines used to transmit the 16 bit data values to the LCD display.<br />
Pixel Clock - used by the LCD display to clock the pixel data into the<br />
line shift register. In active mode this clock transitions constantly.<br />
Line Clock - used by the LCD display to signal the end of a line of pixels<br />
that transfers the line data from the shift register to the screen <strong>and</strong><br />
increment the line pointers. Also signals the panel to start a new line.<br />
Frame Clock - used by the LCD displays to signal the start of a new<br />
frame of pixels that resets the line pointers to the top of the screen.<br />
AC biases used in active mode as a data enable signal when data<br />
should be latched by the pixel clock from the data lines.<br />
Contrast Voltage - Adjustable voltage input to LCD panel - external<br />
voltage circuitry is required (no pin available on the <strong>PXA250</strong><br />
applications processor).<br />
NOTES:<br />
1. In reference to the <strong>PXA250</strong> applications processor. Therefore, outputs are pins that drive a signal from the <strong>PXA250</strong><br />
applications processor to another device.<br />
2. Vcon is a signal external to the <strong>PXA250</strong> applications processor. Please refer to Section 3.5.1, “Contrast Voltage” on page 8.<br />
3.3.1 Typical connections for Active Panel Displays<br />
Figure 3-6, “Active Color Display Typical Connection” on page 7 shows a typical connection for<br />
an active panel display <strong>and</strong> should serve as a guide for designing systems which contain active<br />
LCD displays. The MSB of each color is indicated. The panel is 18-bit, with the LSB of red <strong>and</strong><br />
blue tied to ground.<br />
3-6 <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> Processor Design Guide
LCD Display Controller<br />
Note:<br />
This example shows 6 red, 6 green <strong>and</strong> 6 blue bits on the LCD panel. However, different active<br />
display panels might have more or different data lines. Consult the LCD panel manufacturer’s<br />
datasheet for the actual data lines.<br />
Figure 3-6. Active Color Display Typical Connection<br />
<strong>PXA250</strong> Processor<br />
L_DD0<br />
L_DD1<br />
L_DD2<br />
L_DD3<br />
L_DD4 - MSB of Blue<br />
L_DD5<br />
L_DD6<br />
L_DD7<br />
L_DD8<br />
L_DD9<br />
L_DD10 - MSB of Green<br />
L_DD11<br />
L_DD12<br />
L_DD13<br />
L_DD14<br />
L_DD15 - MSB of Red<br />
B0<br />
B1<br />
B2<br />
B3<br />
B4<br />
B5<br />
G0<br />
G1<br />
G2<br />
G3<br />
G4<br />
G5<br />
R0<br />
R1<br />
R2<br />
R3<br />
R4<br />
R5<br />
LCD Panel<br />
L_PCLK<br />
L_LCLK<br />
L_FCLK<br />
L_BIAS<br />
Clock<br />
Horizontal Sync<br />
Vertical Sync<br />
Data Enable<br />
3.4 <strong>PXA250</strong> Pinout<br />
Table 3-4 describes the ball positions for the LCD controller on the <strong>PXA250</strong> applications<br />
processor.<br />
Table 3-4. <strong>PXA250</strong> LCD Controller Ball Positions (Sheet 1 of 2)<br />
Pin Name<br />
L_DD0<br />
L_DD1<br />
L_DD2<br />
L_DD3<br />
L_DD4<br />
L_DD5<br />
L_DD6<br />
L_DD7<br />
L_DD8<br />
L_DD9<br />
L_DD10<br />
L_DD11<br />
Ball Position<br />
E7<br />
D7<br />
C7<br />
B7<br />
E6<br />
D6<br />
E5<br />
A6<br />
C5<br />
A5<br />
D5<br />
A4<br />
<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> Processor Design Guide 3-7
LCD Display Controller<br />
Table 3-4. <strong>PXA250</strong> LCD Controller Ball Positions (Sheet 2 of 2)<br />
Pin Name<br />
L_DD12<br />
L_DD13<br />
L_DD14<br />
L_DD15<br />
L_FCLK<br />
L_LCLK<br />
L_PCLK<br />
Bias<br />
Ball Position<br />
A3<br />
A2<br />
C3<br />
B3<br />
E8<br />
D8<br />
B8<br />
A8<br />
3.5 Additional Design Considerations<br />
3.5.1 Contrast Voltage<br />
Many displays, both active <strong>and</strong> passive, include a pin for adjusting the display contrast voltage.<br />
This is a variable analog voltage that is supplied to the panel via an voltage source on the system<br />
board. The contrast voltage is adjusted via a variable resistor on the circuit board.<br />
The required voltage range <strong>and</strong> current capabilities vary between panel manufacturers. Consult the<br />
datasheet for your panel to determine the variable voltage circuit design. Ensure that the contrast<br />
voltage is stable, otherwise visual artifacts might result. Possible contrast-voltage circuits are often<br />
suggested by the panel manufacturers.<br />
3.5.2 Backlight Inverter<br />
One potential source of noise for the LCD panel can be the backlight inverter. Since this is a high<br />
voltage device with frequent voltage inversions, it has the potential to inject spurious noise onto the<br />
LCD panel lines. To minimize noise:<br />
• Use a shielded backlight inverter<br />
• Physically locate the inverter as far away from the LCD data lines <strong>and</strong> system board as<br />
possible, usually located with the LCD panel<br />
If power consumption is an issue, chose a backlight inverter that can be disabled through software.<br />
This lets you save power by automatically disabling the backlight if no activity occurs within a<br />
preset period of time<br />
3.5.3 Signal Routing <strong>and</strong> Buffering<br />
Signal transmission rates between the LCD controller <strong>and</strong> the LCD panel are moderate, which<br />
helps to simplify the design of the LCD system. The minimum Pixel Clock Divider (PCD) value<br />
results in a pixel clock rate of one half of the LCLK (this is not the L_LCLK of the LCD<br />
controller.) The maximum LCLK for the <strong>PXA250</strong> applications processor is 166 MHz, resulting in<br />
a maximum pixel clock rate of 83 MHz. Thus, use of 100 MHz design considerations are sufficient<br />
to ensure LCD panel signal integrity.<br />
3-8 <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> Processor Design Guide
LCD Display Controller<br />
However, typical transfer rates are considerably less than 83 Mhz. For example, an 800x600 color<br />
active display running at 75 Hz requires a transfer rate of approximately 36 MHz. To determined<br />
this, calculate the number of pixels (800 x 600 = 480,000) <strong>and</strong> multiply by the screen refresh rate<br />
(75 Hz). Since active panels replace 1 pixel of data with every clock cycle this determines the final<br />
transfer rate. Active displays normally do not require refresh rates as high as 75 Hz, so you may use<br />
a lower refresh rate to reduce transmission rates even more.<br />
Passive displays often do require refresh rates greater than 75 Hz, which transfers more pixels each<br />
clock cycle. For instance, a color passive display with 8 data lines transfers 2 2/3 pixels’ worth of<br />
data each clock cycle. This divides the transmission rate by 2 2/3. Further reductions in the transfer<br />
rate come by using dual panel displays which use twice as many data lines to transfer data - halving<br />
the rate again.<br />
Generally, this gives you lower transfer rates to even large displays <strong>and</strong> thus simpler design<br />
considerations <strong>and</strong> fewer layout constraints.<br />
When laying out your design, minimize trace length of the LCD panel signals <strong>and</strong> allow sufficient<br />
spacing between signals to avoid crosstalk. Crosstalk decreases the signal integrity, especially the<br />
data line signals.<br />
LCD system design is not considered to be critical as infrequent or single bit errors are, typically,<br />
not noticed by the user. Also, the errors are transitory, as the old data is constantly being replaced<br />
with new data. Slower panel refresh rates increase the likelihood that a single error is noticed by the<br />
user. However, there is an counteracting effect in that slower refresh rates relax LCD timing <strong>and</strong><br />
therefore result in fewer screen transmission errors. There are other factors related to choosing a<br />
refresh rate for an LCD system, most significant is the impact on system b<strong>and</strong>width.<br />
If you must use excessively long or poorly routed signals, one possible solution is to add buffers<br />
between the <strong>PXA250</strong> applications processor <strong>and</strong> the LCD panel. This helps strengthen the LCD<br />
panel signal levels <strong>and</strong> synchronizes signal timing. However, this is usually not required as the<br />
LCD panel timings are fairly relaxed. Since the LCD display essentially operates asynchronously<br />
from the processor, the propagation delay of the buffers is not a major concern.<br />
When mounting the LCD panel, it is critical to shield the touchscreen control lines, if present.<br />
Noise from the LCD panel <strong>and</strong> its control signals can become injected into the touchscreen control<br />
lines, causing spurious touch interrupts or loss of resolution.<br />
3.5.4 Panel Connector<br />
Most LCD panels are connected to the system board via a connector, instead of being directly<br />
mounted on the system board. This increases flexibility <strong>and</strong> ease of manufacture. Typically the<br />
manufacturer of the panel recommends a particular connector for the panel. Follow the panel<br />
manufacturer’s recommendation.<br />
<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> Processor Design Guide 3-9
LCD Display Controller<br />
3-10 <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> Processor Design Guide
USB Interface 4<br />
4.1 Self Powered Device<br />
Figure 4-1 shows the USB interface connection for a self-powered device. The 0 ohm resistors are<br />
optional, <strong>and</strong> if not used, then connect USB UDC+ directly to the device UDC+ <strong>and</strong> connect USB<br />
UDC- directly to device UDC-. The device UDC+ <strong>and</strong> UDC- pins match the impedance of a USB<br />
cable, 90 ohms, without the use of external series resistors. You may install 0 ohm resistors on your<br />
board to compensate for minor differences between the USB cable <strong>and</strong> your board trace<br />
impedance.<br />
The 5 to 3.3 voltage divider is required since the device GPIO pins cannot exceed 3.3 V. This<br />
voltage divider can be implemented in a number of ways. The most robust <strong>and</strong> expensive solution<br />
is to use a MAX6348 Power-On-Reset device. This solution produces a very clean signal edge <strong>and</strong><br />
minimizes signal bounce. The more inexpensive solution is to use a 3.3 V line buffer with 5 V<br />
tolerant inputs. This solution does not reduce signal bounce, so software must compensate by<br />
reading the GPIO signal after it stabilizes. A third solution is to implement a signal bounce<br />
minimization circuit that is 5 V tolerant, but produces a 3.3 V signal to the GPIO pin.<br />
Note:<br />
If GPIOn <strong>and</strong> GPIOx are the same pin, never put the device to sleep while the USB cable is<br />
connected to the device. During sleep, the USB controller is in reset <strong>and</strong> will not respond to the<br />
host; after sleep, the device will not respond to its host-assigned address.<br />
Figure 4-1. Self Powered Device<br />
USB 5V<br />
5V to 3.3V<br />
GPIOn<br />
USB UDC+<br />
USB GND<br />
470K<br />
1.5K<br />
0 ohm<br />
(optional)<br />
0 ohm<br />
(optional)<br />
USB UDC-<br />
GPIOx<br />
UDC+<br />
UDC-<br />
Board GND<br />
4.1.1 Operation if GPIOn <strong>and</strong> GPIOx are Different Pins<br />
Any GPIO pins can be defined as GPIOn <strong>and</strong> GPIOx. GPIOn should be a GPIO which can bring<br />
the device out of sleep. Out of reset, configure GPIOx as an input that causes the UDC+ line to<br />
float. GPIOn is configured as an input that causes an interrupt whenever a rising or falling edge is<br />
<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide 4-1
USB Interface<br />
detected. When an interrupt occurs, software must read the GPIOn pin to determine if the cable is<br />
connected or not. GPIOn is 1 if the cable is connected or 0 if the cable is disconnected. If a USB<br />
connect is detected, then software enables the UDC peripheral <strong>and</strong> drives a 1 onto the GPIOx pin to<br />
indicate to the host PC a fast USB device is connected. If a USB disconnect is detected, then<br />
software must configure the GPIOx pin as an input, configure the GPIOn pin to detect a wakeup<br />
event, <strong>and</strong> then put the part into sleep mode.<br />
Also, at any time, you may use software to put the part into sleep mode. Before entering sleep<br />
mode, configure the GPIOx pin as an input to cause the UDC+ line to float. This looks like a<br />
disconnect to the host PC. The device can then be put into sleep mode. When the device becomes<br />
active, software must drive a 1 onto the GPIOx pin to indicate to the host PC a fast USB device has<br />
been connected.<br />
4.1.2 Operation if GPIOn <strong>and</strong> GPIOx are the Same Pin<br />
Out of reset, GPIOn is configured as an input <strong>and</strong> configured to cause an interrupt whenever a<br />
rising or falling edge is detected. When an interrupt occurs, software must read the GPIOn pin to<br />
determine if the cable is connected or not. This pin is 1 if the cable is connected or 0 if the cable is<br />
disconnected. If the USB cable is connected, then software must enable the UDC peripheral before<br />
the host sends the first USB comm<strong>and</strong>. If the USB cable is not connected, then software must<br />
configure the GPIOn pin to detect a wakeup event, <strong>and</strong> then put the part into sleep mode.<br />
4.2 Bus Powered Device<br />
The applications processor cannot support a bus powered device model. When the host sends a<br />
suspend, the device is required to consume less than 500 uA (Section 7.2.3 of the USB spec version<br />
1.1). The applications processor cannot limit its current consumption to 500 uA unless it enters<br />
sleep mode. If it enters sleep mode, all USB registers are reset <strong>and</strong> it does not respond to its hostassigned<br />
address.<br />
4-2 <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide
MultiMediaCard (MMC) 5<br />
The MultiMediaCard (MMC) is a low cost data storage <strong>and</strong> communication media. The MMC<br />
supports the translation protocol from a st<strong>and</strong>ard MMC or Serial Peripheral Interface (SPI) bus to<br />
an application bus.<br />
The MMC controller in the applications processor is compliant with The MultiMediaCard System<br />
Specification, Version 2.1. The only exception is one <strong>and</strong> three byte data transfers are not<br />
supported. The MMC controller is capable of communicating with a card in MMC or SPI mode.<br />
Your application is responsible for specifying the MMC controller communication mode.<br />
5.1 Schematics<br />
The MultiMediaCard (MMC) controller on the applications processor supports MMC <strong>and</strong> SDCard<br />
devices. (The MMC controller does not support SDCard nibble mode.) This section presents<br />
several options on how to connect each type of device to the controller.<br />
5.1.1 Signal Description<br />
MMC controller signal functions are described in Table 5-1.<br />
Table 5-1. MMC Signal Description<br />
Signal Name Input/Output Description<br />
MMCLK Output Clock signal to MMC<br />
MMCMD BiDirectional Comm<strong>and</strong> line<br />
MMDAT BiDirectional Data line<br />
MMCCS0 Output Chip Select 0<br />
MMCCS1 Output Chip Select 1<br />
The MMCLK, MMCCS0, <strong>and</strong> MMCCS1 signals are routed through alternate functions within the<br />
applications processor general purpose input/output (GPIO) module. Each of these signals can be<br />
programmed to a particular GPIO pin.<br />
The signals defined in The MultiMediaCard System Specification for an MMC device are CLK,<br />
CMD, <strong>and</strong> DAT which correspond to the MMCLK, MMCMD, <strong>and</strong> MMDAT in the applications<br />
processor, respectively. The two chip selects in the controller are for the MMC SPI mode <strong>and</strong><br />
correspond to the reserved pin of two different devices, defined in the specification.<br />
The signals defined in the Physical Layer Specification of the SD Memory Card Specifications for<br />
an SDCard device are CLK, CMD, <strong>and</strong> DAT0-DAT3. The obvious difference is the number of<br />
DAT signals. In addition, the socket for an SDCard contains mechanical switches for write protect<br />
(WP) <strong>and</strong> card detect (CD). For an SDCard to be connected to the MMC controller, only one data<br />
line, DAT0, is used. Otherwise the signal mapping remains the same as an MMC device. The WP<br />
<strong>and</strong> CD switches on the socket are discussed in Section 5.1.2, “How to Wire” on page 5-2.<br />
<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide 5-1
MultiMediaCard (MMC)<br />
5.1.2 How to Wire<br />
Notice in the example schematic (Figure 5-1, “<strong>Applications</strong> Processor MMC <strong>and</strong> SDCard Signal<br />
Connections” on page 5-3) an SDCard socket is used. The signals on the socket are defined in<br />
Table 5-2.<br />
Table 5-2. SDCard Socket Signals<br />
Signal Name Pin #<br />
DAT3 1<br />
CMD 2<br />
VSS1 3<br />
VDD 4<br />
CLK 5<br />
VSS2 6<br />
DAT0 7<br />
DAT1 8<br />
DAT2 9<br />
As stated previously, the <strong>PXA250</strong> MMC controller can be connected to either an MMC device or<br />
an SDCard device, but you are limited to which device installs in which socket. Refer to Table 5-3<br />
for information on sockets <strong>and</strong> device supported by the MMC controller.<br />
Table 5-3. MMC Controller Supported Sockets <strong>and</strong> Devices<br />
Sockets<br />
Devices Supported<br />
SDCard socket<br />
MMC socket<br />
SDCard device<br />
MMC device<br />
MMC device<br />
Figure 5-1 is a schematic that supports both MMC <strong>and</strong> SDCard devices. In the schematic, the<br />
signals SA_MMCLK, SA_MMCMD, <strong>and</strong> SA_DAT correspond to the applications processor<br />
signals MMCLK, MMCMD, <strong>and</strong> MMDAT, respectively. These three signals are also directly<br />
connected to the socket.<br />
5-2 <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide
MultiMediaCard (MMC)<br />
Figure 5-1. <strong>Applications</strong> Processor MMC <strong>and</strong> SDCard Signal Connections<br />
J10<br />
DC3P3V<br />
CHECK II<br />
Bottom Mount<br />
DAT2 0<br />
CD_DAT3 1<br />
CMD<br />
2<br />
VSS1<br />
3<br />
VDD<br />
4<br />
CLK<br />
5<br />
VSS2<br />
6<br />
DAT0<br />
7<br />
DAT1<br />
8<br />
WP<br />
COMM<br />
CD<br />
10<br />
11<br />
12<br />
R229<br />
100K<br />
DC3P3V<br />
MMC_WP<br />
MMC_C50<br />
R147<br />
SA_MMCCLK<br />
SA_MMDAT<br />
R150<br />
47.5K<br />
DC3P3V<br />
10K<br />
R226<br />
C91<br />
0K<br />
SA_MMCMD<br />
0.1uF<br />
R225<br />
0K<br />
DNI<br />
IF<br />
SD<br />
CARD Selection Resistors <strong>and</strong> Values<br />
Resistors SDCard MMC<br />
R226<br />
R227<br />
R225<br />
R228<br />
DNI<br />
DNI<br />
0<br />
100K<br />
0<br />
100K<br />
DNI<br />
DNI<br />
DNI IF MMC<br />
R227<br />
R228<br />
DC3P3V<br />
100K<br />
100K<br />
MMC_PWR<br />
DNI<br />
IF<br />
SD<br />
nMMC_DETECT<br />
DNI<br />
IF<br />
MMC<br />
U27<br />
MMC_ON<br />
DC5P5V<br />
1<br />
2<br />
3<br />
MIC5207- 3.38M5<br />
3.3V LDO REG 180ns<br />
VIN<br />
GND<br />
EN<br />
LE33<br />
VOUT<br />
BYP<br />
5<br />
4<br />
4.7uF<br />
1<br />
C92<br />
MMC_PWR<br />
2<br />
A8698-01<br />
MMC_CS0, which corresponds to the applications processor MMCCS0 signal, is connected to the<br />
socket at pin 1. This connection is the SPI mode chip select <strong>and</strong> is available on both MMC <strong>and</strong><br />
SDCard. This pin is also labeled DAT3. DAT3 is only used with an SDCard in SDCard mode <strong>and</strong><br />
not available on the applications processor MMC controller.<br />
The signals DAT1 <strong>and</strong> DAT2 are not connected because these are specific to SDCard operation in<br />
SDCard mode.<br />
<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide 5-3
MultiMediaCard (MMC)<br />
Three other signals shown on the connector are COMM <strong>and</strong> the mechanical switches write protect<br />
(WP) <strong>and</strong> card detect (CD). WP <strong>and</strong> CD are both connected to COMM via a mechanical switch<br />
inside the socket when a device is inserted.<br />
Three other signals shown on the connector are COMM <strong>and</strong> the mechanical switches WP <strong>and</strong> CD.<br />
When a device is inserted in the example schematic (Figure 5-1), WP may be <strong>and</strong> CD is connected<br />
to COMM via a mechanical switch inside the socket<br />
SDCard devices have a write protect tab. Depending on the position of the tab, the WP signal may<br />
or may not be connected to the COMM signal. Connect the WP signal to a CPLD or other device<br />
capable of indicating to the driver software that the card is write protected. In this example,<br />
COMM is tied to a VCC <strong>and</strong> WP has a pull-down resistor. This causes a rising edge when the tab is<br />
in the write protect position <strong>and</strong> the WP signal remains low when the tab is in the read/write<br />
position.<br />
The CD signal, MMC_DETECT, indicates to the MMC controller when a card is installed. It is<br />
used for both an SDCard socket <strong>and</strong> an MMC socket. Since the MMC socket does not have the<br />
mechanical CD switch, other measures must be taken to produce a card detect. Thus, the SDCard<br />
<strong>and</strong> MMC cases are discussed separately.<br />
Note:<br />
While this schematic shows two ways to create a card detect, it is recommended that an SDCard<br />
socket be used if a card detect <strong>and</strong> write protection signal are desired even if only MMC devices<br />
are being used.<br />
5.1.2.1 SDCard Socket<br />
When using Figure 5-1, “<strong>Applications</strong> Processor MMC <strong>and</strong> SDCard Signal Connections” on<br />
page 5-3 as a template for your SDCard circuit design, all resistors labeled “DNI IF SD” should not<br />
be installed <strong>and</strong> all resistors labeled “DNI IF MMC” should be installed in the circuit. Removing<br />
R226 <strong>and</strong> inserting R225 causes the VSS2 signal on pin 6 to be tied to ground. Also, the SDCard<br />
needs a pull-down resistor in position R228.<br />
SDCard sockets have a card detect switch internal to the socket. The CD signal is physically<br />
connected to the COMM signal. Connect the CD signal to a CPLD or other device capable of<br />
indicating to the driver software that a card has been inserted in the socket. In this example,<br />
COMM is tied to a V CC <strong>and</strong> CD has a pull-down resistor. This causes a rising edge on CD when a<br />
card is inserted while the CD signal remains low if no card is in the socket.<br />
5.1.2.2 MMC Socket<br />
When using Figure 5-1, “<strong>Applications</strong> Processor MMC <strong>and</strong> SDCard Signal Connections” on<br />
page 5-3 as a template for your MMC circuit design, all resistors labeled “DNI IF MMC” should<br />
not be installed <strong>and</strong> all resistors labeled “DNI IF SD” should be installed in the circuit. This causes<br />
the VSS2 signal on pin 6 to be pulled-up through resistor R227.<br />
Unlike SDCard sockets, MMC sockets do not have a card detect or write protect switch. In order to<br />
implement this, a pull-up is placed on the VSS2 signal (pin 6 of the socket.) Since VSS2 <strong>and</strong> VSS1<br />
are connected internally on the MMC device, the signal called nMMC_DETECT on the schematic<br />
is driven low when the MMC device is inserted.<br />
5-4 <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide
MultiMediaCard (MMC)<br />
Warning:<br />
Connecting VSS2 to something other than the power supply ground violates The MultiMediaCard<br />
System Specification, Version 2.1. Because the MMC specification does not state that VSS1 <strong>and</strong><br />
VSS2 must be connected internal to the MMC device, the design in Figure 5-1 may not work with<br />
all MMC devices. Use caution when using the card detection method shown in Figure 5-1.<br />
5.1.3 Simplified Schematic<br />
Figure 5-2 shows another SDCard socket. In this case, all applications processor signals are<br />
connected to the socket. This socket does not have a common signal for the write protect <strong>and</strong> card<br />
detect <strong>and</strong> are connected to the two tabs shown on the left side of the diagram. Inserting a card into<br />
the socket may cause the write protect signal <strong>and</strong> will cause the card detect signal to change states<br />
<strong>and</strong> must be interpreted by the CPLD software.<br />
Figure 5-2. <strong>Applications</strong> Processor MMC to SDCard Simplified Signal Connection<br />
+3.3V<br />
12 13<br />
ESD<br />
GND<br />
Jx<br />
WP<br />
CD<br />
DAT1<br />
DAT0<br />
VSS2<br />
CLK<br />
VDD<br />
VSS1<br />
CMD<br />
CD/DAT3<br />
DAT2<br />
11<br />
10<br />
5638 SDMC_NORMAL_SPRG_EJCT<br />
Kyoc 10 5638 009 353 833<br />
8<br />
7<br />
6<br />
5<br />
4<br />
3<br />
2<br />
1<br />
9<br />
Rx<br />
10K Ω<br />
5% 0.1W<br />
Rx<br />
10K Ω<br />
5% 0.1W<br />
Rx<br />
10K Ω<br />
5% 0.1W<br />
Rx<br />
10K Ω<br />
5% 0.1W<br />
SD_WP<br />
SD_CD<br />
MMDAT<br />
MMCLK<br />
MMCMD<br />
MMCCS0<br />
A8699-01<br />
<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide 5-5
MultiMediaCard (MMC)<br />
5.1.4 Pull-up <strong>and</strong> Pull-down<br />
Table 5-4 <strong>and</strong> Table 5-5 show the pull-up <strong>and</strong> pull-down resistors required for SDCard <strong>and</strong> MMC<br />
devices according to their respective specifications.<br />
Table 5-4. SDCard Pull-up <strong>and</strong> Pull-down Resistors<br />
Signal Pull-up or Pull-down Min Max Remark<br />
CMD pull-up 10kΩ 100kΩ Prevents bus floating<br />
DAT0-DAT3 pull-up 10kΩ 100kΩ Prevents bus floating<br />
WP 1 pull-up — — Any value sufficient to prevent bus floating<br />
NOTE: 1. This resistor is shown in the specification but the value is not specified<br />
Table 5-5. MMC Pull-up <strong>and</strong> Pull-down Resistors<br />
Signal Pull-up or Pull-down Min Max Remark<br />
CMD pull-up 4.7kΩ 100kΩ Prevents bus floating<br />
DAT pull-up 50kΩ 100kΩ Prevents bus floating<br />
5.2 Utilized Features<br />
The applications processor MultiMediaCard controller has these features:<br />
• Data transfer rates as fast as 20 Mbps<br />
• A16 bit response FIFO<br />
• Dual receive data FIFOs<br />
• Dual transmit FIFOs<br />
• Support for two MMCs in either MMC or SPI mode<br />
The sample schematics in this section support MMC <strong>and</strong> SDCard <strong>and</strong> are configured to use MMC<br />
or SPI mode.<br />
The applications processor MultiMediaCard controller <strong>and</strong> the MMC device have the same<br />
maximum data rate, 20 Mbps, so their communication rates are compatible. However, because the<br />
maximum applications processor MultiMediaCard controller data rate is 20 Mbps <strong>and</strong> the<br />
maximum SDCard data rate is 25 Mbps, SDCard devices are not utilized to their fullest extent.<br />
The circuit designs presented in this guide (Figure 5-1 <strong>and</strong> Figure 5-2) only show support for one<br />
SDCard or MMC device, but the applications processor MultiMediaCard controller h<strong>and</strong>les as<br />
many as two devices.<br />
5-6 <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide
AC97 6<br />
The AC97 controller unit (ACUNIT) connects audio chips <strong>and</strong> codecs to the applications<br />
processor. It uses a six-wire interface to transmit <strong>and</strong> receive data from AC97 2.0 compliant<br />
codecs. The AC97 port is a bidirectional, serial PCM digital stream. A maximum of two codecs<br />
may be connected to the ACUNIT.<br />
6.1 Schematics<br />
The schematics for an AC97 connection are shown in Figure 6-1. The primary codec supplies the<br />
12.288 MHz clock to the AC97. This clock is then driven into the ACUNIT on the applications<br />
processor <strong>and</strong> the AC97 Secondary Codec.<br />
Figure 6-1. AC97 connection<br />
nACRESET<br />
SDATA_OUT<br />
<strong>PXA250</strong><br />
AC97<br />
Controller<br />
SYNC (48KHz)<br />
SDATA_IN_0<br />
SDATA_IN_1<br />
BITCLK (12.288MHz)<br />
AC97<br />
Primary<br />
CODEC<br />
AC97<br />
Secondary<br />
Codec<br />
<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide 6-1
AC97<br />
6.2 Layout<br />
Because of the analog/digital nature of the codecs, it is important that proper mixed-signal layout<br />
procedures be followed. <strong>Intel</strong> recommends you follow the layout recommendations given in your<br />
Codec datasheet. Some general recommendations are:<br />
• Use a separate power supply for the analog audio portion of the design.<br />
• Place a digital power/ground plane keep-out underneath the analog portion. Use a separate<br />
analog ground plane. You can create an isl<strong>and</strong> inside the keep-out. Connect the digital ground<br />
pins of the codec to the digital ground. Keep the two ground planes on the same layer, with at<br />
least 1/8 of an inch separation between them.<br />
• Connect the two ground planes underneath your codec with a 0 ohm jumper. Add optional Do<br />
Not Populate 0 ohm jumpers between analog <strong>and</strong> digital ground at the power supply.<br />
Excessive noise on the board may be reduced by installing the 0 ohm resistor.<br />
• Do not to route digital signals underneath the analog portion. Digital traces must go over the<br />
digital ground plane, analog traces over the analog plane.<br />
• Buffer any digital signals to or from the codec that go off the board, for example, if your codec<br />
is on a daughter card.<br />
• Fill the areas between analog traces with copper tied to the analog ground. Fill the regions<br />
between digital traces with copper tied to the digital ground.<br />
• Locate the decoupling capacitors for the analog portion as close to the codec as possible.<br />
6-2 <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide
I 2 C 7<br />
The Inter-Integrated Circuit (I 2 C) bus interface unit lets the applications processor serve as a<br />
master <strong>and</strong> slave device residing on the I 2 C bus. The I 2 C bus is a serial bus developed by Philips<br />
Corporation consisting of a two-pin interface. SDA is the serial data line <strong>and</strong> SCL is the serial<br />
clock line.<br />
Using the I 2 C bus lets the applications processor interface to other I 2 C peripherals <strong>and</strong><br />
microcontrollers for system management functions. The serial bus requires a minimum of<br />
hardware for an economical system to relay status <strong>and</strong> reliability information to an external device.<br />
The I 2 C bus interface unit is a peripheral device that resides on the applications processor internal<br />
bus. Data is transmitted to <strong>and</strong> received from the I 2 C bus via a buffered interface. Control <strong>and</strong><br />
status information is relayed through a set of memory-mapped registers. Refer to the I 2 C Bus<br />
Specification for complete details on I 2 C bus operation.<br />
7.1 Schematics<br />
The I 2 C bus is used by many different applications. This reference guide presents two possible<br />
methods for using the I 2 C bus interface. The first method controls a digital-to-analog converter<br />
(DAC) to vary the DC voltage to the processor core. The second method exp<strong>and</strong>s the capabilities of<br />
an existing compact flash socket.<br />
7.1.1 Signal Description<br />
The I 2 C bus interface unit signals are SDA <strong>and</strong> SCL. Table 7-1 describes the function of each<br />
signal.<br />
Table 7-1. I 2 C Signal Description<br />
Signal Name Input/Output Description<br />
SDA BiDirectional Serial data<br />
SCL BiDirectional Serial clock<br />
The I 2 C bus serial operation uses an open-drain, wired-AND bus structure, which allows multiple<br />
devices to drive the bus lines <strong>and</strong> to communicate status about events such as arbitration, wait<br />
states, error conditions <strong>and</strong> so on. For example, when a master drives the clock (SCL) line during a<br />
data transfer, it transfers a bit on every instance that the clock is high. When the slave is unable to<br />
accept or drive data at the rate that the master is requesting, the slave can hold the clock line low<br />
between the high states to insert a wait interval. The master’s clock can only be altered by a slow<br />
slave peripheral keeping the clock line low or by another master during arbitration.<br />
The I 2 C bus lets you design a multi-master system; meaning more than one device can initiate data<br />
transfers at the same time. To support this feature, the I 2 C bus arbitration relies on the wired-AND<br />
connection of all I 2 C interfaces to the I 2 C bus. Two masters can drive the bus simultaneously<br />
provided they are driving identical data. The first master to drive SDA high while another master<br />
drives SDA low loses the arbitration. The SCL line consists of a synchronized combination of<br />
clocks generated by the masters using the wired-AND connection to the SCL line.<br />
<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide 7-1
I2C<br />
7.1.2 Digital-to-Analog Converter (DAC)<br />
Figure 7-1 shows the schematic for connecting the I 2 C interface to a Linear Technology<br />
micropower DAC. The DAC output is connected to the buck converter feedback path <strong>and</strong> is<br />
controlled by the I 2 C bus interface unit. The DAC can modify the voltage of the feedback path,<br />
which effects the processor core voltage.<br />
Figure 7-1. Linear Technology DAC with I 2 C Interface<br />
DC3P3V<br />
R165 1.00M<br />
U30<br />
4<br />
VCC<br />
LTC1663<br />
SA_I2C_SDA<br />
1<br />
SDA<br />
VOUT<br />
3<br />
SA_I2C_SCL<br />
5<br />
SCL<br />
GND<br />
2<br />
LTEP<br />
LTC1663C35<br />
A8752-01<br />
The signals SA_I2C_SDA <strong>and</strong> SA_I2C_SCL correspond to the applications processor signals<br />
SDA <strong>and</strong> SCL, respectively.<br />
7.1.3 Other Uses of I 2 C<br />
Figure 7-2 shows the I 2 C signals passing through an analog switch to a compact flash socket. Since<br />
the CF socket has all of the signals to support two CF cards, <strong>and</strong> this design only uses one CF card,<br />
the signals meant for a second card are being used for alternate functions. If you decide not to use a<br />
CF card, a different application using a CF card socket could be designed to utilize the I 2 C bus<br />
interface unit. If this alternate function is used, the I 2 C bus can be enabled to the CF socket by<br />
asserting the signal SA_I2C_ENAB shown in the diagram. If the user decides to use a CF Card,<br />
negate the SA_I2C_ENAB signal so the I 2 C bus traffic does not interfere with the CF card.<br />
Note:<br />
The CF card socket is disabled if a device is inserted in the expansion bus.<br />
7-2 <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide
.<br />
I2C<br />
Figure 7-2. Using an Analog Switch to Allow a Second CF Card<br />
DC3P3V<br />
U26<br />
MAX4547<br />
V*<br />
2<br />
SA_I2C_SCL<br />
8<br />
COM_1<br />
7<br />
IN_7<br />
NC_1<br />
1<br />
CF_I2C_SCL<br />
SA_I2C_SDA<br />
SA_I2C_ENAB<br />
4<br />
3<br />
COM_7<br />
IN_2<br />
NC_2<br />
GND<br />
5<br />
6<br />
CI_I2C_SDA<br />
AAAF<br />
A8750-01<br />
7.1.4 Pull-Ups <strong>and</strong> Pull-Downs<br />
The I 2 C Bus Specification, available from Philips Corporation, states:<br />
The external pull-up devices connected to the bus lines must be adapted to accommodate the shorter<br />
maximum permissible rise time for the Fast-mode I 2 C-bus. For bus loads up to 200 pF, the pull-up<br />
device for each bus line can be a resistor; for bus loads between 200 pF <strong>and</strong> 400 pF, the pull-up device<br />
can be a current source (3 mA max.) or a switched resistor circuit.<br />
The design presented in this guide is not intended for loads larger than 200pF, so the pull-up device is a<br />
resistor as shown in Figure 7-3.<br />
Figure 7-3. I 2 C Pull-Ups <strong>and</strong> Pull-Downs<br />
DC3P3V<br />
SA_I2C_SCL<br />
SA_I2C_SDA<br />
R4<br />
4.99K<br />
R5<br />
4.99K<br />
A8751-01<br />
<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide 7-3
I2C<br />
The actual value of the pull-up is system dependant <strong>and</strong> a guide is presented in the I 2 C Bus<br />
Specification on determining the maximum <strong>and</strong> minimum resistors to use when the system is<br />
intended for st<strong>and</strong>ard or fast-mode I 2 C bus devices.<br />
7.2 Utilized Features<br />
The applications processor I 2 C bus interface unit is compatible with the two pin interface<br />
developed by Phillips Corporation. A complete list of features <strong>and</strong> capabilities can be found in the<br />
I 2 C Bus Specification.<br />
7-4 <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide
Power <strong>and</strong> Clocking 8<br />
8.1 Operating Conditions<br />
Table 8-1 shows voltage, frequency, <strong>and</strong> temperature specifications for the applications processor<br />
for four different ranges. The temperature specification for each range is constant; the frequency<br />
range is operation voltage dependent. On a prototype design, the VCC/PLL_VCC regulator should<br />
have a range from 0.85 V to 1.65 V. PLL_VCC <strong>and</strong> VCC must be connected together on the board<br />
or driven by the same supply.<br />
Table 8-1. Voltage, Temperature, <strong>and</strong> Frequency Electrical Specifications<br />
Symbol Description Min Typical Max<br />
t A Ambient Temperature -40°C — 85° C<br />
V VSS VSS, VSSN, VSSQ Voltage -0.3 V 0V 0.3 V<br />
V VCCQ VCCQ 3.0 V 3.3 V 3.6 V<br />
V VCCN_H VCCN @ 3.3V 3.0 V 3.3 V 3.6 V<br />
V VCCN_L VCCN @ 2.5V 2.375 V 2.5 V 2.625 V<br />
Low Voltage Range (<strong>PXA210</strong> <strong>and</strong> <strong>PXA250</strong>)<br />
V VCC_L VCC, PLL_VCC Voltage, Low Range 0.8075 V 0.85 V 0.935 V<br />
f TURBO_L Turbo Mode Frequency, Low Range 99.5 MHz — 132.7 MHz<br />
f SDRAM_L External Synchronous Memory Frequency, Low Range — — 66.4 MHz<br />
Medium Voltage Range (<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong>)<br />
V VCC_M VCC, PLL_VCC Voltage, Mid Range 0.9 V 1.0 V 1.1 V<br />
f TURBO_M Turbo Mode Frequency, Mid Range 99.5 MHz — 199.1 MHz<br />
f SDRAM_M External Synchronous Memory Frequency, Mid Range — — 99.5 MHz<br />
High Voltage Range (<strong>PXA250</strong> applications processor only)<br />
V VCC_H VCC, PLL_VCC Voltage, High Range 1.0 V 1.1 V 1.21 V<br />
f TURBO_H Turbo Mode Frequency, High Range 99.5 MHz — 298.7 MHz<br />
f SDRAM_H External Synchronous Memory Frequency, High Range — — 99.5 MHz<br />
Peak Voltage Range (<strong>PXA250</strong> applications processor only)<br />
V VCC_P VCC, PLL_VCC Voltage, Peak Range 1.17 V 1.3 V 1.43 V<br />
f TURBO_P Turbo Mode Frequency, Peak Range 99.5 MHz — 398.2 MHz<br />
f SDRAM_P External Synchronous Memory Frequency, Peak Range — — 99.5 MHz<br />
NOTE: When VCCN=2.5 V, the I/O signals that are supplied by VCCN are 2.5 V tolerant only. Do not apply 3.3 V to any pin<br />
supplied by VCCN in this case.<br />
<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide 8-1
Power <strong>and</strong> Clocking<br />
8.2 Electrical Specifications<br />
Table 8-2 provides the Absolute Maximum ratings for the applications processor. These parameters<br />
may not be exceeded or the part may be permanently damaged. Operation at Absolute Maximum<br />
Ratings is not guaranteed.<br />
Table 8-2. Absolute Maximum Ratings<br />
Symbol Description Min Max<br />
T S Storage Temperature -40° C 125° C<br />
V SS_O<br />
V CC_O<br />
Offset Voltage between any two VSS pins<br />
(VSS, VSSQ, VSSN)<br />
Offset Voltage between any of the following pins:<br />
VCCQ, VCCN<br />
-0.3 V 0.3 V<br />
-0.3 V 0.3 V<br />
V CC_HV<br />
Voltage Applied to High Voltage Supplies<br />
(VCCQ, VCCN)<br />
VSS-0.3 V<br />
VSS+4.0 V<br />
V CC_LV<br />
Voltage Applied to Low Voltage Supplies<br />
(VCC, PLL_VCC)<br />
VSS-0.3 V<br />
VSS+1.45 V<br />
V IP Voltage Applied to non-Supply pins except XTAL pins VSS-0.3 V<br />
max of<br />
VCCQ+0.3 V,<br />
VSS+4.0 V<br />
V IP_X<br />
Voltage Applied to XTAL pins<br />
(PXTAL, PEXTAL, TXTAL, TEXTAL)<br />
VSS-0.3 V<br />
max of<br />
VCC+0.3 V,<br />
VSS+1.45 V<br />
V ESD<br />
Maximum ESD stress voltage, Human Body Model;<br />
Any pin to any supply pin, either polarity, or<br />
Any pin to all non-supply pins together, either polarity.<br />
Three stresses maximum.<br />
2000 V<br />
I EOS Maximum DC Input Current (Electrical Overstress) for any non-supply pin 5mA<br />
8.3 Power Consumption Specifications<br />
Power consumption on any highly integrated device is extremely dependent on the operating<br />
voltage, external switching activity, <strong>and</strong> external loading (shown in Table 8-3, “Power<br />
Consumption Specifications” on page 8-3). Because power consumption on the applications<br />
processor is optimized, power varies based on which functions are being performed <strong>and</strong> by the data<br />
<strong>and</strong> frequency requirements of the module.<br />
The maximum power consumption specification is determined by all units running at their<br />
maximum: processor speed, voltage, <strong>and</strong> loading conditions. This method generates a conservative<br />
power consumption value; however, power supply <strong>and</strong> thermal management design requires the<br />
highest possible power consumption for robust design.The applications processor’s maximum<br />
power consumption is calculated using the following conditions:<br />
• All peripheral units operating at maximum frequency <strong>and</strong> size configuration<br />
• All I/O loads maximum (50pF for Memory interface, 100pF for peripherals)<br />
• Core operating at worst case power scenario (hit rates adjusted for worst power)<br />
• All voltages at maximum of range<br />
8-2 <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide
Power <strong>and</strong> Clocking<br />
Since few systems operate at maximum loading, performance, <strong>and</strong> voltage, a more optimal system<br />
design requires more typical power consumption parameters. These parameters are important when<br />
considering battery size <strong>and</strong> optimizing regulator efficiency. Typical systems operate with fewer<br />
modules active <strong>and</strong> at nominal voltage <strong>and</strong> load. Typical power consumption for the applications<br />
processor is calculated using these conditions:<br />
• SSP, STUART, USB, PWM, Timer, I2S peripherals operating<br />
• LCD enabled with 320x240x16bit color<br />
• MMC, AC97, BTUART, FFUART, ICP, I2C peripherals disabled<br />
• I/O loads at nominal (35pf for all pins)<br />
• Core operating at 98% Instruction Hit Rate, 95% Data Hit Rate<br />
• All voltages at nominal value<br />
The individual power supply specifications add up to more than the total because the operating<br />
conditions which cause maximum power consumption on each supply are sometimes mutually<br />
exclusive.<br />
Table 8-3. Power Consumption Specifications (Sheet 1 of 2)<br />
Symbol Description Min 1 Typical 1 Max 1<br />
Package, Frequency, <strong>and</strong> Voltage Range Independent Power Supplies<br />
P VCCQ Power from VCCQ Supply — 16 mW 115 mW<br />
Low Voltage Range (<strong>PXA210</strong> <strong>and</strong> <strong>PXA250</strong>)<br />
P T_L Total Power, Low Range — 250 mW 550 mW<br />
P VCC_L Power from VCC Supply, Low Range — 110 mW 65 mW<br />
P VCCN_L<br />
@2.5V<br />
P VCCN_L<br />
@3.3V<br />
Power from VCCN Supply, Low Range — 65 mW 145 mW<br />
Power from VCCN Supply, Low Range — 120 mW 250 mW<br />
PT_IDLE_L Total Power, IDLE Mode, Low Range — 110mW —<br />
Medium Voltage Range (<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong>)<br />
P T_MM Total Power, Mid Range (<strong>PXA210</strong> applications processor) — 350 mW 690 mW<br />
P T_MB Total Power, Mid Range (<strong>PXA250</strong> applications processor) — 420 mW 840 mW<br />
P VCC_M Power from VCC Supply, Mid Range — 180 mW 130 mW<br />
P VCCN_MM<br />
P VCCN_MB<br />
@2.5V<br />
P VCCN_MB<br />
@3.3V<br />
Power from VCCN Supply, Mid Range (<strong>PXA210</strong> applications<br />
processor)<br />
Power from VCCN Supply, Mid Range (<strong>PXA250</strong> applications<br />
processor)<br />
Power from VCCN Supply, Mid Range (<strong>PXA250</strong> applications<br />
processor)<br />
— 160 mW 325 mW<br />
— 100 mW 250 mW<br />
— 160 mW 440 mW<br />
PT_IDLE_M Total Power, IDLE Mode, Medium Range — 110mW —<br />
High Voltage Range (<strong>PXA250</strong> applications processor only)<br />
P T_HB Total Power, High Range (<strong>PXA250</strong> applications processor) — 450 mW 890 mW<br />
P VCC_H Power from VCC Supply, High Range — 275 mW 220 mW<br />
<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide 8-3
Power <strong>and</strong> Clocking<br />
Table 8-3. Power Consumption Specifications (Sheet 2 of 2)<br />
Symbol Description Min 1 Typical 1 Max 1<br />
P VCCN_HB<br />
@2.5V<br />
P VCCN_HB<br />
@3.3V<br />
Power from VCCN Supply, High Range (<strong>PXA250</strong> applications<br />
processor)<br />
Power from VCCN Supply, High Range (<strong>PXA250</strong> applications<br />
processor)<br />
— 115 mW 250 mW<br />
— 160 mW 440 mW<br />
PT_IDLE_H Total Power, IDLE Mode, High Range — 135mW —<br />
Peak Voltage Range (<strong>PXA250</strong> applications processor only)<br />
P T_P Total Power, Peak Range — 635 mW 950 mW<br />
P VCC_P Power from VCC Supply, Peak Range — 470 mW 360 mW<br />
P VCCN_P<br />
@2.5V<br />
P VCCN_P<br />
@3.3V<br />
Power from VCCN Supply, Peak Range — 115 mW 255 mW<br />
Power from VCCN Supply, Peak Range — 160 mW 440 mW<br />
PT_IDLE_H Total Power, IDLE Mode, High Range — 185mW —<br />
NOTE:<br />
1. These numbers are pre-silicon estimates, <strong>and</strong> will be replaced with the correct values when characterization is complete.<br />
8.4 Oscillator Electrical Specifications<br />
The applications processor contains two oscillators – 32.768 kHz <strong>and</strong> 3.6864 MHz; each chosen<br />
for a specific crystal. When choosing a crystal, match the crystal parameters as closely as possible.<br />
8.4.1 32.768 kHz Oscillator Specifications<br />
The 32.768 kHz Oscillator is connected between the TXTAL (amplifier input) <strong>and</strong> TEXTAL<br />
(amplified output). The 32.768 kHz specifications are shown in Table 8-4.<br />
Table 8-4. 32.768 kHz Oscillator Specifications (Sheet 1 of 2)<br />
Symbol Description Min Typical Max<br />
Crystal Specifications - Typical is FOX NC38<br />
F XT Crystal Frequency, TXTAL/TEXTAL — 32.768 kHz —<br />
L MT Motional Inductance, TXTAL/TEXTAL — 6827.81 H —<br />
C MT Motional Capacitance, TXTAL/TEXTAL — 3.455 fF —<br />
R MT Motional Resistance, TXTAL/TEXTAL 6kΩ 16 kΩ 35 kΩ<br />
C OT Shunt Capacitance TXTAL to TEXTAL — 1.6 pF —<br />
C LT Load Capacitance TXTAL/TEXTAL — 12.5 pF —<br />
Amplifier Specifications<br />
V IH_X Input High Voltage, TXTAL 0.8 V*VCC — VCC<br />
V IL_X Input Low Voltage, TXTAL VSS — 0.2 V*VCC<br />
I IN_XT Input Leakage, TXTAL — — 1 µA<br />
C IN_XT Input Capacitance, TXTAL/TEXTAL — 18 pF 25 pF<br />
8-4 <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide
Power <strong>and</strong> Clocking<br />
Table 8-4. 32.768 kHz Oscillator Specifications (Sheet 2 of 2)<br />
Symbol Description Min Typical Max<br />
t S_XT Stabilization Time 2s — 10 s<br />
Board Specifications<br />
R P_XT Parasitic Resistance, TXTAL/TEXTAL to any node 20 MΩ — —<br />
C P_XT Parasitic Capacitance, TXTAL/TEXTAL, total — — 5pF<br />
C OP_XT Parasitic Shunt Capacitance, TXTAL to TEXTAL — — 0.4 pF<br />
To drive the 32.768 kHz crystal pins from an external source:<br />
• Drive the TEXTAL pin with a digital signal that has a low level near 0 V <strong>and</strong> a high level near<br />
VCC. Do not exceed VCC or go below VSS by more than 100 mV. The minimum slew rate is<br />
1V per µs. The maximum current drawn by the external clock source when the clock is at its<br />
maximum positive voltage should be about 1mA.<br />
• Float the TXTAL pin or drive it complementary to the TEXTAL pin, using the same voltage<br />
level, slew rate, <strong>and</strong> input current restrictions.<br />
8.4.2 3.6864 MHz Oscillator Specifications<br />
The 3.6864 MHz Oscillator is connected between the PXTAL (amplifier input) <strong>and</strong> PEXTAL<br />
(amplified output). The 3.6864 MHz specifications are shown in Table 8-5<br />
Table 8-5. 3.6864 MHz Oscillator Specifications<br />
Symbol Description Min Typical Max<br />
Crystal Specifications - Typical is FOX HC49S<br />
F XP Crystal Frequency, PXTAL/PEXTAL — 3.6864 MHz —<br />
L MP Motional Inductance, PXTAL/PEXTAL — 0.50593 H —<br />
C MP Motional Capacitance, PXTAL/PEXTAL — 3.68488 fF —<br />
R MP Motional Resistance, PXTAL/PEXTAL 50 Ω 99.3 Ω 200 Ω<br />
C OP Shunt Capacitance PXTAL to PEXTAL — 1.7 pF —<br />
C LP Load Capacitance PXTAL/PEXTAL — 20 pF —<br />
Amplifier Specifications<br />
V IH_X Input High Voltage, PXTAL 0.8V*VCC — VCC<br />
V IL_X Input Low Voltage, PXTAL VSS — 0.2 V*VCC<br />
I IN_XP Input Leakage, PXTAL — — 10 µA<br />
C IN_XP Input Capacitance, PXTAL/PEXTAL — 40 pF 50 pF<br />
t S_XP Stabilization Time 17.8 ms — 67.8 ms<br />
Board Specifications<br />
R P_XP Parasitic Resistance, PXTAL/PEXTAL to any node 20 MΩ — —<br />
C P_XP Parasitic Capacitance, PXTAL/PEXTAL, total — — 5pF<br />
C OP_XP Parasitic Shunt Capacitance, PXTAL to PEXTAL — — 0.4 pF<br />
To drive the 3.6864 MHz crystal pins from an external source:<br />
<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide 8-5
Power <strong>and</strong> Clocking<br />
• Drive the PEXTAL pin with a digital signal that has a low level near 0 V <strong>and</strong> a high level near<br />
VCC. Do not exceed VCC or go below VSS by more than 100 mV. The minimum slew rate is<br />
1 V per 100 ns. The maximum current drawn by the external clock source when the clock is at<br />
its maximum positive voltage should be about 1 mA.<br />
• Float the PXTAL pin or drive it complementary to the PEXTAL pin, using the same voltage<br />
level, slew rate, <strong>and</strong> input current restrictions. If floated, some degree of noise susceptibility<br />
will be introduced in the system, <strong>and</strong> it is therefore not recommended.<br />
8.5 Reset <strong>and</strong> Power AC Timing Specifications<br />
The applications processor asserts the nRESET_OUT pin in one of several modes:<br />
• Power On<br />
• Hardware Reset<br />
• Watchdog Reset<br />
• GPIO Reset<br />
• Sleep Mode<br />
The following sections give the timing <strong>and</strong> other specifications for the entry <strong>and</strong> exit of these<br />
modes.<br />
8.5.1 Power Supply Connectivity<br />
The <strong>PXA250</strong> applications processor requires two or three externally-supplied voltage levels.<br />
VCCQ requires high voltage, VCCN requires high or medium voltage, <strong>and</strong> VCC <strong>and</strong> PLL_VCC<br />
require low voltage. PLL_VCC must be separated from other low voltage supplies. Depending on<br />
the availability of independent regulator outputs <strong>and</strong> the desired memory voltage, VCCQ may have<br />
to be separated from VCCN. VCCN does not have to be separated at the board level.<br />
Note:<br />
Shaded sections are not supported for the <strong>PXA210</strong> applications processor.<br />
Table 8-6. <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> VCCN vs. VCCQ (Sheet 1 of 6)<br />
Pin<br />
Pin<br />
Count<br />
Alt_fn<br />
1-(in)<br />
Alt_fn<br />
2-(in)<br />
Alt_fn<br />
1-(out)<br />
Alt_fn<br />
2-(out)<br />
Signal Description <strong>and</strong><br />
Comments<br />
Power<br />
Supply<br />
MA(25:0) 26 Main Memory Address Bus VCCN<br />
MD(31:16) 16 Main Memory Data Bus (high) VCCN<br />
MD(15:0) 16 Main Memory Data Bus (low) VCCN<br />
nOE 1 Main Memory Bus Output Enable VCCN<br />
nWE 1 Main Memory Bus Write Enable VCCN<br />
nSDRAS 1 Main Memory Bus RAS VCCN<br />
nSDCAS 1 Main Memory Bus CAS VCCN<br />
DQM(3:2) 2<br />
Main Memory Bus SDRAM byte<br />
selects<br />
VCCN<br />
8-6 <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide
Power <strong>and</strong> Clocking<br />
Table 8-6. <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> VCCN vs. VCCQ (Sheet 2 of 6)<br />
Pin<br />
Pin<br />
Count<br />
Alt_fn<br />
1-(in)<br />
Alt_fn<br />
2-(in)<br />
Alt_fn<br />
1-(out)<br />
Alt_fn<br />
2-(out)<br />
Signal Description <strong>and</strong><br />
Comments<br />
Power<br />
Supply<br />
DQM(1:0) 2<br />
nSDCS(3:2) 2<br />
nSDCS(1:0) 2<br />
SDCKE(1:0) 2<br />
Main Memory Bus SDRAM byte<br />
selects<br />
Main Memory Bus SDRAM chip<br />
selects<br />
Main Memory Bus SDRAM chip<br />
selects<br />
Main Memory Bus SDRAM clock<br />
enable<br />
VCCN<br />
VCCN<br />
VCCN<br />
VCCN<br />
SDCLK(2) 1 Main Memory Bus SDRAM clocks VCCN<br />
SDCLK(1:0) 2 Main Memory Bus SDRAM clocks VCCN<br />
RD/nWR 1 CC Steering Signal VCCN<br />
CS(0) 1 Static chip selects VCCN<br />
GP15 1 nCS_1 Active low chip select 1 VCCN<br />
GP18 1 RDY Ext. Bus Ready VCCN<br />
GP19 1 DREQ[1] Ext. Bus Master Request VCCN<br />
GP20 1 DREQ[0] Ext. Bus Master Request VCCN<br />
GP21 1 General Purpose I/O pin VCCN<br />
GP22 1 General Purpose I/O pin VCCN<br />
GP33 1 nCS[5] Active low chip select 5 VCCN<br />
GP48 1 nPOE Output Enable for Card Space VCCN<br />
GP49 1 nPWE Write Enable for Card Space VCCN<br />
GP50 1 nPIOR I/O Read for Card Space VCCN<br />
GP51 1 nPIOW I/O Write for Card Space VCCN<br />
GP52 1 nPCE[1] Card Enable for Card Space VCCN<br />
GP53 1<br />
MMCCLK<br />
nPCE[2]<br />
Card Enable for Card Space<br />
MMC CLock<br />
VCCN<br />
GP54 1<br />
MMCCLK<br />
pSKTSEL<br />
MMC CLock<br />
Socket Select for Card Space<br />
VCCN<br />
GP55 1 nPREG Card Address bit 26 VCCN<br />
GP56 1 nPWAIT Wait signal for Card Space VCCN<br />
GP57 1 nIOIS16<br />
Bus Width select for I/O Card<br />
Space<br />
VCCN<br />
GP78 1 nCS[2] Active low chip select 2 VCCN<br />
GP79 1 nCS[3] Active low chip select 3 VCCN<br />
GP80 1 nCS[4] Active low chip select 4 VCCN<br />
<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide 8-7
Power <strong>and</strong> Clocking<br />
Table 8-6. <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> VCCN vs. VCCQ (Sheet 3 of 6)<br />
Pin<br />
Pin<br />
Count<br />
Alt_fn<br />
1-(in)<br />
Alt_fn<br />
2-(in)<br />
Alt_fn<br />
1-(out)<br />
Alt_fn<br />
2-(out)<br />
Signal Description <strong>and</strong><br />
Comments<br />
Power<br />
Supply<br />
MMCMD 1 MMC Comm<strong>and</strong> VCCQ<br />
MMDAT 1 MMC Data VCCQ<br />
AC_RESET_n 1 ac97 RESET VCCQ<br />
UDC+ 1 USB client high differential signal VCCQ<br />
UDC- 1 USB client low differential signal VCCQ<br />
SCL 1 I2C Clock VCCQ<br />
SDA 1 I2C Bidirectional Data VCCQ<br />
nRESET 1 Hardware reset VCCQ<br />
nRESET_OUT 1 Reset output VCCQ<br />
BOOT_SEL[2:0] 3 ROM Width Select (16/32) VCCQ<br />
PWR_EN 1 power enable VCCQ<br />
nBATT_FAULT 1 Battery Fault VCCQ<br />
nVDD_FAULT 1 VDD Fault VCCQ<br />
nTRST 1 JTAG Reset VCCQ<br />
TDI 1 JTAG Data In VCCQ<br />
TDO 1 JTAG Data Out VCCQ<br />
TMS 1 JTAG Mode Select VCCQ<br />
TCK 1 JTAG Clock VCCQ<br />
TESTCLK 1 TEST Clock VCCQ<br />
TEST 1 TEST mode VCCQ<br />
GP0 1 Reserved for sleep wakeup VCCQ<br />
GP1 1 GP_RST Active low GP_reset VCCQ<br />
GP2 1 General Purpose I/O pin VCCQ<br />
GP3 1 General Purpose I/O pin VCCQ<br />
GP4 1 General Purpose I/O pin VCCQ<br />
GP5 1 General Purpose I/O pin VCCQ<br />
GP6 1 MMCCLK MMC Clock VCCQ<br />
GP7 1 48 MHz 48 mhz clock output VCCQ<br />
GP8 1 MMCCS0 MMC Chip Select 0 VCCQ<br />
GP9 1 MMCCS1 MMC Chip Select 1 VCCQ<br />
GP10 1 RTCCLK real time clock (1Hz) VCCQ<br />
8-8 <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide
Power <strong>and</strong> Clocking<br />
Table 8-6. <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> VCCN vs. VCCQ (Sheet 4 of 6)<br />
Pin<br />
Pin<br />
Count<br />
Alt_fn<br />
1-(in)<br />
Alt_fn<br />
2-(in)<br />
Alt_fn<br />
1-(out)<br />
Alt_fn<br />
2-(out)<br />
Signal Description <strong>and</strong><br />
Comments<br />
Power<br />
Supply<br />
GP11 1 3.6 MHz 3.6 MHz oscillator out VCCQ<br />
GP12 1 32 KHz 32 KHz out VCCQ<br />
GP13 1 MBGNT memory controller grant VCCQ<br />
GP14 1 MBREQ Alternate Bus Master Request VCCQ<br />
GP16 1 PWM0 PWM0 output VCCQ<br />
GP17 1 PWM1 PWM1 output VCCQ<br />
GP23 1 SCLK SSP clock VCCQ<br />
GP24 1 SFRM SSP Frame VCCQ<br />
GP25 1 TXD SSP transmit VCCQ<br />
GP26 1 RXD SSP receive VCCQ<br />
GP27 1 EXTCLK SSP ext_clk VCCQ<br />
BITCLK<br />
AC97 bit_clk<br />
GP28 1<br />
BITCLK<br />
BITCLK<br />
I2S bit_clk<br />
I2S bit_clk<br />
VCCQ<br />
BITCLK<br />
AC97 bit_clk<br />
GP29 1<br />
SDATA_IN0<br />
SDATA_<br />
IN<br />
AC97 Sdata_in0<br />
I2S Sdata_in<br />
VCCQ<br />
GP30 1<br />
SDATA_<br />
OUT<br />
SDATA_<br />
OUT<br />
I2S Sdata_out<br />
AC97 Sdata_out<br />
VCCQ<br />
GP31 1<br />
SYNC<br />
SYNC<br />
I2S sync<br />
AC97 sync<br />
VCCQ<br />
GP32 1<br />
SDATA_IN1<br />
SYSCLK<br />
I2S sysclk<br />
AC97 Sdata_in1<br />
VCCQ<br />
GP34 1<br />
FFRXD<br />
FFUART receive<br />
MMCCS0 MMC Chip Select 0<br />
VCCQ<br />
GP35 1 CTS FFUART Clear to send VCCQ<br />
GP36 1 DCD FFUART Data carrier detect VCCQ<br />
GP37 1 DSR FFUART data set ready VCCQ<br />
GP38 1 RI FFUART Ring Indicator VCCQ<br />
GP39 1<br />
MMCCS1 MMC Chip Select 1<br />
FFTXD<br />
FFUART transmit data<br />
VCCQ<br />
<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide 8-9
Power <strong>and</strong> Clocking<br />
Table 8-6. <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> VCCN vs. VCCQ (Sheet 5 of 6)<br />
Pin<br />
Pin<br />
Count<br />
Alt_fn<br />
1-(in)<br />
Alt_fn<br />
2-(in)<br />
Alt_fn<br />
1-(out)<br />
Alt_fn<br />
2-(out)<br />
Signal Description <strong>and</strong><br />
Comments<br />
Power<br />
Supply<br />
GP40 1 DTR FFUART data terminal Ready VCCQ<br />
GP41 1 RTS FFUART request to send VCCQ<br />
GP42 1 BTRXD BTUART receive data VCCQ<br />
GP43 1 BTTXD BTUART transmit data VCCQ<br />
GP44 1 CTS BTUART clear to send VCCQ<br />
GP45 1 RTS BTUART request to send VCCQ<br />
GP46 1<br />
ICP_RXD<br />
RXD<br />
ICP receive data<br />
STD_UART receive data<br />
VCCQ<br />
GP47 1<br />
TXD<br />
ICP_TXD<br />
STD_UART transmit data<br />
ICP transmit data<br />
VCCQ<br />
GP58 1 LDD[0] LCD data pin 0 VCCQ<br />
GP59 1 LDD[1] LCD data pin 1 VCCQ<br />
GP60 1 LDD[2] LCD data pin 2 VCCQ<br />
GP61 1 LDD[3] LCD data pin 3 VCCQ<br />
GP62 1 LDD[4] LCD data pin 4 VCCQ<br />
GP63 1 LDD[5] LCD data pin 5 VCCQ<br />
GP64 1 LDD[6] LCD data pin 6 VCCQ<br />
GP65 1 LDD[7] LCD data pin 7 VCCQ<br />
GP66 1<br />
MBREQ<br />
LDD[8] LCD data pin 8<br />
Alternate Bus Master Request<br />
VCCQ<br />
GP67 1<br />
LDD[9] LCD data pin 9<br />
MMCCS0 MMC Chip Select 0<br />
VCCQ<br />
GP68 1<br />
MMCCS1 MMC Chip Select 1<br />
LDD[10] LCD data pin 10<br />
VCCQ<br />
GP69 1<br />
MMCCLK<br />
MMC_CLK<br />
LDD[11] LCD data pin 11<br />
VCCQ<br />
GP70 1<br />
RTCCLK<br />
Real Time clock (1Hz)<br />
LDD[12] LCD data pin 12<br />
VCCQ<br />
GP71 1<br />
GP72 1<br />
3.6 MHz 3.6MHz Oscillator clock<br />
LDD[13] LCD data pin 13<br />
32 KHz 32 KHz clock<br />
LDD[14] LCD data pin 14<br />
VCCQ<br />
VCCQ<br />
8-10 <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide
Power <strong>and</strong> Clocking<br />
Table 8-6. <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> VCCN vs. VCCQ (Sheet 6 of 6)<br />
Pin<br />
Pin<br />
Count<br />
Alt_fn<br />
1-(in)<br />
Alt_fn<br />
2-(in)<br />
Alt_fn<br />
1-(out)<br />
Alt_fn<br />
2-(out)<br />
Signal Description <strong>and</strong><br />
Comments<br />
Power<br />
Supply<br />
GP73 1<br />
MBGNT<br />
LDD[15] LCD data pin 15<br />
memory controller grant<br />
VCCQ<br />
GP74 1<br />
LCD_FCL<br />
K<br />
LCD Frame clock<br />
VCCQ<br />
GP75 1<br />
LCD_LCL<br />
K<br />
LCD line clock<br />
VCCQ<br />
GP76 1<br />
LCD_PCL<br />
K<br />
LCD Pixel clock<br />
VCCQ<br />
GP77 1<br />
LCD_AC<br />
BIAS<br />
LCD AC Bias<br />
VCCQ<br />
PXTAL 1 3.6Mhz Crystal input 0.8 * VCC<br />
PEXTAL 1 3.6Mhz Crystal output 0.8 * VCC<br />
TXTAL 1 32khz Crystal input 0.8 * VCC<br />
TEXTAL 1 32khz Crystal output 0.8 * VCC<br />
8.5.2 Power On Timing<br />
The External Voltage Regulator <strong>and</strong> other power-on devices must provide the applications<br />
processor with a specific sequence of power <strong>and</strong> resets to ensure proper operation. This sequence is<br />
shown in Figure 8-1, “Power-On Reset Timing” on page 8-12 <strong>and</strong> detailed in Table 8-7, “Power-<br />
On Timing Specifications” on page 8-12.<br />
It is important that the applications processor power supplies be powered-up in a certain order to<br />
avoid high current situations. The required order is:<br />
1. VCCQ<br />
2. VCCN<br />
3. VCC <strong>and</strong> PLL_VCC<br />
VCCN may be powered at the same time as VCCQ, however do not apply power to VCCN before<br />
powering VCCQ.<br />
<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide 8-11
Power <strong>and</strong> Clocking<br />
Note:<br />
If Hardware Reset is entered during Sleep Mode, the proper power-supply stabilization times <strong>and</strong><br />
nRESET timing requirements indicated in Table 8-7, “Power-On Timing Specifications” on<br />
page 8-12 must be observed.<br />
Figure 8-1. Power-On Reset Timing<br />
t R_VCCQ<br />
VCCQ, PWR_EN<br />
t R_VCCN<br />
VCCN<br />
VCC<br />
nTRST<br />
t D_VCCN<br />
t D_VCC<br />
t R_VCC<br />
t D_NTRST<br />
t D_JTAG<br />
JTAG PINS<br />
nRESET<br />
t D_NRESET<br />
nRESET_OUT<br />
t D_OUT<br />
Note: nBATT_FAULT <strong>and</strong> nVDD_FAULT must be high before nRESET_OUT is<br />
deasserted or <strong>PXA250</strong> enters Sleep Mode<br />
Table 8-7. Power-On Timing Specifications<br />
Symbol Description Min Typical Max<br />
t R_VCCQ VCCQ Rise / Stabilization time 0.01 ms — 100 ms<br />
t R_VCCN VCCN Rise / Stabilization time 0.01 ms — 100 ms<br />
t R_VCC VCC, PLL_VCC Rise / Stabilization time 0.01 ms — 10 ms<br />
t D_VCCN Delay between VCCQ stable <strong>and</strong> VCCN applied 0ms — —<br />
t D_VCC Delay from VCCN stable <strong>and</strong> VCC, PLL_VCC applied 0ms — —<br />
t D_NTRST Delay between VCC, PLL_VCC stable <strong>and</strong> nTRST deasserted 50 ms — —<br />
t D_JTAG<br />
t D_NRESET<br />
t D_OUT<br />
Delay between nTRST deasserted <strong>and</strong> JTAG pins active, with<br />
nRESET asserted<br />
Delay between VCC, PLL_VCC stable <strong>and</strong> nRESET<br />
deasserted<br />
Delay between nRESET deasserted <strong>and</strong> nRESET_OUT<br />
deasserted<br />
0.03 ms — —<br />
50 ms — —<br />
18.1 ms — 18.2 ms<br />
8.5.3 Hardware Reset Timing<br />
The timing sequences shown in Figure 8-2 “Hardware Reset Timing” assumes the power supplies<br />
are stable at the assertion of nRESET. If the power supplies are unstable, follow the timings<br />
indicated in Section 8.5.2, “Power On Timing” on page 11.<br />
8-12 <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide
Power <strong>and</strong> Clocking<br />
Figure 8-2. Hardware Reset Timing<br />
nRESET<br />
nRESET_OUT<br />
t DHW_NRESET<br />
t DHW_OUT<br />
t DHW_OUT_A<br />
Note: nBATT_FAULT <strong>and</strong> nVDD_FAULT must be high before nRESET is deasserted<br />
or <strong>PXA250</strong> enters Sleep Mode<br />
Table 8-8. Hardware Reset Timing Specifications<br />
Symbol Description Min Typical Max<br />
t DHW_NRESET Minimum assertion time of nRESET 0.001 ms — —<br />
t DHW_OUT_A Delay between nRESET Asserted <strong>and</strong> nRESET_OUT Asserted 0ms — 0.001 ms<br />
t DHW_OUT<br />
Delay between nRESET deasserted <strong>and</strong> nRESET_OUT<br />
deasserted<br />
18.1 ms — 18.2 ms<br />
8.5.4 Watchdog Reset Timing<br />
Watchdog Reset is an internally generated reset <strong>and</strong> therefore has no external pin dependencies.<br />
The nRESET_OUT pin is the only indicator of Watchdog Reset, <strong>and</strong> it stays asserted for<br />
t DHW_OUT . Refer to Figure 8-2, “Hardware Reset Timing” on page 8-13 for more information.<br />
8.5.5 GPIO Reset Timing<br />
GPIO Reset is generated externally. The pin used as the GPIO Reset is reconfigured as a st<strong>and</strong>ard<br />
GPIO after the reset propagates internally. Because the clock module is not reset by GPIO Reset,<br />
timing varies based on the frequency of the selected clock. Timing also varies in the Frequency<br />
Change Sequence (see Section 8.4.1, “32.768 kHz Oscillator Specifications” on page 4). Figure<br />
8-3 “GPIO Reset Timing” shows the possible GPIO Reset timing.<br />
Figure 8-3. GPIO Reset Timing<br />
t A_GP[1]<br />
GP[1]<br />
nRESET_OUT<br />
t DGP_OUT<br />
t DGP_OUT_A<br />
Note: nBATT_FAULT <strong>and</strong> nVDD_FAULT must be high before nRESET is deasserted<br />
or <strong>PXA250</strong> enters Sleep Mode<br />
<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide 8-13
Power <strong>and</strong> Clocking<br />
Table 8-9. GPIO Reset Timing Specifications<br />
Symbol Description Min Typical Max<br />
t A_GP[1] Minimum assert time of GP[1] 1 in 3.6864 MHz input clock cycles 4 cycles — —<br />
t DGP_OUT_A<br />
Delay between GP[1] Asserted <strong>and</strong> nRESET_OUT Asserted in<br />
3.6864 MHz input clock cycles<br />
6 cycles — 8 cycles<br />
t DGP_OUT<br />
Delay between nRESET_OUT asserted <strong>and</strong> nRESET_OUT<br />
deasserted, Run or Turbo Mode 2 5 µs — 28 µs<br />
Delay between nRESET_OUT asserted <strong>and</strong> nRESET_OUT<br />
t DGP_OUT_F deasserted, during Frequency Change Sequence 3 5 µs — 380 µs<br />
NOTES:<br />
1. GP[1] is not recognized as a reset source again until configured to do so in software. Software should check the state of<br />
GP[1] before configuring it as a Reset to ensure no spurious reset is generated.<br />
2. Time is 512*N Processor Clock Cycles plus as many as 4 cycles of the 3.6864 MHz input clock.<br />
3. Time during the Frequency Change Sequence depends on the state of the PLL Lock Detector at the assertion of GPIO<br />
Reset. The Lock Detector has a maximum time of 350 us plus synchronization.<br />
8.5.6 Sleep Mode Timing<br />
Sleep Mode is internally asserted, <strong>and</strong> asserts the nRESET_OUT <strong>and</strong> PWR_EN signals. The<br />
sequence indicated in Figure 8-4 “Sleep Mode Timing” <strong>and</strong> detailed in Table 8-10, “Sleep Mode<br />
Timing Specifications” on page 8-14 are the required timing parameters for Sleep Mode.<br />
Figure 8-4. Sleep Mode Timing<br />
t A_GP[x]<br />
GP[x]<br />
PWR_EN<br />
VCC<br />
nVDD_FAULT<br />
tD_PWR_F<br />
t D_PWR_R<br />
t D_FAULT<br />
t DSM_VCC<br />
nRESET_OUT<br />
t DSM_OUT<br />
Note: nBATT_FAULT must be high or <strong>PXA250</strong> will not exit Sleep Mode<br />
Table 8-10. Sleep Mode Timing Specifications (Sheet 1 of 2)<br />
Symbol Description Min Typical Max<br />
t A_GP[x} Assert Time of GPIO Wake up Source (x=[15:0]) 91.6 µs — —<br />
t D_PWR_F Delay from nRESET_OUT asserted to PWR_EN deasserted 61 µs — 91.6 µs<br />
t D_PWR_R Delay between GP[x] asserted to PWR_EN asserted 30.5 µs — 122.1 µs<br />
t DSM_VCC Delay between PWR_EN asserted <strong>and</strong> VCC stable — — 10 ms<br />
8-14 <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide
Power <strong>and</strong> Clocking<br />
Table 8-10. Sleep Mode Timing Specifications (Sheet 2 of 2)<br />
Symbol Description Min Typical Max<br />
t D_FAULT<br />
t DSM_OUT<br />
t DSM_OUT_O<br />
Delay between PWR_EN asserted <strong>and</strong> nVDD_FAULT<br />
deasserted<br />
Delay between PWR_EN asserted <strong>and</strong> nRESET_OUT<br />
deasserted, OPDE Set<br />
Delay between PWR_EN asserted <strong>and</strong> nRESET_OUT<br />
deasserted, OPDE Clear<br />
— — 10 ms<br />
28.0 ms — 80 ms<br />
10.35 ms — 10.5 ms<br />
8.6 Memory Bus <strong>and</strong> PCMCIA AC Specifications<br />
This section gives the timing information for the following types of memory:<br />
• SRAM / ROM / Flash / Synchronous Fast Flash Asynchronous writes (Table 8-11)<br />
• Variable Latency I/O (Table 8-12)<br />
• Card Interface (PCMCIA or Compact Flash) (Table 8-13)<br />
• Synchronous Memories (Table 8-14)<br />
Table 8-11. SRAM / ROM / Flash / Synchronous Fast Flash AC Specifications (3.3 V)<br />
Symbol<br />
Description<br />
MEMCLK Frequency (MHz)<br />
99.5 118.0 132.7 147.5 165.9<br />
Notes<br />
SRAM / ROM / Flash / Synchronous Fast Flash (WRITES) (Asynchronous)<br />
tromAS<br />
tromAH<br />
MA(25:0) setup to nCS, nOE, nSDCAS (as nADV)<br />
asserted<br />
MA(25:0) hold after nCS, nOE, nSDCAS (as nADV)<br />
deasserted<br />
10 ns 8.5 ns 7.5 ns 6.8 ns 6 ns 1<br />
10 ns 8.5 ns 7.5 ns 6.8 ns 6 ns 1<br />
tromASW MA(25:0) setup to nWE asserted 30 ns 25.5 ns 22.5 ns 20.4 ns 18 ns 2<br />
tromAHW MA(25:0) hold after nWE deasserted 10 ns 8.5 ns 7.5 ns 6.8 ns 6 ns 1<br />
tromCES nCS setup to nWE asserted 20 ns 17 ns 15 ns 13.6 ns 12 ns 3<br />
tromCEH nCS hold after nWE deasserted 10 ns 8.5 ns 7.5 ns 6.8 ns 6 ns 1<br />
tromDS MD(31:0), DQM(3:0) write data setup to nWE asserted 10 ns 8.5 ns 7.5 ns 6.8 ns 6 ns 1<br />
tromDSWH<br />
tromDH<br />
MD(31:0), DQM(3:0) write data setup to nWE<br />
deasserted<br />
MD(31:0), DQM(3:0) write data hold after nWE<br />
deasserted<br />
20 ns 17 ns 15 ns 13.6 ns 12 ns 3<br />
10 ns 8.5 ns 7.5 ns 6.8 ns 6 ns 1<br />
tromNWE nWE high time between beats of write data 20 ns 17 ns 15 ns 13.6 ns 12 ns 3<br />
NOTES:<br />
1. This number represents 1 MEMCLK period<br />
2. This number represents 3 MEMCLK periods<br />
3. This number represents 2 MEMCLK periods<br />
<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide 8-15
Power <strong>and</strong> Clocking<br />
Table 8-12. Variable Latency I/O Interface AC Specifications (3.3 V)<br />
Symbol<br />
Description<br />
MEMCLK Frequency (MHz)<br />
99.5 118.0 132.7 147.5 165.9<br />
Notes<br />
Variable Latency IO Interface (VLIO) (Asynchronous)<br />
tvlioAS MA(25:0) setup to nCS asserted 10 ns 8.5 ns 7.5 ns 6.8 ns 6 ns 1<br />
tvlioASRW MA(25:0) setup to nOE or nPWE asserted 10 ns 8.5 ns 7.5 ns 6.8 ns 6 ns 1<br />
tvlioAH MA(25:0) hold after nOE or nPWE deasserted 10 ns 8.5 ns 7.5 ns 6.8 ns 6 ns 1<br />
tvlioCES nCS setup to nOE or nPWE asserted 20 ns 17 ns 15 ns 13.6 ns 12 ns 2<br />
tvlioCEH nCS hold after nOE or nPWE deasserted 10 ns 8.5 ns 7.5 ns 6.8 ns 6 ns 1<br />
tvlioDSW MD(31:0), DQM(3:0) write data setup to nPWE asserted 10 ns 8.5 ns 7.5 ns 6.8 ns 6 ns 1<br />
tvlioDSWH<br />
MD(31:0), DQM(3:0) write data setup to nPWE<br />
deasserted<br />
20 ns 17 ns 15 ns 13.6 ns 12 ns 2<br />
tvlioDHW MD(31:0), DQM(3:0) hold after nPWE deasserted 10 ns 8.5 ns 7.5 ns 6.8 ns 6 ns 1<br />
tvlioDHR MD(31:0) read data hold after nOE deasserted 0 ns 0 ns 0 ns 0 ns 0 ns —<br />
tvlioRDYH RDY hold after nOE, nPWE deasserted 0 ns 0 ns 0 ns 0 ns 0 ns —<br />
nPWE, nOE high time between beats of write or read<br />
tvlioNPWE<br />
data<br />
NOTES:<br />
1. This number represents 1 MEMCLK period<br />
2. This number represents 2 MEMCLK periods<br />
20 ns 17 ns 15 ns 13.6 ns 12 ns 2<br />
Table 8-13. Card Interface (PCMCIA or Compact Flash) AC Specifications (3.3 V)<br />
Symbol<br />
Description<br />
MEMCLK Frequency (MHz)<br />
99.5 118.0 132.7 147.5 165.9<br />
Notes<br />
tcardAS<br />
tcardAH<br />
tcardDS<br />
Card Interface (PCMCIA or Compact Flash) (Asynchronous)<br />
MA(25:0), nPREG, PSKTSEL, nPCE setup to nPWE,<br />
nPOE, nPIOW, or nPIOR asserted<br />
MA(25:0), nPREG, PSKTSEL, nPCE hold after nPWE,<br />
nPOE, nPIOW, or nPIOR deasserted<br />
MD(31:0) setup to nPWE, nPOE, nPIOW, or nPIOR<br />
asserted<br />
20 ns 17 ns 15 ns 13.6 ns 12 ns 1<br />
10 ns 8.5 ns 7.5 ns 6.8 ns 6 ns 1<br />
10 ns 8.5 ns 7.5 ns 6.8 ns 6 ns 1<br />
tcardDH<br />
MD(31:0) hold after nPWE, nPOE, nPIOW, or nPIOR<br />
deasserted<br />
10 ns 8.5 ns 7.5 ns 6.8 ns 6 ns 1<br />
tcardCMD nPWE, nPOE, nPIOW, or nPIOR comm<strong>and</strong> assertion 30 ns 25.5 ns 22.5 ns 20.4 ns 18 ns 1<br />
NOTE:<br />
1. These numbers are minimums. They can be much longer based on the programmable Card Interface timing registers.<br />
8-16 <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide
Power <strong>and</strong> Clocking<br />
Table 8-14. Synchronous Memory Interface AC Specifications (3.3 V)<br />
Symbol Description MIN MAX Notes 1<br />
SDRAM / SMROM<br />
tsynCLK SDCLK period 10 ns 20 ns 2<br />
tsynCMD nSDCAS, nSDRAS, nWE, nSDCS assert time 1 sdclk — —<br />
tsynRCD nSDRAS to nSDCAS assert time 1 sdclk — —<br />
tsynCAS nSDCAS to nSDCAS assert time 2 sdclk — —<br />
tsynSDOS<br />
MA(25:0), MD(31:0), DQM(3:0), nSDCS(3:0), nSDRAS, nSDCAS, nWE, nOE,<br />
SDCKE(1:0), RDnWR output setup time to SDCLK(2:0) rise<br />
5ns — 3<br />
tsynSDOH<br />
MA(25:0), MD(31:0), DQM(3:0), nSDCS(3:0), nSDRAS, nSDCAS, nWE, nOE,<br />
SDCKE(1:0), RDnWR output hold time from SDCLK(2:0) rise<br />
5ns — 3<br />
tsynSDIS MD(31:0) read data input setup time from SDCLK(2:0) rise 0.5 ns —<br />
tsynDIH MD(31:0) read data input hold time from SDCLK(2:0) rise 1.5 ns — —<br />
Fast Flash (Synchronous READS only)<br />
tffCLK SDCLK period 15 ns 20 ns 4<br />
tffAS MA(25:0) setup to nSDCAS (as nADV) asserted 0.5 sdclk — —<br />
tffCES nCS setup to nSDCAS (as nADV) asserted 0.5 sdclk — —<br />
tffADV nSDCAS (as nADV) pulse width 1 sdclk — —<br />
tffOS nSDCAS (as nADV) deassertion to nOE assertion 3 sdclk — —<br />
tffCEH nOE deassertion to nCS deassertion 4 sdclk — —<br />
NOTES:<br />
1. These numbers are for a maximum 99.5 MHz MEMCLK <strong>and</strong> 99.5 MHz output SDCLK.<br />
2. SDCLK for SDRAM <strong>and</strong> SMROM can be at the slowest, divide-by-2 of the 99.5 MHz MEMCLK. It can be 99.5 MHz at the<br />
fastest.<br />
3. This number represents 1/2 SDCLK period.<br />
4. SDCLK for Fast Flash can be at the slowest, divide-by-2 of the 99.5 MHz MEMCLK. It can be divide-by-2 of the 132.7 MHz<br />
MEMCLK at its fastest.<br />
<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide 8-17
Power <strong>and</strong> Clocking<br />
Table 8-15. SRAM / ROM / Flash / Synchronous Fast Flash AC Specifications (2.5 V)<br />
Symbol<br />
Description<br />
MEMCLK Frequency (MHz)<br />
99.5 118.0 132.7 147.5 165.9<br />
Notes<br />
SRAM / ROM / Flash / Synchronous Fast Flash (WRITES) (Asynchronous)<br />
tromAS<br />
tromAH<br />
tromASW<br />
tromAHW<br />
tromCES<br />
tromCEH<br />
tromDS<br />
tromDSWH<br />
tromDH<br />
tromNWE<br />
MA(25:0) setup to nCS, nOE, nSDCAS (as nADV)<br />
asserted<br />
MA(25:0) hold after nCS, nOE, nSDCAS (as nADV)<br />
deasserted<br />
MA(25:0) setup to nWE asserted<br />
MA(25:0) hold after nWE deasserted<br />
nCS setup to nWE asserted<br />
nCS hold after nWE deasserted<br />
MD(31:0), DQM(3:0) write data setup to nWE asserted<br />
MD(31:0), DQM(3:0) write data setup to nWE<br />
deasserted<br />
MD(31:0), DQM(3:0) write data hold after nWE<br />
deasserted<br />
nWE high time between beats of write data<br />
NOTES:<br />
1. This number represents 1 MEMCLK period<br />
2. This number represents 3 MEMCLK periods<br />
3. This number represents 2 MEMCLK periods<br />
TBD<br />
8-18 <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide
Power <strong>and</strong> Clocking<br />
Table 8-16. Variable Latency I/O Interface AC Specifications (2.5 V)<br />
Symbol<br />
Description<br />
MEMCLK Frequency (MHz)<br />
99.5 118.0 132.7 147.5 165.9<br />
Notes<br />
Variable Latency IO Interface (VLIO) (Asynchronous)<br />
tvlioAS<br />
tvlioASRW<br />
tvlioAH<br />
tvlioCES<br />
tvlioCEH<br />
tvlioDSW<br />
tvlioDSWH<br />
tvlioDHW<br />
tvlioDHR<br />
tvlioRDYH<br />
MA(25:0) setup to nCS asserted<br />
MA(25:0) setup to nOE or nPWE asserted<br />
MA(25:0) hold after nOE or nPWE deasserted<br />
nCS setup to nOE or nPWE asserted<br />
nCS hold after nOE or nPWE deasserted<br />
MD(31:0), DQM(3:0) write data setup to nPWE asserted<br />
MD(31:0), DQM(3:0) write data setup to nPWE<br />
deasserted<br />
MD(31:0), DQM(3:0) hold after nPWE deasserted<br />
MD(31:0) read data hold after nOE deasserted<br />
RDY hold after nOE, nPWE deasserted<br />
nPWE, nOE high time between beats of write or read<br />
tvlioNPWE<br />
data<br />
NOTES:<br />
1. This number represents 1 MEMCLK period<br />
2. This number represents 2 MEMCLK periods<br />
TBD<br />
Table 8-17. Card Interface (PCMCIA or Compact Flash) AC Specifications (2.5 V)<br />
Symbol<br />
Description<br />
MEMCLK Frequency (MHz)<br />
99.5 118.0 132.7 147.5 165.9<br />
Notes<br />
tcardAS<br />
tcardAH<br />
tcardDS<br />
tcardDH<br />
tcardCMD<br />
Card Interface (PCMCIA or Compact Flash) (Asynchronous)<br />
MA(25:0), nPREG, PSKTSEL, nPCE setup to nPWE,<br />
nPOE, nPIOW, or nPIOR asserted<br />
MA(25:0), nPREG, PSKTSEL, nPCE hold after nPWE,<br />
nPOE, nPIOW, or nPIOR deasserted<br />
MD(31:0) setup to nPWE, nPOE, nPIOW, or nPIOR<br />
asserted<br />
MD(31:0) hold after nPWE, nPOE, nPIOW, or nPIOR<br />
deasserted<br />
nPWE, nPOE, nPIOW, or nPIOR comm<strong>and</strong> assertion<br />
NOTE:<br />
1. These numbers are minimums. They can be much longer based on the programmable Card Interface timing registers.<br />
TBD<br />
<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide 8-19
Power <strong>and</strong> Clocking<br />
Table 8-18. Synchronous Memory Interface AC Specifications (2.5 V)<br />
Symbol Description MIN MAX Notes 1<br />
SDRAM / SMROM<br />
tsynCLK<br />
tsynCMD<br />
tsynRCD<br />
tsynCAS<br />
tsynSDOS<br />
tsynSDOH<br />
tsynSDIS<br />
tsynDIH<br />
tffCLK<br />
tffAS<br />
tffCES<br />
tffADV<br />
tffOS<br />
tffCEH<br />
SDCLK period<br />
nSDCAS, nSDRAS, nWE, nSDCS assert time<br />
nSDRAS to nSDCAS assert time<br />
nSDCAS to nSDCAS assert time<br />
MA(25:0), MD(31:0), DQM(3:0), nSDCS(3:0), nSDRAS, nSDCAS, nWE, nOE,<br />
SDCKE(1:0), RDnWR output setup time to SDCLK(2:0) rise<br />
MA(25:0), MD(31:0), DQM(3:0), nSDCS(3:0), nSDRAS, nSDCAS, nWE, nOE,<br />
SDCKE(1:0), RDnWR output hold time from SDCLK(2:0) rise<br />
MD(31:0) read data input setup time from SDCLK(2:0) rise<br />
MD(31:0) read data input hold time from SDCLK(2:0) rise<br />
Fast Flash (Synchronous READS only)<br />
SDCLK period<br />
MA(25:0) setup to nSDCAS (as nADV) asserted<br />
nCS setup to nSDCAS (as nADV) asserted<br />
nSDCAS (as nADV) pulse width<br />
nSDCAS (as nADV) deassertion to nOE assertion<br />
nOE deassertion to nCS deassertion<br />
TBD<br />
TBD<br />
NOTES:<br />
1. These numbers are for a maximum 99.5 MHz MEMCLK <strong>and</strong> 99.5 MHz output SDCLK.<br />
2. SDCLK for SDRAM <strong>and</strong> SMROM can be at the slowest, divide-by-2 of the 99.5 MHz MEMCLK. It can be 99.5 MHz at the<br />
fastest.<br />
3. This number represents 1/2 SDCLK period.<br />
4. SDCLK for Fast Flash can be at the slowest, divide-by-2 of the 99.5 MHz MEMCLK. It can be divide-by-2 of the 132.7 MHz<br />
MEMCLK at its fastest.<br />
8.7 Example Form Factor Reference Design Power<br />
Delivery Example<br />
8.7.1 Power System<br />
Features of the example form factor reference design power system (example in Figure 8-5,<br />
“Example Form Factor Reference Design Power System Design” on page 8-22) are:<br />
• A st<strong>and</strong>ard-size cylindrical single-cell Li+ 3.6 V battery with a 1.8 Ahr capacity<br />
• Battery temperature monitoring thermistor during charge cycles<br />
• Battery voltage monitoring<br />
• Charger supply voltage fault monitoring<br />
• Low battery interrupt signal to the microprocessor.<br />
8-20 <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide
Power <strong>and</strong> Clocking<br />
• Provide power gating switches for the CF, LCD, backlight, RS-232, MMC, Radio, <strong>and</strong> audio<br />
amplifier subsystems<br />
• Provide a high-efficiency 5.5 V supply rail for LCD <strong>and</strong> other devices<br />
• Provide a high-efficiency 3.3 V supply rail for I/O <strong>and</strong> general system power<br />
• Provide a high-efficiency 0.8 – 1.3 V Core/PLL supply for the microprocessor<br />
• Provide separate, clean power rails for the LCD <strong>and</strong> Audio subsystems<br />
• A small, low-cost, low-heat dissipation pulse-charge method for the battery<br />
8.7.1.1 Power System Configuration<br />
The example form factor reference design power system design is described in Figure 8-5,<br />
“Example Form Factor Reference Design Power System Design” on page 8-22. Note that there are<br />
four main power rails in the system:<br />
• 3.3 V I/O power<br />
• 0.8-1.3 V Core power<br />
• 1.3 V PLL power<br />
• 5.5 V power<br />
<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide 8-21
Power <strong>and</strong> Clocking<br />
Figure 8-5. Example Form Factor Reference Design Power System Design<br />
LDO<br />
ON/OFF<br />
Audio AMP<br />
LDO<br />
ON/OFF<br />
Audio_DC3P3V<br />
MMC_VDD<br />
LDO<br />
ON/OFF<br />
3.3V<br />
LDO<br />
ON/OFF<br />
LCD_DC3P3V<br />
LDO<br />
ON/OFF<br />
3.2V<br />
LDO<br />
ON/OFF<br />
LCD_DC5V<br />
LDO<br />
ON/OFF<br />
LCD_DC4V<br />
CF_VDD<br />
LDO<br />
ON/OFF<br />
3.3V<br />
Boost<br />
Converter<br />
MAX633<br />
LCD_DC15V<br />
LCD_DC14V-<br />
Boost<br />
Converter<br />
LTC1308A<br />
DC_5P5V<br />
LCD_DC11P7V-<br />
LDO<br />
3.2 V<br />
LDO<br />
3.3 V<br />
DC_3P3V<br />
DC_CORE<br />
Buck<br />
Converter<br />
LTC1878<br />
0.8 - 1.3 V<br />
Wall<br />
Input<br />
Current<br />
Limited<br />
Battery<br />
Charger<br />
LTC1730<br />
battery<br />
LDO<br />
1.3 V<br />
DC_PLL<br />
8.7.2 CORE Power<br />
The example form factor reference design has a variable 0.8 V – 1.3 V core power supply for the<br />
applications processor. This voltage varies depending on the performance required by the<br />
application. A Linear Technologies LTC1878 buck converter is chosen for this application. The<br />
power is drawn directly from the Li+ battery. This device operates at 550 kHz <strong>and</strong> can supply up to<br />
1 A at 0.8 V <strong>and</strong> 800 mA at 1.3 V with up to 95% efficiency. The device is turned on/off by the<br />
SA_PWR_EN signal directly from the applications processor.<br />
The required output voltage is statically adjusted by selecting the value of the feed-back resistor.<br />
Ultimately, output voltage can be changed using software control of the Linear Technologies<br />
LTC1663 DAC. This DAC is controllable via the st<strong>and</strong>ard I2C bus, <strong>and</strong> can modify the voltage of<br />
the feedback path of the buck converter, which effects a change in the output voltage.<br />
8.7.3 PLL Power<br />
DC_PLL supplies power to the three PLLs within the applications processor. This pin requires a<br />
0.85 V to 1.3 V nominal supply at an expected 20 mA load.<br />
8-22 <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide
Power <strong>and</strong> Clocking<br />
8.7.4 I/O 3.3 V Power<br />
A simple LDO linear regulator supplies the 3.3V rail. The Analog Devices ADP3335 is chosen for<br />
its very low drop-out – 200 mV at 500 mA <strong>and</strong> 110 mV at 200 mA. So typically, the input cut-off<br />
voltage for this device is about 3.3 V + 0.11 V = 3.41 V. The power is drawn directly from the Li+<br />
battery. For a 3.6 V battery, this device has a 82% efficiency. There are four zones of operation for<br />
the Li+ battery:<br />
• 4.1 – 3.8 V zone 10% of the time;<br />
• 3.7 – 3.6 V zone at 70% of the time;<br />
• 3.5 – 3.4 V at 10% of the time; <strong>and</strong><br />
• 3.4 – 3.1 V at 10% of the time.<br />
The ADP3335 operates in zone 1,2, 3, <strong>and</strong> cutoffs in zone 4.<br />
The overall efficiency is:<br />
0.1(3.3/4.0) + 0.7(3.3/3.6) + 0.1(3.3/3.4) = 0.0825 + 0.642 + 0.097 = 0.82<br />
To access the energy in zone 4 use the second LDO linear regulator in a parallel configuration with<br />
the ADP3335 <strong>and</strong> set it to output 3.2 V. Input to this regulator is 5.5 V from the boost converter.<br />
When the battery voltage drops below 3.5 V, the ADP3335 drops-out <strong>and</strong> the second regulator<br />
takes over.<br />
8.7.5 Peripheral 5.5 V Power<br />
The example form factor reference design provides a 5.5 V rail to supply power to LCD, Audio<br />
amplifier <strong>and</strong> Radio modules. An LT1308A boost converter is used. This device supplies up to 1 A<br />
at 5.5 V while operating at 600 kHz with up to 90% efficiency at rated load <strong>and</strong> 3.6 V input.<br />
In addition, a low battery voltage detect circuit has an open-drain output. The detect voltage is set<br />
at 3.45 V by a resistor divider circuit. When the battery drops below 3.45 V the output transitions<br />
to a logic low. This output signal is used as a processor interrupt.<br />
<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide 8-23
Power <strong>and</strong> Clocking<br />
8-24 <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide
JTAG/Debug Port 9<br />
9.1 Description<br />
The JTAG/Debug port is essentially several shift registers, with the destination controlled by the<br />
TMS pin <strong>and</strong> data I/O with TDI/TDO. nTRST provides initialization of the test logic. JTAG is<br />
testable via the IEEE 1149.1. Many use JTAG to control the address/data bus for Flash<br />
programming. JTAG is also a hardware debug port.<br />
9.2 Schematics<br />
All JTAG pins, except for nTRST <strong>and</strong> TCK, are directly connected. TCK is not driven internally<br />
<strong>and</strong> so you must add an external pull-up or pull-down resistor. <strong>Intel</strong> recommends adding a 1.5 k<br />
pull-down resistor to TCK. nTRST must be asserted during power-on. Asserting nRESET or<br />
nTRST must not cause the other reset signal to assert. Also, use an external pull-up resistor on<br />
nTRST to prevent spurious resets of the JTAG port when disconnected. The circuit in Figure 9-1<br />
drives nTRST. It uses a reset IC on nTRST to ensure that nTRST is reset at power-on. nRESET<br />
must be directly connected to the CPU nRESET. Do not connect pins 17 <strong>and</strong> 19 – they are special<br />
purpose functions <strong>and</strong> not used.<br />
Figure 9-1. JTAG/Debug Port Wiring Diagram<br />
3.3 V<br />
nTRST<br />
RESET MR<br />
MAX823<br />
TDI<br />
TMS<br />
1<br />
3<br />
5<br />
7<br />
2<br />
4<br />
6<br />
8<br />
nRESET<br />
TCK<br />
1.5K<br />
GND<br />
TDO<br />
9<br />
11<br />
13<br />
15<br />
10<br />
12<br />
14<br />
16<br />
17<br />
19<br />
18<br />
20<br />
If you are not utilizing either JTAG or the hardware debug functions, it is highly recommended that<br />
you design in a JTAG/debug port on your system anyway. This greatly facilitates board debug,<br />
startup, <strong>and</strong> software development. During final production you would not have to populate the<br />
JTAG connector.<br />
<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide 9-1
JTAG/Debug Port<br />
9.3 Layout<br />
Use the JTAG/Debug the port layout recommendations given in ARM’s application note, Multi-<br />
ICE System Design Considerations, Application Note 72. The recommended connector is a 2x10-<br />
way, 2.54 mm pitch pin header, shown in Figure 9-1.<br />
If board space is critical, use a small form-factor receptacle with a smaller pitch. Then use a cable<br />
interface that has a wire “dongle” with a 2.54 mm pitch pin header on one end <strong>and</strong> the smaller pitch<br />
connector on the other.<br />
Place the JTAG/Debug connector as close as possible to the applications processor to minimize<br />
signal degradation.<br />
If you follow these design recommendations, a JTAG bridge board is not required. Essentially, the<br />
JTAG bridge board for the example form factor reference design uses a 220 ohm resistor to tie<br />
nTRST high so that the JTAG logic can be brought out of reset (otherwise it would not come out of<br />
reset since nTRST is open-drain).<br />
9-2 <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide
SA-1110/<strong>Applications</strong> Processor<br />
Migration<br />
A<br />
The <strong>Intel</strong>® <strong>PXA250</strong> an <strong>PXA210</strong> applications processors represent the next generation follow-on to<br />
<strong>Intel</strong>® StrongARM* SA-1110 product. This appendix highlights the migration path needed to<br />
change an SA-1110 design to one that uses the applications processor.<br />
The majority of application code running on the SA-1110 will directly run on the applications<br />
processor, but there are substantial differences in hardware implementation <strong>and</strong> low-level coding,<br />
especially device configuration, that need to be noted.<br />
The applications processor has numerous new hardware <strong>and</strong> software features that substantially<br />
benefit a h<strong>and</strong>held product design. The applications processor can be considered a superset of the<br />
SA-1110, but with so many new features direct socket compatibility is impractical.<br />
For a detailed analysis of the differences between these products, refer to the full specifications of<br />
each device:<br />
• SA-1110 Advanced Developers Manual, Order# 278240 [http://developer.intel.com]<br />
• <strong>Intel</strong>® <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Developer’s Manual, Order# 278522<br />
• ARM* Architecture Reference Manual, Order# ARM DDI 0100D-10<br />
• <strong>Intel</strong> 80200 Developers’ manual, Order# 273411-002 [http://developer.intel.com]<br />
Or later updated versions of any of the above.<br />
This appendix is separated into sections that focus on three different issues:<br />
1. SA-1110 hardware migration issues<br />
— Hardware Compatibility<br />
—Signal Changes<br />
— Power Delivery<br />
— Package<br />
—Clocks<br />
—UCB1300<br />
2. SA-1110 software migration issues<br />
— Software Compatibility<br />
— Address space<br />
— Page Table Changes<br />
— Configuration registers<br />
—DMA<br />
3. Using new features in the applications processor<br />
<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide A-1
SA-1110/<strong>Applications</strong> Processor Migration<br />
— <strong>Intel</strong>® XScale microarchitecture<br />
—Debugging<br />
- Cache attributes<br />
- Other Features<br />
- Conclusion<br />
A.1 SA-1110 Hardware Migration Issues<br />
A.1.1<br />
Hardware Compatibility<br />
The majority of the features provided in the SA-1110 are also provided in the <strong>PXA250</strong> applications<br />
processor. However, with the additional functionality of the <strong>PXA250</strong> applications processor, the<br />
two devices are not pin compatible <strong>and</strong> cannot occupy the same socket.<br />
There has been an effort to ensure Companion Devices that take advantage of SA-1110 memory<br />
interface access works with the <strong>PXA250</strong> applications processor. The memory controls for taking<br />
over the memory bus such as those exercised by the SA-1111, are included in the <strong>PXA250</strong><br />
applications processor memory bus interface however, there are some issues.<br />
One difference in particular is the way <strong>PXA250</strong> applications processor toggles the A1 <strong>and</strong> A0<br />
address lines. The SA-1110 toggled A1 <strong>and</strong> A0 regardless of the size of the data bus. With<br />
<strong>PXA250</strong>, if the data bus is set to 16-bit, then A0 does not toggle <strong>and</strong> if the data bus is set to 32-bit,<br />
then neither A1 nor A0 toggles.<br />
There is a big difference in manufacturing technology between the SA-1110 <strong>and</strong> the <strong>PXA250</strong><br />
applications processors. The most significant change being from a 0.35 micron CMOS technology<br />
to a finer lithography of 0.18 microns. Aside from a potential impact to signal edge rates this<br />
allows for lower applications processor voltage operation.<br />
A.1.2<br />
Signal Changes<br />
There are two pins that control SA-1110 boot-up:<br />
• ROM select pin that selects a 16 or 32-bit interface<br />
• Synchronous Mask ROM enable pin that selects a synchronous or asynchronous ROM access<br />
The <strong>PXA250</strong> applications processor has three pins that select eight different boot select options<br />
(see Table A-1. The subset of these options that are SA-1110 equivalent are not compatible with the<br />
<strong>PXA250</strong> applications processor pin polarities, so these pins must be selected afresh when<br />
designing with the <strong>PXA250</strong> applications processor.<br />
Table A-1. <strong>PXA250</strong> Boot Select Options (Sheet 1 of 2)<br />
Boot Select Pins<br />
2 1 0<br />
Boot Location<br />
0 0 0 Asynchronous 32-bit ROM<br />
0 0 1 Asynchronous 16-bit ROM<br />
0 1 0 Synchronous 32-bit Flash<br />
A-2 <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide
SA-1110/<strong>Applications</strong> Processor Migration<br />
Table A-1. <strong>PXA250</strong> Boot Select Options (Sheet 2 of 2)<br />
Boot Select Pins<br />
2 1 0<br />
Boot Location<br />
0 1 1 Synchronous 16-bit Flash<br />
1 0 0<br />
(1) Synchronous 32-bit Mask ROM (64 Mbit)<br />
(2) Synchronous 16-bit Mask ROM = 32bits (32 Mbit)<br />
1 0 1 (1) Synchronous 16-bit Mask ROM (64 Mbit)<br />
1 1 0 (2) Synchronous 16-bit Mask ROM = 32bits (64 Mbit)<br />
1 1 1 (1) Synchronous 16-bit Mask ROM (32 Mbit)<br />
The power fault (VDD_FAULT) <strong>and</strong> battery fault (BATT_FAULT) pins that drive the SA-1110<br />
sleep mode are negated with respect to the <strong>PXA250</strong> applications processor. You must invert these<br />
signals or change the design to make sure that these signals are negated with respect to the SA-<br />
1110 design.<br />
The <strong>PXA250</strong> applications processor treats variable latency IO differently than the SA-1110. The<br />
difference occurs only when a static chip select is configured to support variable latency IO, i.e. the<br />
bus cycle is to be extended by a value on the RDY pin. In this configuration, the SDRAM refresh<br />
cycle retains the use of the nWE pin to allow the memory bus to be held for an indeterminate time.<br />
During any variable latency IO cycle, the PCMCIA pin nPWE is used to write to an external device<br />
instead of the nWE pin.<br />
Note:<br />
Holding the bus for extended periods is not recommended because it interferes with the LCD DMA<br />
<strong>and</strong> prevents an LCD panel refresh.<br />
This change in write enables only causes an issue if an external companion bus master device has a<br />
single write enable pin <strong>and</strong> requires variable latency IO to be accessed. As shown in Figure A-1,<br />
the write enable to the companion master has to be gated to differentiate between a case where the<br />
<strong>PXA250</strong> applications processor uses the WE to write to the companion <strong>and</strong> a case where the<br />
companion uses the WE to write into SDRAM memory. Gating the WE pin with the Bus Grant<br />
signal (as shown) segregates the two different memory bus cycle types. If the companion bus<br />
master has both a WE input pin <strong>and</strong> a WE output pin to SDRAM, this logic is unnecessary.<br />
Figure A-1. Write Enable Control Pins<br />
SDRAM<br />
~MBGNT<br />
<strong>PXA250</strong><br />
nWE<br />
nPWE<br />
WE#<br />
SA-1110<br />
Companion<br />
Device<br />
MBGNT<br />
<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide A-3
SA-1110/<strong>Applications</strong> Processor Migration<br />
A.1.3<br />
Power Delivery<br />
Although both products are tolerant to 3.3 V inputs <strong>and</strong> outputs, there is a difference in the supply<br />
voltage that drives the transistors of the microprocessor megacell. The <strong>PXA250</strong> applications<br />
processor takes advantage of lower supply voltages to offer substantial power consumption<br />
savings. A design using SA-1110 has a supply voltage of 1.55 V to 1.75 V. The <strong>PXA250</strong><br />
applications processor is rated to 1.4 V maximum.<br />
Drive the <strong>PXA250</strong> applications processor core voltage pins at a lower voltage than the SA-1110 to<br />
reduce overall power consumption. The choice of voltage impacts the maximum upper frequency<br />
of operation so check the <strong>PXA250</strong> documentation for the correct voltages as they are application<br />
dependent.<br />
Also notice that the <strong>PXA250</strong> applications processor supports independent power sources for Core,<br />
IO, Memory Bus, phase lock loops (PLLs), <strong>and</strong> a backup battery. It is recommended that these be<br />
independent power sources.<br />
A.1.4<br />
Package<br />
The SA-1110 <strong>and</strong> the <strong>PXA250</strong> applications processors are similar but not identical. The ball pitch<br />
of 1 mm is the same <strong>and</strong> the body outlines are both 17x17 mm but the heights are different. The<br />
<strong>PXA250</strong> applications processor contains 4-layers within the package making it fractionally thicker<br />
than the SA-1110 2-layer package.<br />
When migrating to the <strong>PXA210</strong> applications processor there a few limits to functionality:<br />
• The upper 16-bits of the databus are unavailable<br />
• Only two of the primary GPIO pins are available<br />
• The upper two SDRAM bank strobes are unavailable<br />
• UART hardware flow control <strong>and</strong> external DMA are not accessible<br />
This smaller package than the SA-1110 accommodates a lower overall power envelope that may<br />
restrict upper voltage operation <strong>and</strong> maximum frequency for power consumption reasons. The ball<br />
pitch is reduced to 0.8 mm <strong>and</strong> the package is much thinner than the mBGA.<br />
A.1.5<br />
Clocks<br />
The crystal inputs for the <strong>PXA250</strong> applications processor are at the same frequency as those for the<br />
SA-1110:<br />
• High frequency input of 3.6864 MHz<br />
• Slow real-time clock source of 32.768 KHz.<br />
The input frequency requirements are relatively low, such that any crystal that is an AT-cut style<br />
with a certain amount of shunt capacitance will work for both products.<br />
The actual PLL design <strong>and</strong> process technology is different between the two products, such that a<br />
marginal SA-1110 design may not work with the <strong>PXA250</strong> applications processor. Please refer to<br />
the product specifications of each device for further details.<br />
A-4 <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide
SA-1110/<strong>Applications</strong> Processor Migration<br />
You can program GPIO pins to generate various clocks in both the SA-1110 <strong>and</strong> the <strong>PXA250</strong><br />
applications processors. For example, these are often used in audio codec designs to generate<br />
clocks. The inter-relationships of some of these clocks have changed from the SA-1110 to the<br />
<strong>PXA250</strong> applications processor. You may need to select different GPIO pins <strong>and</strong> program different<br />
configuration registers to provide similar functionality.<br />
A.1.6<br />
UCB1300<br />
The SA-1110 supports a unique serial protocol for communication with the Philip’s UCB product<br />
family: UCB1100, 1200 <strong>and</strong> 1300. This serial interface is not available on the <strong>PXA250</strong><br />
applications processor. Instead the <strong>PXA250</strong> applications processor supports several industry<br />
st<strong>and</strong>ard Audio codec Interfaces. You may also use I 2 S/I 2 C combinations <strong>and</strong> an AC’97 interface.<br />
If an SA-1110 design utilizes this UCB interface then an alternative choice of components is<br />
necessary for the <strong>PXA250</strong> applications processor.<br />
A.2 SA-1110 to <strong>PXA250</strong> Software Migration Issues<br />
The difficulty of migrating software from the SA-1110 to the <strong>PXA250</strong> applications processor<br />
depends on the amount of hardware <strong>and</strong> software interaction. SA-1110 applications running under<br />
an Operating System, which use device driver interfaces, should move seamlessly between the two<br />
devices.<br />
There is one exception; any application that explicitly uses the Read Buffer to prefetch external<br />
memory data into the SA-1110. This buffer does not exist on the <strong>PXA250</strong> applications processor<br />
<strong>and</strong> register #9 in Coprocessor #15 that was used to access it are not compatible to software.<br />
As the Read Buffer prefetching activity was deemed to be a hint rather than an instruction,<br />
applications can simply delete all references to the Read Buffer <strong>and</strong> still function correctly. They<br />
may not even suffer a performance penalty, as the <strong>PXA250</strong> ’hit-under-miss’ cache feature can turn<br />
the entire data space into a prefetchable region without any explicit software direction.<br />
Alternately, as a patch for software that cannot be modified, all applications must be limited to<br />
User Mode execution, whereupon an Exception can be generated for all Coprocessor activity.<br />
Such an exception manager needs to filter out the Read Buffer coprocessor calls, or convert them to<br />
<strong>PXA250</strong> PLD instructions that can preload a data cache value.<br />
There are major software difference within the device initialization/configuration software <strong>and</strong><br />
device drivers, such as low-level code that controls the hardware.<br />
The <strong>PXA250</strong> applications processor has enhanced functionality <strong>and</strong> extra instructions not found in<br />
the SA-1110. The <strong>PXA250</strong> applications processor software is not backward compatibility to the<br />
SA-1110. Once code is compiled for the <strong>PXA250</strong> applications processor it is unlikely to run on the<br />
SA-1110.<br />
<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide A-5
SA-1110/<strong>Applications</strong> Processor Migration<br />
A.2.1<br />
Software Compatibility<br />
Because the <strong>PXA250</strong> applications processor uses <strong>Intel</strong>® XScale microarchitecture, the <strong>PXA250</strong><br />
applications processor has a different pipeline length relative to the SA-1110. This effects code<br />
performance when migrating between the two devices varies because of the number of clock cycles<br />
needed for execution. Any application that relies on specific cycle counts, or has specific timing<br />
components, will show a difference in performance.<br />
The <strong>PXA250</strong> applications processor features: larger caches, Branch target buffering, <strong>and</strong> faster<br />
multiplication, <strong>and</strong> so many applications run faster than the SA-1110 when running at the same<br />
clock frequency.<br />
A.2.2<br />
Address space<br />
The physical address mapping of gross memory regions is not compatible between the <strong>PXA250</strong><br />
applications processor <strong>and</strong> SA-1110. For example, on the <strong>PXA250</strong> applications processor, Static<br />
chip selects 4 <strong>and</strong> 5 are lower in memory than PCMCIA, on the SA-1110 they are higher in the<br />
memory space.<br />
Changes of this kind could be managed by the Operating System remapping virtual memory pages<br />
to new physical addresses. This assumes that the Operating System has basic support for virtual<br />
memory, but not if this could be managed by initialization code modifications effecting the same<br />
change.<br />
More significantly, memory-mapped registers may have different names, new addresses <strong>and</strong><br />
different functionality. This impacts all device drivers <strong>and</strong> register-level firmware, that at a<br />
minimum, requires re-mapping register address <strong>and</strong> changing the default configuration.<br />
A.2.3<br />
Page Table Changes<br />
There are differences in the virtual memory Page Table Descriptors between the SA-1110 <strong>and</strong> the<br />
<strong>PXA250</strong> applications processors that impact software execution speed. A new bit has been added<br />
to differentiate ARM* compliant operation modes from some features <strong>Intel</strong> includes such as access<br />
to the Mini-Data-Cache.<br />
If any software attempts to explicitly control page table modifications, normally the domain of the<br />
Operating System, then that software may need annotation to allow for the extra opportunities the<br />
<strong>PXA250</strong> applications processor offers.<br />
Any SA-1110 code that explicitly uses the Mini-Data-Cache is executed correctly, but it's ability to<br />
utilize a different cache is lost without a page table bit being changed. The impact here is<br />
performance not functionality.<br />
A.2.4<br />
Configuration registers<br />
There are numerous device configuration changes in the <strong>PXA250</strong> applications processor. You must<br />
now select the configuration options for clock speeds such as Turbo Mode. This requirement is not<br />
found on the SA-1110.<br />
A-6 <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide
SA-1110/<strong>Applications</strong> Processor Migration<br />
You must choose memory clocks, LCD clock rates, audio clocks <strong>and</strong> interfaces, which GPIOs are<br />
actually connected to hardware, <strong>and</strong> many more. There are no easy solutions here, the device<br />
space of the <strong>PXA250</strong> applications processor is very diverse <strong>and</strong> a number of selections must be<br />
made in software to select your particular hardware functionality.<br />
All software that controls registers will need to be updated. If a switch is connected to a GPIO, then<br />
the software that reads the switch register will differ between the <strong>PXA250</strong> applications processor<br />
<strong>and</strong> SA-1110. This applies to software that controls Configuration registers in Coprocessor space<br />
<strong>and</strong> also to a number of the memory-mapped registers. Many functions such as memory timing<br />
configuration are done through these registers. For example the registers to access USB have a<br />
different name, address <strong>and</strong> function. Any code that directly accesses the USB hardware registers<br />
will need to be rewritten.<br />
A.2.5<br />
DMA<br />
The SA-1110 contains a 6-channel DMA controller that pipes data between the serial channels <strong>and</strong><br />
memory. The <strong>PXA250</strong> applications processor provides a far more substantial 16-channel chained<br />
DMA controller that can be configured to do much more than the SA-1110, including memory-tomemory<br />
block moves.<br />
Clearly there are changes in software required to take advantage of this new asset. However this<br />
also implies changes necessary to maintain similar functionality to the SA-1110. To configure a<br />
DMA channel you no longer set it to a specific serial port, instead you map it to the specific source<br />
or destination address of the serial port FIFO. You must configure other parameters for address<br />
incrementing <strong>and</strong> memory width that differ between the <strong>PXA250</strong> applications processor <strong>and</strong> SA-<br />
1110.<br />
Any device driver using the SA-1110 DMA controller, or application that takes direct advantage of<br />
DMA, will need to be modified. The impact of this varies as some Operating Systems <strong>and</strong> many<br />
device drivers have ignored the SA-1110 DMA in favor of programmed I/O.<br />
Some have argued to remove the required interrupt management code as they only move small<br />
blocks. Operating systems have excluded DMA to guarantee they can manage the real-time<br />
behavior of different threads. Other software providers saw the serial ports as so slow that DMA<br />
performance was unnecessarily complex.<br />
The performance benefit of the <strong>PXA250</strong> DMA controller is one of the most significant<br />
improvements over the SA-1110, particularly in the area of memory-to-memory moves. Changing<br />
code on the <strong>PXA250</strong> applications processor to utilize the new DMA functionality will significantly<br />
enhance applications.<br />
A.3 Using New <strong>PXA250</strong> Features<br />
This appendix doesn’t attempt to discuss all the differences between the <strong>PXA250</strong> applications<br />
processor <strong>and</strong> the SA-1110 or it would become quite substantial. There are numerous significant<br />
advantages that the <strong>PXA250</strong> applications processor has to offer, all of which potentially require<br />
changes in hardware, firmware or software development tools. This section lists just a few of the<br />
chief additional benefits of the <strong>PXA250</strong> applications processor. However, refer to the product<br />
specifications for further details. This list is not comprehensive.<br />
<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide A-7
SA-1110/<strong>Applications</strong> Processor Migration<br />
A.3.1<br />
<strong>Intel</strong>® XScale Microarchitecture<br />
The <strong>PXA250</strong> applications processor is a system on a chip that includes <strong>Intel</strong>’s new microprocessor<br />
megacell. This includes <strong>Intel</strong>® Superpipelined Technology <strong>and</strong> a new optimized cache<br />
architecture that allows program execution to continue despite data cache misses.<br />
The <strong>PXA250</strong> applications processor supports:<br />
• ARM* Architecture v5 instructions, including ARM’s Thumb extensions<br />
• DSP Extensions but not ARM’s optional Vector Floating Point instructions<br />
Appendix A in the <strong>Intel</strong> 80200 Developers’ manual, Order# 273411-002 [http://<br />
developer.intel.com], is the best guide to the new capabilities available in the <strong>Intel</strong>® XScale<br />
Megacell's Instruction Set.<br />
Using a software development toolset that takes specific advantage of <strong>Intel</strong>® XScale<br />
microarchitecture, <strong>and</strong> <strong>Intel</strong>® Media Processing Technology could give you substantial<br />
performance benefits.<br />
The <strong>PXA250</strong> applications processor offers increased performance at similar clock rates, <strong>and</strong> also a<br />
wider range of operating clock rates at lower voltages. The overall benefit is more work done for<br />
less battery power.<br />
A.3.2<br />
Debugging<br />
New <strong>PXA250</strong> hardware creates new debugging possibilities. You can use the JTAG test port to<br />
download programs into a dedicated memory area to act as a debug monitor. <strong>Applications</strong> can be<br />
inspected <strong>and</strong> performance data, such as cache hit rates, can be measured via a dialog over JTAG.<br />
These features offer developers far more visibility inside a <strong>PXA250</strong> system improving time to<br />
market.<br />
A.3.3<br />
Cache Attributes<br />
The <strong>PXA250</strong> applications processor has twice the instruction cache <strong>and</strong> four times the data cache<br />
of the SA-1110. The Caches can be locked for optimized code or data <strong>and</strong> for reliability the caches<br />
are now covered by parity protection.<br />
To take advantage of cache locking software, data must be selected <strong>and</strong> specifically loaded <strong>and</strong><br />
locked into cache.<br />
To take advantage of new features such as Write-Through mode for external IO buffers, page tables<br />
will need to be revisited in boot software.<br />
A.3.4<br />
Other features<br />
As mentioned before, the <strong>PXA250</strong> DMA controller is highly versatile. With 16 channels it can be<br />
utilized as:<br />
• Several serial ports in parallel<br />
• A general-purpose memory move capability<br />
• A fast interface for external companion devices<br />
A-8 <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide
SA-1110/<strong>Applications</strong> Processor Migration<br />
Additional software is required to access these benefits.<br />
A similar story is true for AC’97, I2C, GPIOs, MMC <strong>and</strong> others. The benefits are substantial, but<br />
new hardware <strong>and</strong> software will be necessary to effectively use the <strong>PXA250</strong> applications<br />
processor.<br />
A.3.5<br />
Conclusion<br />
Although most application software will migrate unchanged between SA-1110 <strong>and</strong> the <strong>PXA250</strong><br />
applications processors, the underlying microarchitectures are radically different. The <strong>PXA250</strong><br />
applications processor being considerably more ornate <strong>and</strong> capable than the SA-1110. The majority<br />
of hardware <strong>and</strong> low-level software from any SA-1110 design will need to be redesigned. with a<br />
view to taking full advantage of the new features that the <strong>PXA250</strong> applications processor brings to<br />
the h<strong>and</strong>held market.<br />
<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide A-9
SA-1110/<strong>Applications</strong> Processor Migration<br />
A-10 <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide
Example Form Factor Reference Design<br />
Schematic Diagrams<br />
B<br />
B.1 Notes<br />
The example form factor reference design schematics in this appendix have known issues <strong>and</strong><br />
assumptions that need to be assessed for each board design. This appendix documents the issues<br />
that have been discovered <strong>and</strong> provides revision data for the schematics. This appendix also points<br />
out some of the design specific assumptions that were made in designing this board.<br />
Page 4: The schematic supports the SA1110 legacy mode for addressing the SDRAM. See<br />
SDRAM section of the design guidelines to explain normal vs. legacy addressing modes.<br />
Page 10: U26 allows the CF card to access the I 2 C interface.<br />
Page 11: The MMC slot has resistor jumpers to select SDCARD <strong>and</strong>/or MMC card support. If the<br />
users wants to support both SCARD <strong>and</strong> MMC, populate the resistor values in the SD column of<br />
the CARD selection table. If MMC card support only populate the resistors under the MMC<br />
column in the table.<br />
Page 11: The JTAG port on this board assumes that it is connected to a specific JTAG bridge board.<br />
If you follow this design guide, you should not need the bridge board. See the JTAG section of this<br />
document for more details on this bridge board implementation.<br />
Page 11: J19 pin 9 requires a 1.5 k pull down.<br />
Page 13: U33, U34, U35, U40, <strong>and</strong> surrounding circuits are to support a legacy sharp LCD. Refer<br />
to that vendor’s design guidelines if you are integrating a different LCD display.<br />
Page 14: U36, U37, U39, J13, <strong>and</strong> surrounding circuits including the resistor divider network in the<br />
upper left h<strong>and</strong> corner support a legacy Sharp LCD. Refer to that vendor’s design guidelines if you<br />
are integrating a different LCD display.<br />
Page 14: J14 is the Toshiba LCD connector. Confirm the pinout before layout.<br />
B.2 Schematic Diagrams<br />
The example form factor reference design schematics are on the following pages.<br />
<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide B-1
8<br />
D D<br />
A A<br />
<strong>PXA250</strong> Processor Reference Design<br />
Rev 2.07<br />
1<br />
Pg.1<br />
Sheet 1 of 16<br />
1<br />
7<br />
6<br />
5<br />
4<br />
3<br />
2<br />
Copyright 2002 <strong>Intel</strong> Corporation<br />
Example Form Factor Reference Design for <strong>PXA250</strong><br />
Page Description<br />
C C<br />
1 Cover Sheet<br />
2-3 <strong>PXA250</strong> Processor<br />
4 SDRAM, System Configuration Register<br />
5 <strong>Intel</strong> Flash Memory (BGA)<br />
6 Buffer, CPLD, Board Control Register<br />
7 Transceivers<br />
8 Audio Codec, Audio AMP<br />
9 Headset Jack, Microphone, Stereo Jack, Speaker, Dual Axis Accelerometer, IrDA, USB<br />
10 Basestation Hdr, RS232 Xcvr, CF Socket, Function Switches<br />
11 SD socket, Radio Header, JTAG Port<br />
12 Boost Buck Power , Battery Header, Battery On Jumper<br />
13 LCD CPLD, LCD Power, Back Light Connector<br />
14 LCD Connectors, 9 Channel Buffer, Touch Screen Connector<br />
15 Bus Connectors, 2-140 Pin<br />
16 Schematic Revision Page<br />
B B<br />
Size Rev<br />
B<br />
2.07<br />
8<br />
7<br />
6<br />
5<br />
4<br />
3<br />
Date:<br />
Tuesday, February 05, 2002<br />
2
8<br />
1<br />
7<br />
6<br />
5<br />
4<br />
3<br />
2<br />
Copyright 2002 <strong>Intel</strong> Corporation<br />
22.1 R256<br />
{6,15} SA_nCS_5<br />
C12<br />
{4,5,7} SA_A20<br />
{9} SA_UDCP<br />
10K<br />
B12<br />
USB Ch<br />
R257 22.1<br />
{9} SA_UDCN<br />
nCS_0<br />
N8<br />
SA_nCS_0 {6,15}<br />
{4,5,7} SA_A21<br />
nCS_1_GPIO15<br />
T8<br />
SA_nCS_1<br />
C15<br />
P9<br />
{6}<br />
{9} IR_TXD<br />
SA_nCS_2 {6}<br />
R267<br />
22.1 R258<br />
IR_TXD_GPIO47<br />
IrDA Ch<br />
nCS_2_GPIO78<br />
{6,15} SA_nPCE_1<br />
{4,5,7} SA_A22<br />
{9} IR_RXD<br />
B15<br />
IR_RXD_GPIO46<br />
nCS_3_GPIO79<br />
T9<br />
SA_nCS_3 {6,15}<br />
100K<br />
R13<br />
R259 22.1<br />
nCS_4_GPIO80<br />
SA_nCS_4<br />
B14<br />
{6,15}<br />
{4,5,7} SA_A23<br />
{11} SA_BT_RTS BT_RTS_GPIO45<br />
nCS_5_GPIO33<br />
T13<br />
SA_nCS_5<br />
A15<br />
{6,15} R268<br />
22.1 R260<br />
{11} SA_BT_CTS BT_CTS_GPIO44<br />
BT Ch<br />
{6,15} SA_nPCE_2<br />
D13<br />
{4,5,7} SA_A24<br />
{11,15} SA_BT_TXD<br />
BT_TXD_GPIO43<br />
{11,15} SA_BT_RXD<br />
SA_DQM_0 {4,7}<br />
100K<br />
B13<br />
M8<br />
R261 22.1<br />
BT_RXD_GPIO42<br />
DQM_0<br />
{6,7} SA_A25<br />
DQM_1<br />
B1<br />
SA_DQM_1<br />
B9<br />
B2<br />
{4,7}<br />
SA_DQM_2 {4,7}<br />
R269<br />
22.1<br />
EXTCLK_GPIO27<br />
DQM_2<br />
{6,15} SA_RD_nWR<br />
E9<br />
R10<br />
SFRM_C_GPIO24<br />
DQM_3<br />
L7<br />
SA_DQM_3 {4,7}<br />
100K<br />
F9<br />
{11} RADIO_RI<br />
SCLK_C_GPIO23<br />
0 R9<br />
D9<br />
TXD_C_GPIO25<br />
F1<br />
SA_nSDCS_0 {4,7}<br />
SSP Ch<br />
nSDCS_0<br />
A9<br />
G6<br />
R281<br />
{11} RADIO_DTR<br />
RXD_C_GPIO26<br />
nSDCS_1<br />
{3,12} nCHRGR_PRESENT<br />
R8 0<br />
nSDCS_2<br />
G3<br />
SA_nSDCS_2 {6}<br />
100K<br />
D14<br />
F2<br />
{11} RADIO_DSR<br />
MMCCMD<br />
0<br />
MMC<br />
nSDCS_3<br />
B16<br />
R7<br />
MMCDAT<br />
H14<br />
E4<br />
R272<br />
{11} RADIO_DCD<br />
MMCCLK_GPIO6<br />
SDCKE_0<br />
SA_SDCKE_0 {15}<br />
F14<br />
E3<br />
R6<br />
0<br />
MMCCS0_GPIO8<br />
SDCKE_1<br />
SA_SDCKE_1 {4,6} {3,6,15} MBGNT_CF_IRQ<br />
B6<br />
{11} MMC_WP<br />
nMMCCD_GPIO12<br />
4.99K<br />
0<br />
SDCLK_0<br />
D2<br />
SA_SDCLK_0 {5,15}<br />
B10<br />
F5<br />
{10} SA_FF_RI FF_RI_GPIO38<br />
SA_SDCLK_1 {4,7}<br />
A12<br />
FF Ch<br />
SDCLK_1<br />
D1<br />
R148<br />
{10} SA_FF_DCD FF_DCD_GPIO36<br />
SDCLK_2<br />
SA_SDCLK_2 {6}<br />
B11<br />
{11} RADIO_RXD_C<br />
{10} SA_FF_DSR FF_DSR_GPIO37<br />
0<br />
F10<br />
E1<br />
SA_nSDRAS {4,6,7}<br />
DNI<br />
{10} SA_FF_DTR FF_DTR_GPIO40<br />
nSDRAS<br />
F8<br />
F3<br />
{10} SA_FF_RTS FF_RTS_GPIO41<br />
nSDCAS<br />
SA_nSDCAS {4,5,6,7}<br />
A14<br />
{10} SA_FF_CTS FF_CTS_GPIO35<br />
R11<br />
E13<br />
G5<br />
{10,15} SA_FF_TXD<br />
FF_TXD_GPIO39<br />
nOE<br />
SA_nOE<br />
A13<br />
G4<br />
{5,7}<br />
{11} SA_MMCMD<br />
{10,15} SA_FF_RXD<br />
FF_RXD_GPIO34<br />
nWE<br />
SA_nWE {4,5,6,7,10}<br />
DC3P3V<br />
R205<br />
Pg.2<br />
{6} SA_A0<br />
R237 22.1<br />
U1A<br />
{6} SA_A1<br />
R1<br />
22.1 R238<br />
{6,15} SA_nPWAIT<br />
{5,6} SA_A2<br />
<strong>Intel</strong> <strong>PXA250</strong> Processor<br />
100K<br />
R239 22.1<br />
G1<br />
N4<br />
{5,6} SA_A3<br />
A_0<br />
D_0<br />
SA_D0<br />
H2<br />
M5<br />
{4,5,6,7}<br />
SA_D1 {4,5,6,7}<br />
R2<br />
22.1 R240<br />
A_1<br />
D_1<br />
{6,15} SA_nIOIS16<br />
H1<br />
{5,7} SA_A4<br />
A_2<br />
D_2<br />
L5<br />
SA_D2 {4,5,6,7}<br />
SA_D3 {4,5,6,7}<br />
100K<br />
H6<br />
T6<br />
R241 22.1<br />
A_3<br />
D_3<br />
J6<br />
{5,7} SA_A5<br />
A_4<br />
D_4<br />
N6<br />
SA_D4<br />
J5<br />
T7<br />
{4,5,6,7}<br />
SA_D5 {4,5,6,7}<br />
R3<br />
22.1 R242<br />
A_5<br />
D_5<br />
{15} SA_RDY<br />
J3<br />
{5,7} SA_A6<br />
A_6<br />
D_6<br />
M6<br />
SA_D6 {4,5,6,7}<br />
SA_D7 {4,5,6,7}<br />
100K<br />
J1 Address <strong>and</strong> Data Buses<br />
M7<br />
R243 22.1<br />
A_7<br />
D_7<br />
{5,7} SA_A7<br />
K1<br />
M9<br />
SA_D8 {4,5,6,7}<br />
R4<br />
A_8<br />
D_8<br />
K2<br />
T10<br />
22.1 R244<br />
A_9<br />
D_9<br />
SA_D9 {10,12,15} SA_I2C_SCL<br />
K5<br />
R9<br />
{4,5,6,7}<br />
{5,7} SA_A8<br />
SA_D10 {4,5,6,7}<br />
4.99K<br />
A_10<br />
D_10<br />
K6<br />
T11<br />
R245 22.1<br />
A_11<br />
D_11<br />
SA_D11<br />
L1<br />
{4,5,6,7}<br />
{5,7} SA_A9<br />
SA_D12 {4,5,6,7}<br />
R5<br />
A_12<br />
D_12<br />
P11<br />
L3<br />
N10<br />
22.1 R246<br />
A_13<br />
D_13<br />
SA_D13 {10,12,15} SA_I2C_SDA<br />
M1<br />
{4,5,6,7}<br />
{4,5,7} SA_A10<br />
A_14<br />
D_14<br />
T12<br />
SA_D14<br />
M3<br />
{4,5,6,7}<br />
SA_D15 {4,5,6,7}<br />
4.99K<br />
R247 22.1<br />
A_15<br />
D_15<br />
M10<br />
N3<br />
{4,5,7} SA_A11<br />
A_16<br />
D_16<br />
H3<br />
SA_D16<br />
P1<br />
{4,5,7}<br />
SA_D17 {4,5,7}<br />
R137<br />
22.1 R248<br />
A_17<br />
D_17<br />
H5<br />
{6} SA_nCS_1<br />
{4,5,7} SA_A12<br />
R1<br />
A_18<br />
D_18<br />
J4<br />
SA_D18 {4,5,7}<br />
100K<br />
P2<br />
R249 22.1<br />
A_19<br />
D_19<br />
K3<br />
SA_D19<br />
R3<br />
{4,5,7}<br />
{4,5,7} SA_A13<br />
A_20<br />
D_20<br />
L4<br />
SA_D20<br />
T4<br />
{4,5,7}<br />
SA_D21 {4,5,7}<br />
R263<br />
22.1 R250<br />
A_21<br />
D_21<br />
M2<br />
{6} SA_nCS_2<br />
R5<br />
{4,5,7} SA_A14<br />
A_22<br />
D_22<br />
N1<br />
SA_D22 {4,5,7}<br />
SA_D23 {4,5,7}<br />
100K<br />
P5<br />
R251 22.1<br />
A_23<br />
D_23<br />
T3<br />
T5<br />
{4,5,7} SA_A15<br />
A_24<br />
D_24<br />
P6<br />
SA_D24<br />
P4<br />
R7<br />
{4,5,7}<br />
SA_D25 {4,5,7}<br />
R264<br />
22.1 R252<br />
A_25<br />
D_25<br />
{6,15} SA_nCS_3<br />
{4,5,7} SA_A16<br />
D_26<br />
P7<br />
SA_D26 {4,5,7}<br />
SA_D27 {4,5,7}<br />
100K<br />
R253 22.1<br />
D_27<br />
P8<br />
{4,5,7} SA_A17<br />
D_28<br />
L8<br />
SA_D28 {4,5,7}<br />
SA_D29 {4,5,7}<br />
R265<br />
22.1 R254<br />
D_29<br />
P10<br />
{6,15} SA_nCS_4<br />
{4,5,7} SA_A18<br />
D_30<br />
R11<br />
SA_D30 {4,5,7}<br />
10K<br />
D11<br />
R255 22.1<br />
{10,12,15} SA_I2C_SCL<br />
SCL<br />
SA_D31<br />
I2C<br />
D_31<br />
P12<br />
A11<br />
{4,5,7}<br />
{4,5,7} SA_A19<br />
{10,12,15} SA_I2C_SDA<br />
SDA<br />
R266<br />
D D<br />
C C<br />
B B<br />
R12 47.5<br />
P13<br />
D3<br />
{11} SA_MMDAT<br />
{6,15} SA_nPOE<br />
nPOE_GPIO48<br />
RD_nWR<br />
SA_RD_nWR {6,15}<br />
47.5 R13<br />
{6,15} SA_nPWE<br />
T14<br />
nPWE_GPIO49<br />
RDY_GPIO18<br />
C1<br />
SA_RDY {15}<br />
{11} SA_MMCCLK<br />
{6,15} SA_nPIOR<br />
T15<br />
nPIOR_GPIO50<br />
R15<br />
N15<br />
47.5<br />
{6,15} SA_nPIOW<br />
nPIOW_GPIO51<br />
DVAL_0_GPIO21<br />
GPIO_21 {10,11}<br />
{11} MMC_CS0<br />
{6,15} SA_nPCE_1<br />
P14<br />
nPCE_1_GPIO52<br />
DVAL_1_GPIO22<br />
M12<br />
GPIO_22 {10,11}<br />
{6,15} SA_nPCE_2<br />
R16<br />
nPCE_2_GPIO53<br />
DREQ_0_GPIO20<br />
N12<br />
GPIO_20<br />
P16<br />
N14<br />
{10,11}<br />
{11,13} nMMC_DETECT<br />
{15} SA_PSKTSEL<br />
PSKTSEL_GPIO54 DREQ_1_GPIO19<br />
GPIO_19 {10,11}<br />
{6,15} SA_nPREG<br />
M13<br />
nPREG_GPIO55<br />
N16<br />
{6,15} SA_nPWAIT<br />
nPWAIT_GPIO56<br />
M16<br />
D10<br />
{6,15} SA_nIOIS16<br />
nI0IS16_GPIO57<br />
SA_nAC97_RESET {8}<br />
AC97<br />
nAC97_RESET<br />
SYNC_GPIO31<br />
E11<br />
SA_SYNC<br />
F15<br />
A10<br />
{8}<br />
NC1<br />
SDATA_OUT_GPIO30<br />
SA_SDATA_OUT {8}<br />
D16<br />
NC2<br />
SDATA_IN0_GPIO29<br />
E10<br />
SA_SDATA_IN {8}<br />
E15<br />
NC3<br />
BITCLK_GPIO28<br />
C9<br />
SA_BITCLK<br />
E16<br />
{8} <strong>PXA250</strong> Processor Reference Design<br />
NC4<br />
F16<br />
NC5<br />
PWM_0_GPIO16<br />
E12<br />
SA_PWM_0 {13}<br />
A A<br />
8<br />
7<br />
6<br />
5<br />
4<br />
CARD Interface<br />
Memory Control<br />
Pulse Width<br />
<strong>PXA250</strong>_MBGA256<br />
3<br />
Size Rev<br />
B<br />
2.07<br />
Date:<br />
Tuesday, February 05, 2002<br />
2<br />
Sheet 2 of 16<br />
1
8<br />
1<br />
Pg.3<br />
Sheet 3 of 16<br />
1<br />
7<br />
6<br />
5<br />
4<br />
3<br />
2<br />
Copyright 2002 <strong>Intel</strong> Corporation<br />
U1B<br />
<strong>Intel</strong> <strong>PXA250</strong> Processor<br />
DC3P3V DC3P3V<br />
DC3P3V<br />
L_DD_0_GPIO58<br />
E7<br />
L_DD_0<br />
L10<br />
{13}<br />
{10,15}<br />
GPIO_0<br />
L_DD_1_GPIO59<br />
D7<br />
L_DD_1 {13}<br />
{9,15}<br />
L12<br />
USB_WAKE<br />
GPIO_1<br />
L_DD_2_GPIO60<br />
C7<br />
L_DD_2<br />
L13<br />
{13}<br />
{10} SA_I2C_ENAB<br />
GPIO_2<br />
L_DD_3_GPIO61<br />
B7<br />
L_DD_3<br />
K14<br />
{13}<br />
{10,15} GFX_IRQ_CF_BVD2<br />
GPIO_3<br />
L_DD_4_GPIO62<br />
E6<br />
L_DD_4<br />
D {10} RS232_VALID<br />
J12<br />
{13}<br />
GPIO_4<br />
L_DD_5_GPIO63<br />
D6<br />
L_DD_5 D<br />
J11<br />
{13}<br />
DNI DNI DNI<br />
{2,12} nCHRGR_PRESENT<br />
GPIO_5<br />
L_DD_6_GPIO64<br />
E5<br />
L_DD_6<br />
G15<br />
{13}<br />
{8} AC97_IRQ<br />
GPIO_7<br />
L_DD_7_GPIO65<br />
A6<br />
L_DD_7<br />
F12<br />
{13}<br />
{10,15} SA1111_IRQ_CF_BVD1<br />
GPIO_9<br />
L_DD_8_GPIO66<br />
C5<br />
L_DD_8<br />
F7<br />
{4,13}<br />
{12,15} nVBATT_LOW_IRQ<br />
GPIO_10<br />
L_DD_9_GPIO67<br />
A5<br />
L_DD_9 {4,13}<br />
{13}<br />
A7<br />
GPIO_11<br />
L_DD_10_GPIO68<br />
D5<br />
L_DD_10<br />
{6,15} MBGNT_CF_IRQ<br />
B5<br />
{4,13}<br />
GPIO_13<br />
L_DD_11_GPIO69<br />
A4<br />
L_DD_11<br />
B4<br />
{4,13}<br />
{13,15} MBREQ_CF_DETECT<br />
GPIO_14<br />
L_DD_12_GPIO70<br />
A3<br />
L_DD_12 {4,13}<br />
{10}<br />
D12<br />
GPIO_17<br />
L_DD_13_GPIO71<br />
A2<br />
L_DD_13 {4,13} {15} BOOT_SEL_0<br />
{15} BOOT_SEL_1<br />
BOOT_SEL_2<br />
{10}<br />
A16<br />
GPIO_32<br />
L_DD_14_GPIO72<br />
C3<br />
L_DD_14 {4,13}<br />
L_DD_15_GPIO73<br />
B3<br />
L_DD_15 {4,13}<br />
LCD Port<br />
L_FCLK_GPIO74<br />
E8<br />
L_FCLK {13}<br />
L_LCLK_GPIO75<br />
D8<br />
L_LCLK<br />
B8<br />
{13}<br />
L_PCLK<br />
GPIO Port<br />
L_PCLK_GPIO76<br />
A8<br />
{13}<br />
L_BIAS_GPIO77<br />
L_BIAS {13}<br />
H12<br />
LAYOUT: Keep Close in<br />
DC3P3V<br />
{6,10,11,13} JTAG_TCK<br />
TCK<br />
H15<br />
{13} CPLD2_TDO<br />
TDI<br />
a Matrix <strong>and</strong> in an<br />
H16<br />
JTAG<br />
Y4<br />
DNI<br />
{10,11} SA_TDO<br />
Accessible location.<br />
{6,10,11,13} JTAG_TMS<br />
H13<br />
TMS<br />
1 4<br />
{11} JTAG_nTRST<br />
H11<br />
Y1<br />
Add Silk screen Box.<br />
R271<br />
2 3<br />
2 1<br />
J13 K11<br />
{10,11,15} nRESET_IN<br />
nRESET_OUT<br />
nRESET_OUT {6,11,13,15}<br />
C 681<br />
C<br />
3.6864Mhz<br />
3.6864MHZ<br />
G16<br />
{15}<br />
BOOT_SEL_0<br />
G13<br />
{15}<br />
BOOT_SEL_1<br />
F13<br />
DC3P3V<br />
BOOT_SEL_2<br />
BOOT_SEL_2<br />
nRESET_IN {10,11,15}<br />
{12}<br />
DC_PLL<br />
DC3P3V<br />
C15<br />
0.1UF<br />
C16<br />
0.1UF<br />
DC3P3V<br />
DC_CORE<br />
C123<br />
0.1UF<br />
R277<br />
0<br />
R200<br />
0<br />
R21<br />
100K<br />
R22<br />
100K<br />
Y2<br />
2 1<br />
32.768KHZ<br />
K15<br />
K16<br />
L16<br />
L15<br />
L11<br />
{12,13} SA_PWR_EN<br />
K12<br />
nBATT_FAULT<br />
K13<br />
nVDD_FAULT<br />
3.6Mhz<br />
32Khz<br />
{13} nVDD_FAULT<br />
{8,10,11,12,13,14} VBATT<br />
F11<br />
DC_CORE<br />
VDD_1<br />
VSS_1<br />
C16<br />
G7<br />
VDD_2<br />
VSS_2<br />
H8<br />
G9<br />
H9<br />
U2<br />
VDD_3<br />
VSS_3<br />
H10<br />
VDD_4<br />
VSS_4<br />
J8<br />
J7<br />
VDD_5<br />
VSS_5<br />
J9<br />
MAX6328<br />
K8<br />
VDD_6<br />
VSS_6<br />
T1<br />
1<br />
K10<br />
GND<br />
VDD_7<br />
L6<br />
VDD_8<br />
VSSN_1<br />
C2<br />
L9<br />
E2<br />
VDD_9<br />
3<br />
DC3P3V<br />
VIN<br />
Capacitors for Core<br />
DC3P3V<br />
B B<br />
2<br />
RESET<br />
U3<br />
DC3P3V<br />
MAX6328XR27-T-SC<br />
MAX811TEUS-T<br />
4<br />
VCC<br />
{12} PLL_SENSE<br />
A1<br />
D4<br />
F4<br />
H4<br />
K4<br />
M4<br />
M14<br />
N5<br />
N7<br />
N9<br />
N11<br />
N13<br />
P3<br />
T16<br />
PXTAL<br />
PEXTAL<br />
TXTAL<br />
TEXTAL<br />
VDDN_1<br />
VDDN_2<br />
VDDN_3<br />
VDDN_4<br />
VDDN_5<br />
VDDN_6<br />
VDDN_7<br />
VDDN_8<br />
VDDN_9<br />
VDDN_10<br />
VDDN_11<br />
VDDN_12<br />
VDDN_13<br />
VDDN_14<br />
S1<br />
VSSQ_3<br />
J15<br />
PLL_VCC<br />
VSSQ_4<br />
C14<br />
J16<br />
PLL_SENSE<br />
VSSQ_5<br />
F6<br />
RESET<br />
T2<br />
VCCKP<br />
VSSQ_6<br />
G8<br />
D15<br />
ADC_VCC<br />
VSSQ_7<br />
G10<br />
M11<br />
BATT_VCC<br />
VSSQ_8<br />
H7<br />
J10<br />
A DC3P3V<br />
VSSQ_9<br />
C6<br />
J14<br />
Capacitors for VDDX<br />
A<br />
VDDQ_1<br />
VSSQ_10<br />
C10<br />
VDDQ_2<br />
VSSQ_11<br />
K7<br />
C13<br />
VDDQ_3<br />
VSSQ_12<br />
K9<br />
E14<br />
VDDQ_4<br />
VSSQ_13<br />
L14<br />
G14<br />
VDDQ_5 BALL 12-11-00<br />
<strong>PXA250</strong> Processor Reference Design<br />
R262<br />
0<br />
TESTCLK<br />
TEST<br />
VSSN_2<br />
VSSN_3<br />
VSSN_4<br />
VSSN_5<br />
VSSN_6<br />
VSSN_7<br />
VSSN_8<br />
VSSN_9<br />
VSSN_10<br />
VSSN_11<br />
VSSN_12<br />
VSSN_13<br />
VSSN_14<br />
VSSN_15<br />
G11<br />
G12<br />
G2<br />
J2<br />
L2<br />
N2<br />
R2<br />
R4<br />
R6<br />
R8<br />
R10<br />
R12<br />
R14<br />
M15<br />
P15<br />
VSSQ_1<br />
C4<br />
VSSQ_2<br />
C8<br />
C11<br />
R48<br />
0<br />
R51<br />
0<br />
C125<br />
0.1UF<br />
4<br />
B<br />
1 2<br />
Top<br />
7A<br />
C7<br />
0.1UF<br />
C8<br />
0.1UF<br />
3<br />
3<br />
MR<br />
RESET<br />
GND<br />
2<br />
1<br />
R26<br />
1_Ohm<br />
C6<br />
0.1UF<br />
C9<br />
0.1UF<br />
R27<br />
1_Ohm<br />
C10<br />
0.1UF<br />
C11<br />
0.1UF<br />
C12<br />
0.1UF<br />
C13<br />
0.1UF<br />
C14<br />
0.1UF<br />
R23<br />
10K<br />
R24<br />
10K<br />
R25<br />
10K<br />
R18<br />
100K<br />
R19<br />
100K<br />
R20<br />
100K<br />
<strong>PXA250</strong>_MBGA256<br />
Size Rev<br />
B<br />
2.07<br />
8<br />
7<br />
6<br />
5<br />
4<br />
3<br />
Date:<br />
Tuesday, February 05, 2002<br />
2
8<br />
1<br />
Sheet 4 of 16<br />
1<br />
7<br />
6<br />
5<br />
4<br />
3<br />
2<br />
Copyright 2002 <strong>Intel</strong> Corporation<br />
C17<br />
0.1UF<br />
U4<br />
SDRAM<br />
SYSTEM CONFIGURATION REGISTER<br />
23<br />
{2,5,7} SA_A10 A0<br />
24<br />
{2,5,7} SA_A11 A1<br />
25 4M x 4 x 16<br />
DC3P3V<br />
{2,5,7} SA_A12 A2<br />
26 SDRAM<br />
{2,5,7} SA_A13 A3<br />
29<br />
SDRAM Bank Addressing:<br />
{2,5,7} SA_A14 A4<br />
30<br />
{2,5,7} SA_A15 A5<br />
31<br />
D {2,5,7} SA_A16 A6<br />
SDRAM Address Bus wired for<br />
D<br />
32<br />
{2,5,7} SA_A17 A7<br />
33<br />
SA1110 legacy compatibility mode<br />
DNI<br />
{2,5,7} SA_A18 A8<br />
34<br />
{2,5,7} SA_A19 A9<br />
for SDRAM Bank Addressing.<br />
22<br />
{2,5,7} SA_A20 A10<br />
SD_SZ_0<br />
{2,5,7} SA_A21<br />
35<br />
40<br />
R29<br />
A11<br />
NC<br />
{3,13} L_DD_8<br />
{2,5,7} SA_A24<br />
36<br />
A12<br />
SA_D0 {2,5,6,7}<br />
100K<br />
2<br />
DC3P3V<br />
D0<br />
D1<br />
4<br />
SA_D1<br />
{2,7}<br />
19<br />
5<br />
{2,5,6,7}<br />
SA_nSDCS_0 nCS<br />
D2<br />
SA_D2<br />
{2,5,6,7,10} SA_nWE<br />
16<br />
{2,5,6,7}<br />
D3<br />
7<br />
SA_D3<br />
17<br />
{2,5,6,7}<br />
{2,5,6,7} SA_nSDCAS<br />
nCAS<br />
D4<br />
8<br />
SA_D4<br />
18<br />
{2,5,6,7}<br />
DNI<br />
{2,6,7} SA_nSDRAS nRAS<br />
D5<br />
10<br />
SA_D5 {2,5,6,7}<br />
D6<br />
11<br />
SA_D6<br />
13<br />
{2,5,6,7}<br />
SD_SZ_1<br />
SA_D7 {2,5,6,7} R32<br />
D7<br />
{3,13} L_DD_9<br />
{2,7} SA_SDCLK_1<br />
38<br />
42<br />
D8<br />
SA_D8 {2,5,6,7}<br />
{2,6} SA_SDCKE_1<br />
SA_D9 {2,5,6,7}<br />
DC3P3V<br />
100K<br />
37<br />
D9<br />
44<br />
20<br />
{2,5,7} SA_A23 BS_0<br />
D10<br />
45<br />
SA_D10<br />
21<br />
{2,5,6,7}<br />
{2,5,7} SA_A22 BS_1<br />
D11<br />
47<br />
SA_D11<br />
{2,7} SA_DQM_0<br />
15<br />
{2,5,6,7}<br />
DC3P3V<br />
LDQM D12<br />
48<br />
SA_D12 {2,5,6,7}<br />
{2,7} SA_DQM_1<br />
39<br />
UDMQ D13<br />
50<br />
SA_D13 {2,5,6,7}<br />
D14<br />
51<br />
SA_D14 {2,5,6,7}<br />
DNI<br />
D15<br />
53<br />
SA_D15<br />
1<br />
{2,5,6,7}<br />
VDD_1<br />
FLASH_SZ_0<br />
C 14<br />
28<br />
R35<br />
VDD_2 VSS_1<br />
{3,13} L_DD_10<br />
C<br />
27<br />
VDD_3 VSS_2<br />
41<br />
100K<br />
DC3P3V<br />
VSS_3<br />
54<br />
3<br />
VDD_Q1 VSSQ_1<br />
6<br />
9<br />
VDD_Q2 VSSQ_2<br />
12<br />
43<br />
VDD_Q3 VSSQ_3<br />
46<br />
49<br />
VDD_Q4 VSSQ_4<br />
52<br />
DNI<br />
R38<br />
FLASH_SZ_1<br />
{3,13} L_DD_11<br />
100K<br />
DC3P3V<br />
U5<br />
{2,5,7} SA_A10<br />
23<br />
A0<br />
24<br />
{2,5,7} SA_A11 A1<br />
25 4M x 4 x 16<br />
DNI<br />
{2,5,7} SA_A12 A2<br />
26 SDRAM<br />
{2,5,7} SA_A13 A3<br />
29<br />
R41<br />
FLASH_TYPE<br />
{2,5,7} SA_A14 A4<br />
{3,13} L_DD_12<br />
{2,5,7} SA_A15<br />
30<br />
A5<br />
100K<br />
31<br />
DC3P3V<br />
{2,5,7} SA_A16 A6<br />
32<br />
{2,5,7} SA_A17 A7<br />
B 33<br />
B<br />
{2,5,7} SA_A18 A8<br />
34<br />
{2,5,7} SA_A19 A9<br />
22<br />
{2,5,7} SA_A20 A10<br />
35<br />
40<br />
DNI<br />
{2,5,7} SA_A21 A11<br />
NC<br />
36<br />
{2,5,7} SA_A24 A12<br />
2<br />
SA_D16 {2,5,7}<br />
R44<br />
D0<br />
{3,13} L_DD_13<br />
LCD_TYPE<br />
4<br />
{13}<br />
D1<br />
SA_D17 {2,5,7}<br />
{2,7} SA_nSDCS_0<br />
SA_D18 {2,5,7}<br />
DC3P3V<br />
100K<br />
19<br />
5<br />
nCS<br />
D2<br />
16<br />
{2,5,6,7,10} SA_nWE<br />
D3<br />
7<br />
SA_D19 {2,5,7}<br />
{2,5,6,7}<br />
17<br />
SA_nSDCAS nCAS<br />
D4<br />
8<br />
SA_D20<br />
18<br />
{2,5,7}<br />
{2,6,7} SA_nSDRAS nRAS<br />
D5<br />
10<br />
SA_D21 {2,5,7}<br />
D6<br />
11<br />
SA_D22 {2,5,7}<br />
D7<br />
13<br />
SA_D23 {2,5,7}<br />
{2,7} SA_SDCLK_1<br />
38<br />
42<br />
CLK<br />
D8<br />
SA_D24<br />
37<br />
{2,5,7}<br />
{2,6} SA_SDCKE_1 CKE<br />
D9<br />
44<br />
SA_D25<br />
20<br />
45<br />
{2,5,7}<br />
{2,5,7} SA_A23<br />
SA_D26 {2,5,7}<br />
R47<br />
BS_0<br />
D10<br />
{3,13} L_DD_14<br />
nGFX_PRESENT {13,15}<br />
21<br />
47<br />
{2,5,7} SA_A22 BS_1<br />
D11<br />
SA_D27 {2,5,7}<br />
{2,7} SA_DQM_2<br />
SA_D28 {2,5,7}<br />
100K<br />
15<br />
48<br />
DC3P3V<br />
DC3P3V<br />
LDQM D12<br />
39<br />
50<br />
{2,7} SA_DQM_3 UDMQ D13<br />
SA_D29<br />
51<br />
{2,5,7}<br />
D14<br />
SA_D30<br />
53<br />
{2,5,7}<br />
D15<br />
SA_D31<br />
1<br />
{2,5,7}<br />
VDD_1<br />
14<br />
VDD_2 VSS_1<br />
28<br />
27<br />
41<br />
A VDD_3 VSS_2<br />
54<br />
R50<br />
A<br />
VSS_3<br />
{3,13} L_DD_15<br />
nNEP_PRESENT {13,15}<br />
3<br />
VDD_Q1 VSSQ_1<br />
6<br />
100K<br />
9<br />
VDD_Q2 VSSQ_2<br />
12<br />
43<br />
VDD_Q3 VSSQ_3<br />
46<br />
49<br />
VDD_Q4 VSSQ_4<br />
52<br />
<strong>PXA250</strong> Processor Reference Design<br />
C19<br />
0.1UF<br />
C20<br />
0.1UF<br />
R49<br />
10K<br />
R46<br />
10K<br />
R45<br />
R42<br />
0<br />
R40<br />
10K<br />
R43 R39 R37<br />
R33<br />
0 10K<br />
0 10K<br />
0<br />
10K<br />
C18<br />
0.1UF<br />
R36<br />
0<br />
R34<br />
10K<br />
R31<br />
R30<br />
0<br />
R28<br />
10K<br />
Pg. 4<br />
Size Rev<br />
B<br />
2.07<br />
8<br />
7<br />
6<br />
5<br />
4<br />
3<br />
Date:<br />
Tuesday, February 05, 2002<br />
2
8<br />
1<br />
Sheet 5 of 16<br />
1<br />
7<br />
6<br />
5<br />
4<br />
3<br />
2<br />
Copyright 2002 <strong>Intel</strong> Corporation<br />
U6<br />
Flash Memory<br />
<strong>Intel</strong> StrataFlash<br />
16M x 16<br />
G2<br />
F2<br />
A0<br />
DQ0<br />
SA_D0<br />
A1<br />
E2<br />
{2,4,6,7}<br />
{2,6} SA_A2 A1<br />
DQ1<br />
SA_D1<br />
B1<br />
G3<br />
{2,4,6,7}<br />
{2,6} SA_A3 A2<br />
DQ2<br />
SA_D2<br />
C1<br />
E4<br />
{2,4,6,7}<br />
{2,7} SA_A4 A3<br />
DQ3<br />
SA_D3<br />
D1<br />
E5<br />
{2,4,6,7}<br />
{2,7} SA_A5 A4<br />
DQ4<br />
SA_D4<br />
D2<br />
G5<br />
{2,4,6,7}<br />
{2,7} SA_A6 A5<br />
DQ5<br />
SA_D5<br />
A2<br />
{2,4,6,7}<br />
D {2,7} SA_A7 A6<br />
DQ6<br />
G6<br />
SA_D6 Resistor StrataFlash Synchronous<br />
D<br />
C2<br />
{2,4,6,7}<br />
{2,7} SA_A8 A7<br />
DQ7<br />
H7<br />
SA_D7<br />
A3<br />
{2,4,6,7}<br />
StrataFlash<br />
{2,7} SA_A9 A8<br />
DQ8<br />
E1<br />
SA_D8<br />
B3<br />
{2,4,6,7}<br />
{2,4,7} SA_A10 A9<br />
DQ9<br />
E3<br />
SA_D9<br />
C3<br />
{2,4,6,7}<br />
{2,4,7} SA_A11 A10<br />
DQ10<br />
F3<br />
SA_D10 {2,4,6,7}<br />
R52 DNI IN<br />
{2,4,7} SA_A12<br />
D3<br />
A11<br />
DQ11<br />
F4<br />
SA_D11<br />
C4<br />
{2,4,6,7}<br />
{2,4,7} SA_A13 A12<br />
DQ12<br />
F5<br />
SA_D12 {2,4,6,7}<br />
R53 IN DNI<br />
A5<br />
{2,4,7} SA_A14 A13<br />
DQ13<br />
H5<br />
SA_D13<br />
B5<br />
{2,4,6,7}<br />
{2,4,7} SA_A15 A14<br />
DQ14<br />
G7<br />
SA_D14 {2,4,6,7}<br />
R54 DNI IN<br />
C5<br />
E7<br />
{2,4,7} SA_A16<br />
SA_D15<br />
DC3P3V<br />
A15<br />
DQ15<br />
{2,4,6,7}<br />
{2,4,7} SA_A17<br />
D7<br />
A16<br />
R56 DNI IN<br />
D8<br />
DNI<br />
{2,4,7} SA_A18 A17<br />
E8<br />
STS<br />
A7<br />
DC3P3V<br />
{2,4,7} SA_A19 A18<br />
R212<br />
R57 DNI IN<br />
B7<br />
{2,4,7} SA_A20 A19<br />
B6<br />
DU1 / NC<br />
C7<br />
C6<br />
{2,4,7} SA_A21 A20 DU2 / nWP<br />
0 R52<br />
R212 DNI IN<br />
{2,4,7} SA_A22<br />
C8<br />
D5<br />
A21 DU3 / VDDQ<br />
A8<br />
D6<br />
{2,4,7} SA_A23 A22 DU4 / VDDQ<br />
0<br />
G1<br />
{2,4,7} SA_A24 A23<br />
H8<br />
A24<br />
DC3P3V<br />
H2<br />
DNI<br />
DU8 / VSSQ<br />
D4<br />
{13} FLASH_nRP<br />
nRP<br />
F1<br />
R54<br />
nBYTE<br />
E6<br />
G4<br />
{2,15} SA_SDCLK_0<br />
DU5 / CLK V_DDQ<br />
R55<br />
C 0<br />
F6<br />
DU6 / ADV<br />
A4<br />
V_PEN<br />
C<br />
F7<br />
DU7 / WAIT<br />
0<br />
A6<br />
R56<br />
VDD_1<br />
F8<br />
H3<br />
{2,4,6,7} SA_nSDCAS<br />
{2,7} SA_nOE<br />
nOE VDD_2<br />
0<br />
G8<br />
{2,4,6,7,10} SA_nWE<br />
nWE<br />
B2<br />
VSS_1<br />
{6} nFLASH_BOOT_CS<br />
B4<br />
H4<br />
nCE_0 VSS_2<br />
B8<br />
H6<br />
CS_AWS<br />
nCE_1 VSS_3<br />
H1<br />
nCE_2 BGA<br />
Pg. 5<br />
DNI<br />
R58<br />
10K<br />
C2<br />
0.1UF<br />
U7<br />
<strong>Intel</strong> StrataFlash<br />
16M x 16<br />
G2<br />
F2<br />
A0<br />
DQ0<br />
SA_D16<br />
A1<br />
E2<br />
{2,4,7}<br />
{2,6} SA_A2<br />
A1<br />
DQ1<br />
SA_D17<br />
B1<br />
G3<br />
{2,4,7}<br />
{2,6} SA_A3<br />
A2<br />
DQ2<br />
SA_D18<br />
C1<br />
E4<br />
{2,4,7}<br />
{2,7} SA_A4<br />
A3<br />
DQ3<br />
SA_D19<br />
{2,7} SA_A5<br />
D1<br />
E5<br />
{2,4,7}<br />
A4<br />
DQ4<br />
SA_D20<br />
D2<br />
G5<br />
{2,4,7}<br />
{2,7} SA_A6<br />
A5<br />
DQ5<br />
SA_D21<br />
A2<br />
{2,4,7}<br />
{2,7} SA_A7<br />
A6<br />
DQ6<br />
G6<br />
SA_D22 {2,4,7}<br />
B C2<br />
B<br />
{2,7} SA_A8<br />
A7<br />
DQ7<br />
H7<br />
SA_D23<br />
A3<br />
{2,4,7}<br />
{2,7} SA_A9<br />
A8<br />
DQ8<br />
E1<br />
SA_D24<br />
B3<br />
{2,4,7}<br />
{2,4,7} SA_A10<br />
A9<br />
DQ9<br />
E3<br />
SA_D25<br />
C3<br />
{2,4,7}<br />
{2,4,7} SA_A11<br />
A10<br />
DQ10<br />
F3<br />
SA_D26<br />
D3<br />
{2,4,7}<br />
{2,4,7} SA_A12<br />
A11<br />
DQ11<br />
F4<br />
SA_D27<br />
C4<br />
F5<br />
{2,4,7}<br />
{2,4,7} SA_A13<br />
A12<br />
DQ12<br />
SA_D28<br />
A5<br />
H5<br />
{2,4,7}<br />
{2,4,7} SA_A14<br />
A13<br />
DQ13<br />
SA_D29<br />
B5<br />
G7<br />
{2,4,7}<br />
{2,4,7} SA_A15<br />
A14<br />
DQ14<br />
SA_D30<br />
C5<br />
E7<br />
{2,4,7}<br />
{2,4,7} SA_A16<br />
A15<br />
DQ15<br />
SA_D31<br />
D7<br />
{2,4,7}<br />
{2,4,7} SA_A17<br />
A16<br />
D8<br />
E8<br />
{2,4,7} SA_A18<br />
A17<br />
STS<br />
A7<br />
{2,4,7} SA_A19<br />
A18<br />
B7<br />
B6<br />
{2,4,7} SA_A20<br />
A19 DU1 / NC<br />
C7<br />
C6<br />
{2,4,7} SA_A21<br />
A20 DU2 / nWP<br />
C8<br />
D5<br />
{2,4,7} SA_A22<br />
A21 DU3 / VDDQ<br />
A8<br />
D6<br />
{2,4,7} SA_A23<br />
A22 DU4 / VDDQ<br />
G1<br />
{2,4,7} SA_A24<br />
A23<br />
H8<br />
A24<br />
H2<br />
DU8 / VSSQ<br />
D4<br />
nRP<br />
F1<br />
DC3P3V<br />
nBYTE<br />
E6<br />
DU5 / CLK<br />
G4<br />
V_DDQ<br />
F6<br />
A4<br />
A DU6 / ADV V_PEN<br />
F7<br />
A<br />
DU7 / WAIT<br />
A6<br />
VDD_1<br />
VDD_2<br />
H3<br />
F8<br />
G8<br />
nOE<br />
nWE<br />
B4<br />
nCE_0<br />
B8<br />
nCE_1<br />
H1<br />
nCE_2<br />
VSS_1<br />
VSS_2<br />
VSS_3<br />
BGA<br />
B2<br />
H4<br />
H6<br />
C23<br />
0.1UF<br />
C24<br />
0.1UF<br />
R57<br />
0<br />
C21<br />
0.1UF<br />
C22<br />
0.1UF<br />
C1<br />
0.1UF<br />
R53<br />
0<br />
<strong>PXA250</strong> Processor Reference Design<br />
Size Rev<br />
B<br />
2.07<br />
8<br />
7<br />
6<br />
5<br />
4<br />
3<br />
Date:<br />
Tuesday, February 05, 2002<br />
2
8<br />
1<br />
Sheet 6 of 16<br />
1<br />
7<br />
6<br />
5<br />
4<br />
3<br />
2<br />
Copyright 2002 <strong>Intel</strong> Corporation<br />
U8<br />
Pg. 6<br />
CF_PWR_ON<br />
Buffer<br />
{13}<br />
16_Bit Buffer/Line<br />
R59<br />
Driver<br />
100K<br />
74LVCH162244A<br />
47<br />
2<br />
{2,15} SA_nPIOW<br />
CF_nPIOW {10}<br />
R60<br />
1A1<br />
1Y1<br />
46<br />
{2,15} SA_nPOE 1A2<br />
1Y2<br />
3<br />
CF_nPOE {10}<br />
D CF_nPWE {10} 100K<br />
44<br />
{2,15} SA_nPWE 1A3<br />
1Y3<br />
5<br />
Board Control<br />
D<br />
43<br />
{2,15} SA_nPIOR 1A4<br />
1Y4<br />
6<br />
CF_nPIOR {10}<br />
CF_GFX_RESET<br />
Register<br />
{10,15}<br />
IRDA_FSEL {9}<br />
{2} SA_nSDCS_2<br />
41<br />
2A1<br />
2Y1<br />
8<br />
VX_nSDCS_2 {15}<br />
IRDA_MD0 {9}<br />
{2,15} SA_nPCE_2<br />
40<br />
CF_nPCE_2 {10}<br />
IRDA_MD1 {9} DC3P3V<br />
2A2<br />
2Y2<br />
9<br />
{2,4} SA_SDCKE_1<br />
38<br />
2A3<br />
2Y3<br />
11<br />
VX_SDCKE_1 {15} CF_nBUS_ON<br />
37<br />
{2} SA_SDCLK_2 2A4<br />
2Y4<br />
12<br />
VX_SDCLK_2 {15}<br />
U9<br />
{10} CF_nPWAIT<br />
36<br />
SA_nPWAIT {2,15}<br />
R61<br />
3A1<br />
3Y1<br />
13<br />
{10} CF_nIOIS16<br />
35<br />
3A2<br />
3Y2<br />
14<br />
SA_nIOIS16 {2,15}<br />
100K<br />
{2,15} SA_nPREG<br />
33<br />
3A3<br />
3Y3<br />
16<br />
CF_nPREG {10} 74LVCH16374A<br />
{2,15} SA_nPCE_1<br />
32<br />
17<br />
CF_nPCE_1 {10}<br />
R62<br />
3A4<br />
3Y4<br />
16-Bit Edge Triggered<br />
{2,5} SA_A3<br />
VX_A3 {10,15}<br />
100K<br />
30<br />
4A1<br />
4Y1<br />
19<br />
D-Type Flip Flop<br />
29<br />
{2,5} SA_A2 4A2<br />
4Y2<br />
20<br />
VX_A2 {10,15} 47<br />
{2,4,5,7} SA_D0 1D1<br />
2<br />
1Q1<br />
AUDIO_PWR_ON<br />
{2} SA_A1<br />
27<br />
{8}<br />
4A3<br />
4Y3<br />
22<br />
VX_A1 {10,15} {2,4,5,7} SA_D1<br />
46<br />
1D2<br />
3<br />
1Q2<br />
26<br />
{2} SA_A0 4A4<br />
4Y4<br />
23<br />
VX_A0 {10,15} 44<br />
{2,4,5,7} SA_D2 1D3<br />
5<br />
1Q3<br />
LIGHT_PWR_ON<br />
43<br />
{13}<br />
{2,4,5,7} SA_D3 1D4<br />
1Q4<br />
6<br />
{7} nVX_CF_OE<br />
1<br />
1nOE VSS_1<br />
4<br />
41<br />
{2,4,5,7} SA_D4 1D5<br />
1Q5<br />
8<br />
48<br />
10<br />
40<br />
9<br />
R63<br />
2nOE VSS_2<br />
{2,4,5,7} SA_D5 1D6<br />
1Q6<br />
25<br />
DC3P3V CF_nBUS_ON<br />
3nOE VSS_3<br />
15<br />
38<br />
{2,4,5,7} SA_D6 1D7<br />
1Q7<br />
11<br />
100K<br />
24<br />
4nOE VSS_4<br />
21<br />
37<br />
{2,4,5,7} SA_D7 1D8<br />
1Q8<br />
12<br />
VSS_5<br />
28<br />
7<br />
VDD_1 VSS_6<br />
34<br />
36<br />
13<br />
{2,4,5,7} SA_D8 2D1<br />
2Q1<br />
LCD_PWR_ON {13,14}<br />
C 18<br />
VDD_2 VSS_7<br />
39<br />
35<br />
14<br />
{2,4,5,7} SA_D9 2D2<br />
2Q2<br />
C<br />
31<br />
VDD_3 VSS_8<br />
45<br />
33<br />
16<br />
{2,4,5,7} SA_D10 2D3<br />
2Q3<br />
42<br />
32<br />
17<br />
R64<br />
VDD_4<br />
{2,4,5,7} SA_D11 2D4<br />
2Q4<br />
{2,4,5,7} SA_D12<br />
30<br />
2D5<br />
2Q5<br />
19<br />
100K<br />
{2,4,5,7} SA_D13<br />
29<br />
2D6<br />
2Q6<br />
20<br />
{2,4,5,7} SA_D14<br />
27<br />
2Q7<br />
22<br />
RS232_ON<br />
74LVCH162244APF<br />
2D7<br />
{10}<br />
{2,4,5,7} SA_D15<br />
26<br />
2D8<br />
2Q8<br />
23<br />
nBCR_OE<br />
1<br />
R65<br />
nBCR_WR<br />
1nOE<br />
48<br />
1CLK<br />
100K<br />
4<br />
DC3P3V<br />
VSS_1<br />
24<br />
10<br />
2nOE VSS_2<br />
25<br />
15<br />
2CLK VSS_3<br />
RADIO_PWR_ON<br />
21<br />
{11}<br />
VSS_4<br />
7<br />
VDD_1 VSS_5<br />
28<br />
18<br />
VDD_2 VSS_6<br />
34<br />
R66<br />
31<br />
VDD_3 VSS_7<br />
39<br />
100K<br />
42<br />
VDD_4 VSS_8 45<br />
RADIO_WAKE {11}<br />
U10<br />
74LVCH16374A<br />
DC3P3V<br />
CPLD<br />
nRED_LED<br />
B XCR3032XL-10VQ44C<br />
B<br />
Xilinx CPLD<br />
{2} SA_SDCLK_2<br />
42<br />
35<br />
CF_nBUS_ON<br />
D1<br />
A0_CLK<br />
B0<br />
R67<br />
{15} nNEP_FLASH_CS<br />
43<br />
A1<br />
B1<br />
34<br />
nXCV_ADD_OE {7,13}<br />
2 1<br />
{7}<br />
44<br />
XCV_DATA_DIR A2<br />
B2<br />
33<br />
SA_nCS_5 {2,15}<br />
{10,11} CPLD1_TDI<br />
CPLD1_TDO {11,13}<br />
1.5K<br />
1<br />
RED<br />
DC3P3V<br />
A3_TDI<br />
B3_TDO<br />
32<br />
2<br />
nGREEN_LED<br />
{3,15} MBGNT_CF_IRQ<br />
nBCR_OE<br />
A4<br />
B4<br />
31<br />
SA_nCS_4<br />
3<br />
{2,15}<br />
nBCR_WR<br />
A5<br />
B5<br />
30<br />
SA_nCS_3<br />
5<br />
{2,15}<br />
SA_nCS_2 {2}<br />
D2<br />
A6<br />
B6<br />
28<br />
{7} nVX_CF_OE<br />
SA_nCS_1 {2}<br />
R68<br />
6<br />
A7<br />
B7<br />
27<br />
2 1<br />
7<br />
{3,10,11,13} JTAG_TMS<br />
A8_TMS<br />
B8_TCK<br />
26<br />
JTAG_TCK {3,10,11,13}<br />
GRN<br />
{10,15} nNEP_REG_CS<br />
SA_nCS_0 {2,15} 1.5K<br />
8<br />
A9<br />
B9<br />
25<br />
10<br />
{2,4,5,7,10} SA_nWE<br />
A10<br />
B10<br />
23<br />
SA_A25 {2,7}<br />
{7} nXCV_DATA_OE<br />
11<br />
A11<br />
B11<br />
22<br />
VX_nOE {7,15}<br />
SPKR_OFF<br />
12<br />
{8} DC3P3V<br />
{7} XCV_ADD_DIR A12<br />
B12<br />
21<br />
13<br />
{10,15} CF_IRQ_LVL2OE<br />
A13<br />
B13<br />
20<br />
SA_nPCE_2<br />
14<br />
19<br />
{2,15}<br />
{3,11,13,15} nRESET_OUT<br />
SA_nPCE_1 {2,15} DC3P3V<br />
A14<br />
B14<br />
R69<br />
{5} nFLASH_BOOT_CS<br />
15<br />
A15<br />
B15<br />
18<br />
SA_RD_nWR {2,15}<br />
100K<br />
VDD_1<br />
9<br />
VDD_2<br />
17<br />
VDD_3<br />
29<br />
{15} SWAP_FLASH<br />
37<br />
IN0<br />
41<br />
VDD_4<br />
R70<br />
39<br />
A {2,4,7} SA_nSDRAS IN1<br />
MMC_PWR_ON {13}<br />
38<br />
4<br />
A<br />
{2} SA_nSDCS_2 IN2<br />
VSS_1<br />
0<br />
40<br />
16<br />
{2,4,5,7} SA_nSDCAS<br />
IN3<br />
VSS_2<br />
VSS_3<br />
24<br />
VSS_4<br />
36<br />
C29<br />
0.1UF<br />
C30<br />
0.1UF<br />
C31<br />
0.1UF<br />
C32<br />
0.1UF<br />
C27<br />
0.1UF<br />
C28<br />
0.1UF<br />
C25<br />
0.1UF<br />
C26<br />
0.1UF<br />
<strong>PXA250</strong> Processor Reference Design<br />
XCR3032XL<br />
Size Rev<br />
B<br />
2.07<br />
8<br />
7<br />
6<br />
5<br />
4<br />
3<br />
Date:<br />
Tuesday, February 05, 2002<br />
2
8<br />
1<br />
Pg. 7<br />
Sheet 7 of 16<br />
1<br />
7<br />
6<br />
5<br />
4<br />
3<br />
2<br />
Copyright 2002 <strong>Intel</strong> Corporation<br />
DC3P3V<br />
Transceivers<br />
NOTE:<br />
DIR H = A -> B<br />
DIR L = A
8<br />
1<br />
Sheet 8 of 16<br />
1<br />
7<br />
6<br />
5<br />
4<br />
3<br />
2<br />
Copyright 2002 <strong>Intel</strong> Corporation<br />
XTAL_IN<br />
Audio CODEC<br />
XTAL_OUT<br />
U15<br />
24.576MHZ<br />
+<br />
UCB1400<br />
XTAL_IN<br />
2<br />
Modem / Audio<br />
XTL_IN<br />
ADCSYNC<br />
12<br />
R72<br />
DNI<br />
0<br />
XTAL_OUT 3<br />
34<br />
XTL_OUT VREFDRV<br />
D D<br />
VREF<br />
C46<br />
L_OUT_A {9}<br />
100UF<br />
C50<br />
R_OUT<br />
{9}<br />
100UF<br />
R89<br />
6<br />
AMP5V<br />
1<br />
2<br />
R92<br />
AUDIO3P3V {9}<br />
1<br />
DNI<br />
AUDIO3P3V {9}<br />
+<br />
27<br />
{13,15} SYSCLK<br />
8<br />
29<br />
DNI<br />
{2} SA_SDATA_IN<br />
SDATA_IN<br />
IRQOUT<br />
AC97_IRQ {3}<br />
R73<br />
R74<br />
6<br />
37<br />
{2} SA_BITCLK<br />
BIT_CLK<br />
GPIO_0<br />
AC97_GPIO_0 {11}<br />
Audio Amp<br />
47.5<br />
R75 0<br />
5<br />
39<br />
{2} SA_SDATA_OUT<br />
SDATA_OUT GPIO_1<br />
AC97_GPIO_1 {11}<br />
R76<br />
0 R77<br />
{2} SA_SYNC<br />
10<br />
40<br />
SYNC<br />
GPIO_2<br />
AC97_GPIO_2 {11}<br />
20K<br />
R78 0<br />
R79<br />
11<br />
41<br />
{2} SA_nAC97_RESET RESET<br />
GPIO_3<br />
AC97_GPIO_3 {11}<br />
0 R80<br />
LINE_OUT_L {11}<br />
43<br />
20K<br />
C141<br />
GPIO_4<br />
AC97_GPIO_4 {11}<br />
{9} MICIN<br />
21<br />
MICP<br />
R82<br />
0<br />
R14 2 1<br />
44<br />
U16<br />
{10} CF_AUD<br />
R83<br />
GPIO_5<br />
LINE_OUT_R {11}<br />
10K<br />
22<br />
4.7UF<br />
{9,11} MICGND MICGND<br />
100K<br />
45<br />
R84<br />
{11} RADIO_SPKRP<br />
0<br />
GPIO_6<br />
LM4881<br />
J1<br />
C45<br />
100K<br />
Dual Audio Pwr<br />
2 1<br />
23<br />
46<br />
R86<br />
R81<br />
{9}<br />
LINE_IN_L<br />
GPIO_7<br />
Amp w/shutdwn<br />
C131<br />
100K<br />
2 1<br />
24<br />
47<br />
R87<br />
0.1UF<br />
20K<br />
8 7<br />
LINE_IN_R<br />
GPIO_8<br />
C47<br />
IN_A OUT_A<br />
4.7UF<br />
J2<br />
48<br />
R124 100K<br />
R85<br />
4<br />
GPIO_9<br />
IN_B OUT_B<br />
5<br />
C C<br />
R88<br />
100K<br />
20K<br />
20<br />
0.1UF<br />
1<br />
{14} TSPY<br />
TSPY<br />
BYPASS VDD<br />
R90 0<br />
18<br />
35<br />
{14} TSMX<br />
LINE_OUT_L<br />
3<br />
TSMX<br />
{6} SPKR_OFF SHDN GND<br />
R91 0<br />
19<br />
36<br />
{14} TSMY<br />
TSMY LINE_OUT_R<br />
DC_CORE<br />
R93 0<br />
+<br />
17<br />
LM4881MM<br />
{14} TSPX<br />
TSPX<br />
0<br />
R94<br />
AD_3<br />
13<br />
VBATT<br />
{3,10,11,12,13,14}<br />
0<br />
{3,10,11,12,13,14}<br />
14<br />
AD_2<br />
R96<br />
0<br />
15<br />
AD_1<br />
XFILT {9}<br />
DC5P5V<br />
U17<br />
{9} AUDIO3P3V<br />
16<br />
AD_0<br />
YFILT<br />
1<br />
{9}<br />
MIC5207-3.3BM5<br />
DVDD1<br />
9<br />
4<br />
3.3V LDO REG<br />
DVDD2<br />
DVSS1<br />
DVSS2<br />
7<br />
1 180ma<br />
5<br />
VIN<br />
VOUT<br />
25<br />
AVDD1<br />
32 26<br />
2<br />
AVDD2 GND<br />
38<br />
AVDD3<br />
AVSS2<br />
33<br />
AVSS3<br />
42<br />
3 4<br />
EN BYP<br />
B B<br />
LE33<br />
R99 28<br />
VADCP<br />
10<br />
C58<br />
0.1UF<br />
C55<br />
0.01UF<br />
C42<br />
0.1UF<br />
Pg. 8<br />
R101<br />
1<br />
R104<br />
2<br />
C71<br />
+<br />
4.7UF<br />
C72<br />
1<br />
2<br />
C68<br />
+<br />
4.7UF<br />
C67<br />
1<br />
C57<br />
0.1UF<br />
+<br />
+<br />
+<br />
MIC5207-4.0BM5<br />
4.0V LDO REG<br />
VIN 180ma VOUT<br />
GND<br />
{6} AUDIO_PWR_ON<br />
3 4<br />
EN BYP<br />
LE40<br />
A A<br />
1<br />
1<br />
2<br />
U18<br />
5<br />
C73<br />
270PF<br />
C62<br />
0.1UF<br />
C59<br />
0.01UF<br />
R100<br />
1<br />
C66<br />
0.1UF<br />
C53<br />
0.01UF<br />
C56<br />
0.01UF<br />
30<br />
TEST<br />
VADCN<br />
31<br />
+<br />
AMP5V<br />
C75<br />
+<br />
4.7UF<br />
1<br />
2<br />
C74<br />
0.1UF<br />
0.1UF<br />
R102<br />
0<br />
R103<br />
0<br />
2<br />
C69<br />
4.7UF<br />
C70<br />
0.1UF<br />
1<br />
0.1UF<br />
R282<br />
0<br />
C63<br />
270PF<br />
2<br />
C64<br />
0.01UF<br />
C61<br />
4.7UF<br />
1<br />
C54<br />
0.01UF<br />
C52<br />
0.1UF<br />
C51<br />
1UF<br />
1 2<br />
2<br />
R71<br />
+<br />
47.5<br />
33PF<br />
C43<br />
Y3<br />
2<br />
1<br />
22pF<br />
C44<br />
1<br />
10UF<br />
C41<br />
<strong>PXA250</strong> Processor Reference Design<br />
Size Rev<br />
B<br />
2.07<br />
8<br />
7<br />
6<br />
5<br />
4<br />
3<br />
Date:<br />
Tuesday, February 05, 2002<br />
2
8<br />
<strong>PXA250</strong> Processor Reference Design<br />
1<br />
2<br />
3<br />
4<br />
5<br />
1<br />
1<br />
J7<br />
12-54819-78<br />
USB_WAKE {3,15}<br />
Sheet 9 of 16<br />
1<br />
7<br />
6<br />
5<br />
4<br />
3<br />
2<br />
Copyright 2002 <strong>Intel</strong> Corporation<br />
R105<br />
{8} AUDIO3P3V<br />
10<br />
MIC_PWR<br />
Headset Jack<br />
Stereo Headphone Jack<br />
IrDA Transceiver<br />
1 0.1UF<br />
VCC<br />
J4<br />
AGND<br />
2<br />
1 3<br />
D R_OUT {8} 3<br />
FIR_SEL<br />
IRDA_FSEL {6}<br />
D<br />
MD_0<br />
4<br />
IRDA_MD0<br />
11<br />
{6}<br />
GND MD_1<br />
5<br />
IRDA_MD1<br />
Microphone<br />
{6}<br />
L_OUT_B<br />
NC<br />
6<br />
2<br />
GND<br />
7<br />
RXD<br />
8<br />
IR_RXD<br />
1<br />
{2}<br />
GND<br />
TXD<br />
9<br />
IR_TXD<br />
Speaker<br />
{2} DC3P3V<br />
LEDA<br />
10<br />
4<br />
SHA<br />
5 L_OUT_B<br />
STEREO<br />
HDSL-3600 # 007<br />
SHB<br />
R107<br />
J5<br />
JACK<br />
2<br />
TIP<br />
10<br />
3<br />
RING<br />
L_OUT_A {8} 3.5mm<br />
4<br />
R108<br />
MICGND {8,11} HEADSET<br />
J6<br />
10<br />
JACK<br />
R109<br />
2.5mm<br />
10<br />
MICIN {8}<br />
C79<br />
R111<br />
1 2<br />
USB_5V<br />
10<br />
C R112<br />
C<br />
4.7UF<br />
{2} SA_UDCN<br />
R149<br />
0<br />
Mini USB Jack<br />
RADIO_MICP {11}<br />
0<br />
DC3P3V<br />
+<br />
J3<br />
2<br />
1<br />
U19<br />
DC3P3V<br />
C76<br />
Pg. 9<br />
DNI<br />
{2}<br />
R115<br />
SA_UDCP<br />
0<br />
{8}<br />
AUDIO3P3V<br />
Dual Axis Acelerometer<br />
DNI<br />
B B<br />
U20<br />
DC3P3V DC3P3V<br />
R123<br />
100K<br />
XFILT {8}<br />
USB_5V<br />
3<br />
U21<br />
MAX6348<br />
RESET<br />
VIN<br />
2<br />
R120<br />
YFILT {8}<br />
100K<br />
A + +<br />
MAX6348XR40-T<br />
A<br />
1uF<br />
C3<br />
1uF<br />
C4<br />
R117<br />
1 2<br />
237K<br />
C81<br />
0.01UF<br />
C82<br />
0.01UF<br />
C80<br />
0.1UF<br />
R113<br />
475K<br />
C78<br />
0.1UF<br />
ADXL202E<br />
Dual Axis<br />
Accelerometer<br />
8<br />
VDD XCAP 7<br />
1<br />
ST<br />
YCAP<br />
6<br />
2<br />
T2 XOUT 5<br />
3<br />
COM<br />
YOUT<br />
LCC8<br />
4<br />
R121<br />
1K<br />
C84<br />
0.1UF<br />
R118<br />
10K<br />
R119<br />
100K<br />
R116<br />
475K<br />
R110<br />
0<br />
2<br />
1<br />
C77<br />
0.1UF<br />
R106<br />
1.5K<br />
R114<br />
1.5K<br />
GND<br />
1<br />
Size Rev<br />
B<br />
2.07<br />
8<br />
7<br />
6<br />
5<br />
4<br />
3<br />
Date:<br />
Tuesday, February 05, 2002<br />
2
8<br />
1<br />
Sheet 10 of 16<br />
1<br />
7<br />
6<br />
5<br />
4<br />
3<br />
2<br />
Copyright 2002 <strong>Intel</strong> Corporation<br />
J8<br />
DC5P5V<br />
Momentary Switches<br />
CF_TYPE_II<br />
MIC5219BM5<br />
Compact Flash Type II Socket<br />
50 GND2<br />
ADJ LDO REG<br />
25 nCD2<br />
1<br />
DC3P3V<br />
S2<br />
{13} CF_nCD2<br />
D10<br />
VIN 500ma VOUT<br />
5<br />
49<br />
{7,15} VX_D10<br />
24 nIOIS16<br />
2<br />
1 S 2<br />
{6} CF_nIOIS16<br />
GPIO_0<br />
D09<br />
GND<br />
48<br />
4 3<br />
{3,15}<br />
{7,15} VX_D9<br />
23 D02<br />
3 4<br />
D {7,15} VX_D2<br />
D<br />
D08<br />
{13} CF_PWR EN<br />
47<br />
ADJ<br />
{7,15} VX_D8<br />
22 D01<br />
LGAA<br />
R129 {7,15} VX_D1<br />
46 BVD1<br />
DC3P3V<br />
S3<br />
{3,15} SA1111_IRQ_CF_BVD1<br />
21 D00<br />
U24<br />
R130<br />
10K {7,15} VX_D0<br />
{3,15} GFX_IRQ_CF_BVD2<br />
45 BVD2<br />
1 S 2<br />
GPIO_32<br />
20 A00<br />
MIC5219-3.3BM5<br />
{3}<br />
10K<br />
4 3<br />
{6,15} VX_A0<br />
44 nREG<br />
3.3V LDO REG<br />
{6} CF_nPREG<br />
19 A01<br />
1<br />
CF_VDD<br />
{6,15} VX_A1<br />
{3,8,11,12,13,14} VBATT<br />
500ma<br />
5<br />
nINPACK<br />
VIN VOUT<br />
43<br />
CF_I2C_SDA<br />
A02<br />
DC3P3V<br />
S4<br />
{6,15} VX_A2<br />
18<br />
2<br />
nWAIT<br />
GND<br />
42<br />
+<br />
{6} CF_nPWAIT<br />
17 A03<br />
3 4<br />
{6,15} VX_A3<br />
GPIO_17<br />
RESET<br />
EN<br />
41<br />
BYP<br />
1 S 2<br />
R132<br />
4 3<br />
{3}<br />
{6,15} CF_GFX_RESET<br />
16 A04<br />
LG33<br />
1K {7,15} VX_A4<br />
CF_I2C_SCL<br />
40 nVS2<br />
15 A05<br />
{7,15} VX_A5<br />
39 nCSE<br />
DC3P3V<br />
S5<br />
{6,15} nNEP_REG_CS<br />
14 A06<br />
{7,15} VX_A6<br />
VCC2<br />
R15<br />
38<br />
1 S 2<br />
CF_VDD<br />
GPIO_22<br />
13 VCC1<br />
J9<br />
4 3 0<br />
Base Station Connector<br />
{2,11}<br />
37 IREQ<br />
{6,15} CF_IRQ_LVL2OE<br />
12 A07<br />
{7,15} VX_A7<br />
36 nWE<br />
{6} CF_nPWE<br />
C 11 A08<br />
DC3P3V<br />
{7,15} VX_A8<br />
C<br />
35 nIOWR<br />
{6} CF_nPIOW<br />
10 A09<br />
DC3P3V<br />
{7,15} VX_A9<br />
34 nIORD<br />
20<br />
Three Position Switch<br />
{6} CF_nPIOR<br />
9 nOE<br />
19<br />
{6} CF_nPOE<br />
33 nVS1<br />
18<br />
{8} CF_AUD<br />
8 A10<br />
17<br />
R135<br />
{7,15} VX_A10<br />
32 nCE2<br />
R138<br />
{13} CF_nCD1<br />
{6} CF_nPCE_2<br />
nCE1<br />
{2,14} GPIO_21<br />
{6} CF_nPCE_1<br />
7<br />
100K<br />
31 D15<br />
RS_RI<br />
100K<br />
16 15<br />
{7,15} VX_D15<br />
6 D07<br />
R136<br />
{7,15} VX_D7<br />
R140<br />
D14<br />
RS_DCD<br />
{13} CF_nCD2<br />
{7,15} VX_D14<br />
30<br />
14 13<br />
SA_nWE<br />
5 D06<br />
{2,4,5,6,7}<br />
100K<br />
{7,15} VX_D6<br />
1.5K<br />
29 D13<br />
12 11<br />
DC3P3V<br />
{7,15} VX_D13<br />
D05<br />
{3,6,11,13} JTAG_TCK<br />
4<br />
R139<br />
{7,15} VX_D5<br />
28 D12<br />
RS_TX 10<br />
9<br />
RS_RX<br />
{6} CF_nIOIS16<br />
{7,15} VX_D12<br />
D04<br />
{7,15} VX_D4<br />
3<br />
S6<br />
100K<br />
27 D11<br />
RS_RTS 8 7<br />
{7,15} VX_D11<br />
2 D03<br />
CCW<br />
R141<br />
{7,15} VX_D3<br />
26 nCD1<br />
RS_CTS<br />
R142<br />
6 5<br />
{6} CF_nPWAIT<br />
{13} CF_nCD1<br />
nRESET_IN<br />
1 GND1<br />
0<br />
{3,11,15}<br />
100K<br />
RS_DTR 4 3<br />
DNI<br />
PUSH<br />
RS_DSR 2<br />
1<br />
B B<br />
JTAG_TMS {3,6,11,13}<br />
CW<br />
22<br />
CPLD1_TDI {6,11}<br />
U25<br />
R144<br />
C86<br />
21<br />
{12,15} IN_PWR<br />
SA_TDO<br />
C87<br />
{3,11}<br />
75<br />
MAX3244ECAI<br />
0.1UF<br />
0.1UF<br />
RS-232 XCVR<br />
28<br />
27 C88<br />
C1+<br />
V+<br />
24<br />
3<br />
C89<br />
C1-<br />
V-<br />
DC3P3V<br />
{2,14} GPIO_20<br />
1<br />
0.1UF<br />
C2+<br />
2<br />
0.1UF<br />
C2-<br />
{2,14} GPIO_19<br />
14<br />
RS_TX<br />
{2,15} SA_FF_TXD T1 IN T1OUT<br />
9<br />
13<br />
RS_RTS<br />
U26<br />
DC3P3V<br />
{2} SA_FF_RTS T2 IN T2OUT<br />
10<br />
RS_DTR<br />
{2} SA_FF_DTR<br />
12<br />
T3 IN T3OUT<br />
11<br />
19<br />
RS_RX<br />
MAX4542<br />
{2,15} SA_FF_RXD R1OUT R1 IN<br />
4<br />
18<br />
RS_DCD<br />
2<br />
{2} SA_FF_DCD R2OUT R2 IN<br />
5<br />
RS_DSR<br />
V+<br />
17<br />
{2} SA_FF_DSR R3OUT R3 IN<br />
6<br />
RS_RI<br />
{2} SA_FF_RI<br />
16<br />
R4OUT R4 IN<br />
7<br />
RS_CTS<br />
{2,12,15} SA_I2C_SCL<br />
8<br />
COM_1<br />
15<br />
8<br />
A {2} SA_FF_CTS R5OUT R5 IN<br />
7<br />
1<br />
A<br />
IN_1<br />
NC_1<br />
CF_I2C_SCL<br />
20<br />
R2OUTB INVLD<br />
21<br />
RS232_VALID {3}<br />
{6} RS232_ON<br />
22<br />
FORCEOFF VCC<br />
26<br />
{2,12,15} SA_I2C_SDA<br />
4<br />
COM_2 NC_2<br />
5<br />
CF_I2C_SDA<br />
23<br />
GND<br />
25<br />
FORCEON<br />
3<br />
<strong>PXA250</strong> Processor Reference Design<br />
{3} SA_I2C_ENAB<br />
IN_2<br />
6<br />
GND<br />
Size Rev<br />
AAAF<br />
B<br />
2.07<br />
C90<br />
0.1UF<br />
R145<br />
100K<br />
R146<br />
100K<br />
R153<br />
0<br />
R17<br />
0<br />
1<br />
2<br />
3<br />
R122<br />
0<br />
U23<br />
4<br />
5<br />
6<br />
R16<br />
0<br />
R134<br />
100K<br />
2<br />
R133<br />
100K<br />
4.7UF<br />
C85<br />
1<br />
R131<br />
100K<br />
R128<br />
1.5K<br />
R127<br />
100K<br />
R126<br />
953<br />
Pg. 10<br />
8<br />
7<br />
6<br />
5<br />
4<br />
3<br />
Date:<br />
Tuesday, February 05, 2002<br />
2
8<br />
1<br />
Pg. 11<br />
Sheet 11 of 16<br />
1<br />
7<br />
6<br />
5<br />
4<br />
3<br />
2<br />
Copyright 2002 <strong>Intel</strong> Corporation<br />
SD Socket<br />
DC3P3V<br />
J10<br />
R147 10K<br />
D D<br />
Bottom Mount<br />
MMC_CS0 {2} RADIO_DSR {2}<br />
DC3P3V<br />
DAT2<br />
9<br />
SA_MMCMD {2}<br />
LAYOUT NOTE: Place close to<br />
Battery Header <strong>and</strong> Codec UCB<br />
CD_DAT3<br />
1<br />
1400<br />
2<br />
CMD<br />
3<br />
Radio<br />
VSS1<br />
C132<br />
4<br />
MMC_PWR<br />
Baseb<strong>and</strong><br />
VDD<br />
{8} LINE_OUT_L<br />
5<br />
DNI IF MMC<br />
Connector<br />
SA_MMCCLK {2}<br />
0.1UF J20<br />
CLK<br />
C140<br />
VSS2<br />
6<br />
R225<br />
{8} LINE_OUT_R<br />
1<br />
2<br />
0<br />
DAT0<br />
7<br />
SA_MMDAT {2}<br />
DC3P3V<br />
0.1UF<br />
3<br />
4<br />
R226 DNI 0<br />
MMC<br />
MMC_WP {2} 19<br />
20<br />
R227 DNI 100K<br />
{9} RADIO_MICP<br />
DAT1<br />
8<br />
DC3P3V<br />
DNI<br />
5<br />
{2} RADIO_DTR<br />
{2}<br />
6<br />
SA_BT_CTS<br />
R150<br />
IF<br />
{2} SA_BT_RTS<br />
7<br />
8<br />
SD<br />
DNI<br />
SA_BT_RXD<br />
{2,15}<br />
IF<br />
{2,15} SA_BT_TXD<br />
9<br />
10<br />
RADIO_RI {2}<br />
C C<br />
SD<br />
47.5K<br />
{6} RADIO_PWR_ON<br />
11<br />
12<br />
RADIO_RXD_C {2}<br />
nMMC_DETECT {2,13}<br />
DC3P3V<br />
13<br />
{6} RADIO_WAKE<br />
14<br />
nRESET_IN {3,10,15} CARD Selection Resistors<br />
15<br />
16<br />
RADIO_SPKRN<br />
<strong>and</strong> Values<br />
DNI<br />
{2} RADIO_DCD<br />
RES SD MMC<br />
IF<br />
{8,9} 17<br />
MICGND<br />
18<br />
RADIO_SPKRP<br />
{8}<br />
R225 0 DNI<br />
21 22<br />
{3,6,13,15} nRESET_OUT<br />
R228 100K DNI<br />
DC5P5V<br />
23 24<br />
{3,8,10,12,13,14} VBATT<br />
AC97_GPIO_0 {8}<br />
DC5P5V<br />
{3,8,10,12,13,14} VBATT<br />
25 26<br />
AC97_GPIO_1 {8}<br />
U27<br />
R198<br />
27 28<br />
AC97_GPIO_2 {8}<br />
MIC5207-3.3BM5<br />
0<br />
3.3V LDO REG<br />
29 30<br />
MMC_PWR<br />
{8} AC97_GPIO_4<br />
AC97_GPIO_3 {8}<br />
1<br />
VIN 180ma VOUT<br />
5<br />
2<br />
GND<br />
+<br />
B B<br />
{13} 3 MMC_ON EN BYP<br />
4<br />
LE33<br />
R226<br />
0<br />
DC3P3V<br />
DC3P3V<br />
JTAG ICE Connector<br />
DNI<br />
R236<br />
DVAL_1<br />
{15}<br />
DREQ_1 {15}<br />
DREQ_0 {15}<br />
J19<br />
{2,10} GPIO_22<br />
R221<br />
1<br />
2<br />
{3,6,10,13} 0 R219<br />
JTAG_TMS 0<br />
{15}<br />
R233 0<br />
{3} JTAG_nTRST<br />
3<br />
4<br />
{2,10} GPIO_21<br />
{6,10} 5<br />
6<br />
CPLD1_TDI<br />
{6,10} 0 R218<br />
CPLD1_TDI DVAL_0 {15}<br />
DNI<br />
{3,6,10,13} JTAG_TMS<br />
7<br />
8<br />
{2,10} R234 0<br />
GPIO_19<br />
0<br />
R232<br />
{3,6,10,13} 9<br />
10<br />
JTAG_TCK<br />
{3,6,10,13} JTAG_TCK 11<br />
12<br />
{2,10} R235 0<br />
GPIO_20<br />
{3,10} R223<br />
SA_TDO<br />
13<br />
14<br />
{3,10} 0 R231<br />
SA_TDO<br />
0<br />
A A<br />
75 R224<br />
{3,10,15} nRESET_IN<br />
15<br />
16<br />
0<br />
17<br />
18<br />
R222<br />
100K<br />
R270<br />
10K<br />
2<br />
4.7UF<br />
C92<br />
1<br />
R229<br />
100K<br />
R228<br />
100K<br />
10<br />
11<br />
12<br />
R227<br />
100K<br />
WP<br />
COMM<br />
CD<br />
CHECK !!<br />
C91<br />
0.1UF<br />
19<br />
20<br />
<strong>PXA250</strong> Processor Reference Design<br />
Size Rev<br />
B<br />
2.07<br />
8<br />
7<br />
6<br />
5<br />
4<br />
3<br />
Date:<br />
Tuesday, February 05, 2002<br />
2
8<br />
IN_PWR {10,15}<br />
D10<br />
1<br />
Pg. 12<br />
7<br />
6<br />
5<br />
4<br />
3<br />
2<br />
Copyright 2002 <strong>Intel</strong> Corporation<br />
5.5 Volt Supply<br />
D3<br />
DC5P5V<br />
Processor Core Voltage Supply<br />
U28<br />
L1<br />
11-TM104-NP<br />
4.7uH<br />
LTC1878<br />
Battery Connector<br />
VBATT<br />
+<br />
8<br />
{3,8,10,11,13,14}<br />
LPF<br />
1<br />
D <strong>and</strong> Jumper Post {3,13} SA_PWR_EN<br />
RUN<br />
+<br />
D<br />
U29<br />
7<br />
{3,8,10,11,13,14} VBATT<br />
J18<br />
SYNC-MODE<br />
2<br />
DC_CORE<br />
DC3P3V<br />
Ith<br />
1<br />
+<br />
LT1308A<br />
{3,8,10,11,13,14} VBATT<br />
6<br />
BATTERY<br />
VIN<br />
6<br />
VIN SW<br />
5<br />
2<br />
3<br />
FB<br />
L2<br />
4<br />
2<br />
J17<br />
4<br />
5 1 2<br />
GND FB<br />
GND SW<br />
LTNX<br />
R159<br />
1<br />
10uH<br />
3<br />
BATT_IN_POS<br />
{3,13} SA_PWR_EN<br />
nVBATT_LOW_IRQ {3,15}<br />
2<br />
+<br />
SHDN<br />
8<br />
LBO<br />
0<br />
3<br />
BATT_IN_NEG<br />
LTC1878EMS8<br />
R158<br />
4<br />
SA_I2C_SDA<br />
1<br />
7<br />
5<br />
{2,10,15}<br />
VC LBI<br />
6<br />
47.5K<br />
7<br />
SA_SMB_MODE<br />
1308A<br />
8<br />
nBATT_PRESENT<br />
R162 R163<br />
9<br />
BATT_TEMP<br />
{3,8,10,11,13} VBATT<br />
10<br />
976K 61.9K<br />
DC3P3V<br />
U30<br />
53261-1090<br />
LTC1663<br />
C 4<br />
VCC<br />
C<br />
VOUT<br />
3<br />
1<br />
{2,10,15} SA_I2C_SDA<br />
SDA<br />
GND<br />
2<br />
5<br />
{2,10,15} SA_I2C_SCL<br />
SCL<br />
C100<br />
0.1UF<br />
SA_I2C_SCL {2,10,15} DC_PLL {3}<br />
Battery Charger<br />
3.3 Volt Supply<br />
DC3P3V<br />
DC5P5V<br />
U31<br />
B B<br />
MIC5207-BM5<br />
+<br />
ADJ LDO REG<br />
1 180ma<br />
5<br />
D7<br />
U43<br />
VIN VOUT<br />
GRN D8<br />
2<br />
RED<br />
GND<br />
PLL Voltage Supply<br />
3<br />
DC_CORE<br />
nCHRG SENSE<br />
9<br />
3 4<br />
EN BYP<br />
R211<br />
10<br />
Q1<br />
LEAA<br />
DC3P3V<br />
{2,3} nCHRGR_PRESENT nACPR<br />
0<br />
7 4<br />
U42<br />
DRV<br />
4<br />
TIMER<br />
DC3P3V<br />
MIC5207-BM5<br />
6<br />
1<br />
BATTERY<br />
ADJ LDO REG<br />
PROG BAT<br />
1 180ma<br />
5<br />
U32<br />
VIN VOUT<br />
2<br />
GND<br />
DNI<br />
LTC1732<br />
{3,8,10,11,13,14} VBATT<br />
ADP3335<br />
3 4<br />
{3,13} SA_PWR_EN<br />
BYP<br />
+<br />
7<br />
5<br />
LEAA<br />
IN_1<br />
NR<br />
+<br />
8<br />
A IN_2<br />
OUT_1<br />
1<br />
PLL_SENSE {3}<br />
A<br />
6<br />
SHUTDOWN<br />
22UF<br />
C103<br />
2<br />
OUT_2<br />
C104<br />
0.1UF<br />
R169<br />
200K<br />
5<br />
2<br />
C137<br />
2 1<br />
0.33F<br />
0.1UF<br />
R276<br />
20K<br />
GND<br />
SEL<br />
R168<br />
160K<br />
2 1<br />
2 1<br />
Vcc<br />
8<br />
R165<br />
887K<br />
R164<br />
487K<br />
R161<br />
100K<br />
2<br />
C99<br />
22pF<br />
R160<br />
196K<br />
1<br />
220pF<br />
C98<br />
R155<br />
100K<br />
22UF<br />
C97<br />
2<br />
C94<br />
0.1UF<br />
C95<br />
100UF<br />
1<br />
DNI<br />
R170<br />
8<br />
100K<br />
C139<br />
470PF<br />
R203<br />
4.99K<br />
33uF<br />
C138<br />
R95<br />
0<br />
R201<br />
357K<br />
C142<br />
R206<br />
5<br />
6<br />
7<br />
8<br />
0<br />
3<br />
2<br />
1<br />
R209<br />
C144<br />
1uF<br />
1K<br />
C102<br />
100PF<br />
D4<br />
2 1<br />
RED<br />
C101<br />
R166<br />
100UF<br />
1K<br />
R157<br />
150K<br />
R156<br />
100K<br />
LTEP<br />
LTC1663CS5<br />
R274<br />
1<br />
C143<br />
4.7uF<br />
R167<br />
100K<br />
R210<br />
1K<br />
R275<br />
0.1<br />
12<br />
22UF<br />
C96<br />
R220<br />
100K<br />
R154<br />
357K<br />
4<br />
GND<br />
OUT_3<br />
3<br />
LFE<br />
ADP3335ARM-3.3<br />
7<br />
6<br />
DNI<br />
5<br />
4<br />
3<br />
<strong>PXA250</strong> Processor Reference Design<br />
Size Rev<br />
B<br />
2.07<br />
Date:<br />
Tuesday, February 05, 2002<br />
Sheet 12 of 16<br />
2<br />
1
8<br />
INDUCTOR<br />
1<br />
Sheet 13 of 16<br />
1<br />
7<br />
6<br />
5<br />
4<br />
3<br />
2<br />
Copyright 2002 <strong>Intel</strong> Corporation<br />
LCD CPLD<br />
D5<br />
U33<br />
2<br />
R216<br />
DCNEG14V<br />
U40<br />
1<br />
{14}<br />
XCR3128XL-10VQ100C<br />
3<br />
100K<br />
Xilinx CPLD<br />
2<br />
40<br />
{14} LCD_G4 A0<br />
E0_CLK1<br />
MAX633ACSA<br />
D6<br />
1<br />
{14} LCD_G5 A2<br />
E2<br />
41<br />
CF_nCD1 {10}<br />
Adj Step-up<br />
100<br />
D {14} LCD_SPS A4<br />
E4<br />
42<br />
nNEP_PRESENT {4,15}<br />
Sw Reg<br />
D<br />
99<br />
LCD_DC5V<br />
{14} LCD_CLS A5<br />
E5<br />
44<br />
CF_PWR_ON {6}<br />
1<br />
8<br />
ZENER_3P3V<br />
LBI COMP<br />
98<br />
{14} LCD_LP A7<br />
E7<br />
45<br />
CF_PWR {10}<br />
DC_15V {14,15}<br />
DCNEG11P7V {14}<br />
97<br />
46<br />
{14} LCD_SPL A8<br />
E8<br />
GPIO_11<br />
96<br />
47<br />
{3}<br />
2<br />
7<br />
LBO<br />
VFB<br />
{14} LCD_G0 A10<br />
E10<br />
{14} LCD_G1<br />
94<br />
A12<br />
E12<br />
48<br />
nXCV_ADD_OE {6,7}<br />
3 6<br />
93<br />
49<br />
L3<br />
GND CP<br />
{14} LCD_G2 A13<br />
E13<br />
92<br />
50<br />
{14} LCD_G3 A15_CLK3<br />
E15<br />
MBREQ_CF_DETECT {3,15}<br />
4<br />
5<br />
LX<br />
VOUT<br />
SYSCLK {8,15} VBATT<br />
14<br />
{14} LCD_SPR B0<br />
F0<br />
52<br />
nGFX_PRESENT {4,15}<br />
470UH<br />
REV {4} LCD_TYPE<br />
13<br />
53<br />
L_DD_0 {3}<br />
+<br />
C129<br />
B2<br />
F2<br />
12<br />
54<br />
L_DD_1 {3}<br />
MAX633ACSA<br />
B4<br />
F4<br />
4.7UF<br />
10<br />
{14} LCD_R2 B5<br />
F5<br />
55<br />
L_DD_2<br />
9<br />
{3}<br />
{14} LCD_R3 B7<br />
F7<br />
56<br />
L_DD_3<br />
8<br />
{3}<br />
{14} LCD_R4 B8<br />
F8<br />
57<br />
L_DD_4 {3}<br />
{14} LCD_R5<br />
7<br />
B10<br />
F10<br />
58<br />
L_DD_5<br />
6<br />
{3}<br />
{14} LCD_LBR B12<br />
F12<br />
60<br />
L_DD_6<br />
5<br />
{3}<br />
{14} LCD_PS B13<br />
F13<br />
61<br />
L_DD_7<br />
4<br />
{3}<br />
{6} CPLD1_TDO B15_TDI<br />
F15_TCK<br />
62<br />
JTAG_TCK {3,6,10,11,14}<br />
25<br />
{6} MMC_PWR_ON<br />
C0<br />
G0<br />
63<br />
L_DD_8<br />
24<br />
{3,4}<br />
{2,11} nMMC_DETECT<br />
C2<br />
G2<br />
64<br />
L_DD_9<br />
23<br />
{3,4}<br />
{11} MMC_ON C4<br />
G4<br />
65<br />
L_DD_10<br />
22<br />
{3,4} {14} SHARP_LCD_PWR_ON<br />
C5<br />
G5<br />
67<br />
L_DD_11<br />
C 21<br />
{3,4}<br />
{14} LCD_R0 C7<br />
G7<br />
68<br />
L_DD_12 {3,4}<br />
C<br />
20<br />
{14} LCD_R1 C8<br />
G8<br />
69<br />
L_DD_13<br />
19<br />
{3,4}<br />
{14} LCD_B1 C10<br />
G10<br />
70<br />
L_DD_14<br />
17<br />
{3,4}<br />
{14} LCD_B0 C12<br />
G12<br />
71<br />
L_DD_15 {14} LCD_CLK 16<br />
{3,4}<br />
C13<br />
G13<br />
72<br />
L_LCLK<br />
15<br />
{3}<br />
{3,6,10,11,14} JTAG_TMS<br />
C15_TMS G15_TDO<br />
73<br />
CPLD2_TDO {3}<br />
R213<br />
37<br />
D0_CLK2<br />
H0<br />
75<br />
L_FCLK<br />
36<br />
76<br />
{3}<br />
100K<br />
{3} nVDD_FAULT<br />
D2<br />
H2<br />
L_BIAS<br />
35<br />
{3}<br />
LCD_DC5V<br />
{15} VDD_FAULT D4<br />
H4<br />
77<br />
33<br />
U44<br />
D5<br />
H5<br />
78<br />
LCD_PWR_ON {6,14}<br />
{14} LCD_ENAB<br />
32<br />
D7<br />
H7<br />
79<br />
SA_PWR_EN {3,12}<br />
Note: On<br />
31<br />
80<br />
R214<br />
{14} LCD_NCLK D8<br />
H8<br />
nRESET_OUT {3,6,11,15}<br />
30<br />
HBL-0204<br />
{14} LCD_B5 D10<br />
H10<br />
81<br />
FLASH_nRP {5}<br />
A1<br />
VCC<br />
board Back<br />
29<br />
83<br />
H CN2-1<br />
{14} LCD_B2<br />
LCD_MODE {14}<br />
A2<br />
100K<br />
D12<br />
H12<br />
{3,8,10,11,12,14}<br />
VIN<br />
28<br />
A3<br />
Light Inverter<br />
{14} LCD_B3 D13<br />
H13<br />
84<br />
{14} LCD_B4<br />
LCD_UBL {14}<br />
R207<br />
ON_OFF<br />
27<br />
L CN2-2<br />
D15<br />
H15<br />
85<br />
{2} SA_PWM_0<br />
A4<br />
GND<br />
for Toshiba<br />
0<br />
87<br />
DNI<br />
PIEZOELECTRIC INVERTER Display<br />
{3} L_PCLK IN0_CLK0<br />
89<br />
R171<br />
IN1<br />
88<br />
IN2<br />
{10} CF_nCD2<br />
90<br />
100K<br />
IN3<br />
DC3P3V<br />
3<br />
VDD_1<br />
VSS_1<br />
11<br />
B 18<br />
26<br />
B<br />
VDD_2<br />
VSS_2<br />
34<br />
VDD_3<br />
VSS_3<br />
38<br />
39<br />
VDD_4<br />
VSS_4<br />
43<br />
51<br />
59<br />
DNI<br />
Back Light<br />
VDD_5<br />
VSS_5<br />
66<br />
74<br />
R151<br />
VDD_6<br />
VSS_6<br />
82<br />
86<br />
Header for<br />
VDD_7<br />
VSS_7<br />
{2} SA_PWM_0<br />
91<br />
VDD_8<br />
VSS_8<br />
95<br />
4.99K<br />
Off Board<br />
Sharp Back<br />
XCR3128XL-10VQ100C<br />
Light Inverter<br />
LCD_DC5V<br />
R172<br />
LCD_DC5V<br />
{14} VCOM<br />
U35<br />
U34<br />
R173<br />
10<br />
J11<br />
SN74HCT04D<br />
DC5P5V<br />
{14} PVEE<br />
SN74HCT04D<br />
10<br />
Hex Inv<br />
1<br />
C109<br />
Hex Inv<br />
R175<br />
1<br />
1A<br />
14<br />
2<br />
VDD<br />
LCD_DC4V {14} {6} LIGHT_PWR_ON<br />
1<br />
1A<br />
14<br />
2<br />
2<br />
3<br />
VDD<br />
1Y<br />
REV<br />
R152<br />
2<br />
13<br />
4<br />
1Y<br />
REV<br />
10K<br />
15UF<br />
6A<br />
13<br />
3<br />
12<br />
nREV<br />
2A 6Y<br />
0<br />
5<br />
6A<br />
AB_SW {14}<br />
{3,8,10,11,12,14} VBATT<br />
3<br />
+<br />
2A<br />
12<br />
4<br />
6Y<br />
2Y<br />
4<br />
11<br />
A 2Y<br />
5A<br />
11<br />
10<br />
Layout Note:<br />
A<br />
5A<br />
5Y<br />
10<br />
5<br />
VBATT ADD WIDE<br />
53261-0590<br />
5Y<br />
3A<br />
5<br />
6<br />
9<br />
ETCH<br />
3A<br />
3Y 4A<br />
6<br />
9<br />
4Y<br />
8<br />
3Y 4A<br />
8<br />
V0 {14}<br />
7<br />
4Y<br />
GND<br />
7<br />
<strong>PXA250</strong> Processor Reference Design<br />
GND<br />
C111<br />
SN74HCT04PWR<br />
SN74HCT04PWR<br />
{14} DCNEG14V<br />
Size Rev<br />
15UF<br />
B<br />
2.07<br />
R177<br />
15K<br />
2<br />
1<br />
R176<br />
27.4K<br />
4.7UF<br />
C110<br />
1<br />
R174<br />
5K<br />
3<br />
C107<br />
0.1UF<br />
C108<br />
0.1UF<br />
C105<br />
0.1UF<br />
C106<br />
0.1UF<br />
+<br />
+<br />
R208<br />
+<br />
0<br />
22UF<br />
C120<br />
C122<br />
0.1UF<br />
C126<br />
C127<br />
0.1UF<br />
R202<br />
9.76K<br />
1 2<br />
C121<br />
22UF<br />
+<br />
+<br />
C93<br />
0.1UF C128<br />
22UF<br />
0.1UF<br />
1<br />
2<br />
3<br />
Pg. 13<br />
8<br />
7<br />
6<br />
5<br />
4<br />
3<br />
Date:<br />
Tuesday, February 05, 2002<br />
2
8<br />
C C<br />
1<br />
7<br />
6<br />
5<br />
4<br />
3<br />
2<br />
Copyright 2002 <strong>Intel</strong> Corporation<br />
LCD Power<br />
3 4<br />
3 4<br />
D {6,13} LCD_PWR_ON<br />
EN BYP<br />
{6,13} LCD_PWR_ON<br />
EN BYP<br />
D<br />
L_DC3P3V<br />
L_DC3P1V<br />
L_DC2P6V<br />
L_DC3P6V<br />
L_DC2P3V<br />
LEAA<br />
LE50<br />
L_DC2P1V<br />
L_DC1P15V<br />
L_DC1P9V<br />
L_DC0P5V<br />
L_DC2P35V<br />
L_DC1P6V<br />
{13} LCD_DC4V<br />
L_DC2P0V<br />
L_DC0P9V<br />
L_DC1P75V<br />
L_DC1P45V<br />
DC5P5V<br />
MIC5207-3.3BM5<br />
5<br />
LCD_DC5V U38<br />
3.3V LDO REG<br />
1<br />
MIC5207-4.0BM5<br />
{3,8,10,11,12,13} VBATT<br />
180ma<br />
5<br />
VIN<br />
VOUT<br />
LCD_DC3P3V<br />
4.0V LDO REG<br />
2<br />
GND<br />
+<br />
1 180ma<br />
VIN VOUT<br />
3 EN BYP<br />
4<br />
2<br />
GND<br />
LE33<br />
{13} SHARP_LCD_PWR_ON<br />
3 4<br />
EN BYP<br />
LE40<br />
J13<br />
1<br />
2<br />
U41<br />
MIC5207-BM5<br />
ADJ LDO REG<br />
VIN 180ma VOUT<br />
GND<br />
U36<br />
Sharp LCD Connector<br />
5<br />
DC5P5V U37<br />
LCD_DC5V<br />
1<br />
2<br />
MIC5207-5.0BM5<br />
5.0V LDO REG<br />
VIN 180ma VOUT<br />
GND<br />
5<br />
100UF<br />
+<br />
C116<br />
Pg. 14<br />
LCD_DC4V {13}<br />
(50)<br />
1<br />
AGND<br />
(49) V9<br />
2<br />
V9<br />
LCD Grey Scale<br />
(48)<br />
Touch Screen<br />
V8<br />
3<br />
V8<br />
(47) V7<br />
4<br />
V7<br />
Level Buffer<br />
(46)<br />
Connector<br />
V6<br />
5<br />
V6<br />
(45) V5<br />
6<br />
U39<br />
V5<br />
(44) V4<br />
7<br />
V4<br />
LCD_DC5V<br />
(43) V3<br />
8<br />
J21<br />
V3<br />
(42) V2<br />
9<br />
V2<br />
LMC6009<br />
1<br />
TSPY {8} (41) V1<br />
10<br />
V1<br />
9 Ch Buf Amp<br />
2<br />
TSMX {8}<br />
(40) V0<br />
11<br />
V0 {13} for TFT-LCD<br />
3<br />
TSMY {8}<br />
(39) VSHA<br />
12<br />
4<br />
LCD_SPR {13}<br />
L_DC3P3V<br />
A1A<br />
4<br />
TSPX {8}<br />
(38)<br />
13<br />
5<br />
42<br />
SPR<br />
L_DC0P5V<br />
A1B<br />
A1 OUT<br />
V1<br />
(37)<br />
14<br />
LCD_LBR {13}<br />
L_DC3P1V<br />
6<br />
LBR<br />
A2A<br />
(36) DCLK<br />
15<br />
LCD_CLK {13} L_DC0P9V<br />
7<br />
41<br />
V2<br />
487951-4<br />
A2B<br />
A2 OUT<br />
(35) LP 16<br />
LCD_LP {13}<br />
8<br />
LCD_PS<br />
Toshiba LCD Connector<br />
{13} L_DC2P6V<br />
A3A<br />
(34) PS 17<br />
L_DC1P45V<br />
9<br />
40<br />
A3B<br />
A3 OUT<br />
V3<br />
(33) DGND<br />
18<br />
L_DC2P35V<br />
10<br />
A4A<br />
(32) VSHD<br />
19<br />
LCD_DC3P3V<br />
L_DC1P75V<br />
11<br />
39<br />
V4<br />
J14<br />
A4B<br />
A4 OUT<br />
(31) B5<br />
20<br />
LCD_B5 {13}<br />
L_DC2P1V<br />
12<br />
A5A<br />
(30) B4<br />
21<br />
LCD_B4 {13}<br />
L_DC2P0V<br />
13<br />
36<br />
A5B<br />
A5 OUT<br />
V5<br />
B B<br />
(29) B3<br />
22<br />
LCD_B3 {13} L_DC1P9V<br />
14<br />
A6A<br />
1<br />
(28) B2<br />
23<br />
LCD_B2 {13}<br />
L_DC2P3V<br />
15<br />
35<br />
A6B<br />
A6 OUT<br />
V6<br />
2<br />
{13} LCD_NCLK<br />
(27) B1<br />
24<br />
LCD_B1 {13} 16<br />
L_DC1P6V<br />
A7A<br />
3<br />
(26) B0<br />
25<br />
LCD_B0 {13}<br />
17<br />
34<br />
L_DC2P6V<br />
A7B<br />
A7 OUT<br />
V7<br />
4<br />
{13} LCD_R0<br />
(25) G5<br />
26<br />
LCD_G5 {13}<br />
18<br />
L_DC1P15V<br />
A8A<br />
5<br />
LCD_R1 {13}<br />
(24) G4<br />
27<br />
LCD_G4 {13}<br />
19<br />
33<br />
L_DC3P3V<br />
A8B<br />
A8 OUT<br />
V8<br />
6<br />
{13} LCD_R2<br />
(23) G3<br />
28<br />
LCD_G3 {13}<br />
L_DC0P5V<br />
20<br />
A9A<br />
7<br />
LCD_R3 {13}<br />
(22) G2<br />
29<br />
LCD_G2 {13} L_DC3P6V<br />
21<br />
32<br />
A9B<br />
A9 OUT<br />
V9<br />
8<br />
{13} LCD_R4<br />
(21) G1<br />
30<br />
LCD_G1<br />
9<br />
{13} LCD_R5 {13}<br />
(20) G0<br />
31<br />
LCD_G0 {13}<br />
29<br />
{13} AB_SW A_B_SWITCH<br />
10<br />
(19) R5<br />
32<br />
LCD_R5<br />
11<br />
{13}<br />
LCD_G0 {13}<br />
(18) R4<br />
33<br />
LCD_R4 {13}<br />
1<br />
26<br />
NC1<br />
NC8<br />
12<br />
{13} LCD_G1<br />
(17) R3<br />
34<br />
LCD_R3 {13} 2<br />
27<br />
NC2<br />
NC9<br />
13<br />
LCD_G2 {13}<br />
(16) R2<br />
35<br />
LCD_R2 {13}<br />
3<br />
28<br />
NC3<br />
NC10<br />
14<br />
{13} LCD_G3<br />
(15) R1<br />
36<br />
LCD_R1 {13}<br />
22<br />
45<br />
LCD_G4 {13}<br />
(14) R0<br />
37<br />
LCD_R0 {13} 23 NC4<br />
NC11<br />
15<br />
46<br />
NC5<br />
NC12<br />
16<br />
{13} LCD_G5<br />
(13)<br />
38<br />
SPL<br />
LCD_SPL {13}<br />
24<br />
47<br />
NC6<br />
NC13<br />
17<br />
(12) VCOM1<br />
39<br />
VCOM {13}<br />
25<br />
48<br />
NC7<br />
NC14<br />
18<br />
{13} LCD_B0<br />
(11) VCOM2<br />
40<br />
VCOM<br />
19<br />
{13}<br />
LCD_B1 {13}<br />
(10) VEE2 41<br />
PVEE {13} 44<br />
43<br />
{13} LCD_DC4V VDD1<br />
GND1<br />
20<br />
{13} LCD_B2<br />
(9) VEE1 42<br />
PVEE {13}<br />
38<br />
37<br />
VDD2<br />
GND2<br />
21<br />
LCD_B3 {13}<br />
(8) VSS1 43<br />
DCNEG14V {13}<br />
30<br />
31<br />
VDD3<br />
GND3<br />
{13} LCD_B4<br />
22<br />
(7) CLS<br />
44<br />
LCD_CLS<br />
23<br />
{13}<br />
A LCD_B5 {13}<br />
(6) SPS<br />
45<br />
LCD_SPS<br />
24<br />
{13}<br />
A<br />
{13} LCD_ENAB<br />
(5) UL<br />
46<br />
LCD_UBL<br />
25<br />
{13} (4) MOD2<br />
47<br />
LCD_MODE {13}<br />
26<br />
LCD_DC3P3V<br />
(3) MOD1<br />
48<br />
LCD_MODE {13}<br />
27<br />
LCD_DC3P3V<br />
(2) VCC1<br />
49<br />
DCNEG11P7V {13}<br />
(1) VDD1 50<br />
DC_15V<br />
JAE<br />
{13,15}<br />
<strong>PXA250</strong> Processor Reference Design<br />
C119<br />
0.1UF<br />
R193<br />
28.7K<br />
R194<br />
12.4K<br />
R195<br />
40.2K<br />
R196<br />
22.6K<br />
R197<br />
36.5K<br />
2<br />
2<br />
C112<br />
C117<br />
0.1UF<br />
4.7UF<br />
4.7UF<br />
R188<br />
23.7K<br />
R189<br />
34.8K<br />
R190<br />
18.7K<br />
R191<br />
27.4K<br />
R192<br />
7.32K<br />
C113<br />
0.1UF<br />
1<br />
R183<br />
30.1K<br />
R184<br />
30.1K<br />
R185<br />
6.19K<br />
R186<br />
40.2K<br />
R187<br />
13.7K<br />
R204<br />
150K<br />
2<br />
R178<br />
17.4K<br />
R179<br />
22.6K<br />
R180<br />
34.8K<br />
R181<br />
9.76K<br />
R182<br />
42.2K<br />
R199<br />
100K<br />
C114<br />
0.1UF<br />
4.7UF<br />
+<br />
C115<br />
1<br />
+<br />
C118<br />
1<br />
IL-FHJ-27S-HF<br />
Molex<br />
TOP_CONN_50<br />
Size Rev<br />
B<br />
2.07<br />
8<br />
7<br />
6<br />
54104-5090<br />
5<br />
4<br />
3<br />
Date:<br />
Tuesday, February 05, 2002<br />
2<br />
Sheet 14 of 16<br />
1
8<br />
1<br />
7<br />
6<br />
5<br />
4<br />
3<br />
2<br />
Copyright 2002 <strong>Intel</strong> Corporation<br />
J15<br />
RCPT AMP<br />
J16<br />
RCPT AMP<br />
2<br />
1<br />
2<br />
1<br />
Pg. 15<br />
4<br />
{6,10} VX_A0<br />
C1<br />
3<br />
VX_A1 {6,10}<br />
4<br />
{6,10} VX_A0<br />
C1<br />
3<br />
VX_A1<br />
C2<br />
C1<br />
C2<br />
C1<br />
{6,10}<br />
6<br />
{6,10} VX_A2<br />
C2<br />
5<br />
VX_A3 {6,10}<br />
6<br />
VX_A5 {7,10}<br />
{6,10} VX_A2<br />
C2<br />
5<br />
VX_A3<br />
8<br />
7<br />
8<br />
7<br />
{6,10}<br />
{7,10} VX_A4<br />
{7,10} VX_A4<br />
VX_A5<br />
10<br />
{7,10}<br />
{7,10} VX_A6<br />
C3<br />
9<br />
VX_A7 {7,10}<br />
10<br />
{7,10} VX_A6<br />
C3<br />
9<br />
VX_A7<br />
C4<br />
C3<br />
C4<br />
C3<br />
{7,10}<br />
12<br />
{7,10} VX_A8<br />
C4<br />
11<br />
VX_A9 {7,10}<br />
12<br />
VX_A11 {7}<br />
{7,10} VX_A8<br />
C4<br />
11<br />
VX_A9<br />
14<br />
13<br />
14<br />
13<br />
{7,10}<br />
{7,10} VX_A10<br />
D {7} VX_A12<br />
VX_A13 {7}<br />
{7,10} VX_A10<br />
VX_A11<br />
16<br />
15<br />
16<br />
15<br />
{7}<br />
VX_A13 D<br />
DC3P3V<br />
{7} VX_A12<br />
18<br />
17<br />
{7} VX_A14<br />
VX_A15 {7}<br />
DC3P3V<br />
18<br />
17<br />
{7}<br />
VX_A15 {7} DC3P3V<br />
{7} VX_A16<br />
VX_A17 {7}<br />
{7} VX_A14<br />
20<br />
19<br />
DC3P3V<br />
20<br />
19<br />
VX_A19 {7}<br />
{7} VX_A16<br />
VX_A17<br />
22<br />
21<br />
22<br />
21<br />
{7}<br />
{7} VX_A18<br />
{7} VX_A20<br />
VX_A21 {7}<br />
{7} VX_A18<br />
VX_A19<br />
24<br />
{7}<br />
C5<br />
23<br />
24<br />
{7} VX_A20<br />
C5<br />
23<br />
VX_A21<br />
C6<br />
C5<br />
C6<br />
C5<br />
{7}<br />
26<br />
{7} VX_A22<br />
C6<br />
25<br />
VX_A23 {7}<br />
26<br />
{7} VX_A24<br />
VX_A25 {7}<br />
{7} VX_A22<br />
C6<br />
25<br />
VX_A23<br />
28<br />
27<br />
28<br />
27<br />
{7}<br />
{7} VX_A24<br />
VX_A25<br />
30<br />
{7}<br />
C7<br />
29<br />
30<br />
C7<br />
29<br />
C8<br />
C7<br />
C8<br />
C7<br />
{7} VX_nSDCS_0<br />
32<br />
C8<br />
31<br />
VX_nSDCS_2 {6}<br />
{7} VX_nSDCS_0<br />
32<br />
C8<br />
31<br />
VX_nSDCS_2<br />
{7}<br />
34<br />
33<br />
VX_nSDCAS<br />
VX_DQM_3 {7}<br />
34<br />
33<br />
{6}<br />
{7} VX_nSDCAS<br />
VX_DQM_3 {7} VX_nSDRAS 36<br />
35<br />
VX_DQM_2 {7}<br />
36<br />
35<br />
{7}<br />
VX_DQM_1 {7}<br />
{7} VX_nSDRAS<br />
VX_DQM_2<br />
38<br />
37<br />
38<br />
37<br />
{7}<br />
{3} BOOT_SEL_0<br />
{2} SA_SDCKE_0<br />
VX_DQM_0 {7}<br />
{3} BOOT_SEL_0<br />
VX_DQM_1<br />
40<br />
39<br />
40<br />
39<br />
{7}<br />
{2} SA_SDCKE_0<br />
VX_DQM_0 {7}<br />
{3} BOOT_SEL_1<br />
42<br />
41<br />
{3} BOOT_SEL_1<br />
42<br />
41<br />
{6} VX_SDCKE_1<br />
44<br />
C9<br />
43<br />
SA_SDCLK_0 {2,5}<br />
{6} VX_SDCKE_1<br />
44<br />
C9<br />
43<br />
SA_SDCLK_0<br />
C10<br />
C9<br />
C10<br />
C9<br />
{2,5}<br />
46<br />
C10<br />
45<br />
46<br />
C10<br />
45<br />
48<br />
47<br />
{7} VX_SDCLK_1<br />
VX_SDCLK_2 {6}<br />
48<br />
47<br />
{7} VX_SDCLK_1<br />
VX_SDCLK_2<br />
50<br />
{6}<br />
C11<br />
49<br />
50<br />
C11<br />
49<br />
C12<br />
C11<br />
C12<br />
C11<br />
{2,6} SA_RD_nWR<br />
52<br />
C12<br />
51<br />
MBREQ_CF_DETECT {3,13}<br />
{2,6} SA_RD_nWR<br />
52<br />
C12<br />
51<br />
MBREQ_CF_DETECT {3,13}<br />
{4,13}<br />
54<br />
53<br />
nGFX_PRESENT<br />
MBGNT_CF_IRQ {3,6}<br />
{4,13}<br />
54<br />
53<br />
nGFX_PRESENT<br />
MBGNT_CF_IRQ {3,6}<br />
C 56<br />
55<br />
{6,10} CF_IRQ_LVL2OE<br />
DREQ_1 {11}<br />
56<br />
55<br />
C<br />
nJTAG_TRST<br />
VX_D1 {7,10}<br />
{6,10} CF_IRQ_LVL2OE<br />
DREQ_1<br />
58<br />
57<br />
58<br />
57<br />
{11}<br />
VX_D1<br />
LCD_DC5V<br />
nJTAG_TRST<br />
60<br />
59<br />
{7,10}<br />
{7,10} VX_D0<br />
VX_D3 {7,10} LCD_DC5V<br />
60<br />
59<br />
{7,10} VX_D2<br />
VX_D5 {7,10}<br />
{7,10} VX_D0<br />
VX_D3 {7,10} LCD_DC5V<br />
62<br />
61<br />
{7,10} VX_D2<br />
62<br />
61<br />
VX_D5<br />
{7,10} VX_D4<br />
64<br />
{7,10}<br />
C13<br />
63<br />
VX_D7 {7,10}<br />
{7,10} VX_D4<br />
64<br />
C13<br />
63<br />
VX_D7<br />
C14<br />
C13<br />
LCD_DC5V<br />
C14<br />
C13<br />
{7,10}<br />
{7,10} VX_D6<br />
66<br />
C14<br />
65<br />
VX_D9 {7,10}<br />
{7,10} VX_D6<br />
66<br />
C14<br />
65<br />
VX_D9<br />
68<br />
67<br />
{7,10}<br />
{7,10} VX_D8<br />
VX_D11 {7,10}<br />
68<br />
67<br />
VX_D11 {7,10} DC3P3V<br />
{7,10} VX_D10<br />
VX_D13 {7,10}<br />
{7,10} VX_D8<br />
70<br />
DC3P3V<br />
C15<br />
69<br />
70<br />
{7,10} VX_D10<br />
C15<br />
69<br />
VX_D13<br />
C16<br />
C15<br />
C16<br />
C15<br />
{7,10}<br />
72<br />
{7,10} VX_D12<br />
C16<br />
71<br />
VX_D15 {7,10}<br />
72<br />
{7,10} VX_D12<br />
C16<br />
71<br />
VX_D15 {7,10}<br />
{7,10} VX_D14<br />
74<br />
73<br />
{7,10} VX_D14<br />
74<br />
73<br />
76<br />
75<br />
{7} VX_D16<br />
VX_D17 {7}<br />
76<br />
75<br />
{7} VX_D18<br />
VX_D19 {7}<br />
{7} VX_D16<br />
VX_D17<br />
78<br />
77<br />
78<br />
77<br />
{7}<br />
VX_D19 {7}<br />
{7} VX_D20<br />
VX_D21 {7}<br />
{7} VX_D18<br />
80<br />
79<br />
80<br />
79<br />
VX_D21 {7}<br />
{7} VX_D22<br />
VX_D23 {7}<br />
{7} VX_D20<br />
82<br />
81<br />
82<br />
81<br />
VX_D23 {7}<br />
{7} VX_D24<br />
VX_D25 {7}<br />
{7} VX_D22<br />
84<br />
C17<br />
83<br />
{7} VX_D24<br />
84<br />
C17<br />
83<br />
VX_D25<br />
C18<br />
C17<br />
C18<br />
C17<br />
{7}<br />
86<br />
{7} VX_D26<br />
C18<br />
85<br />
VX_D27 {7}<br />
{7}<br />
86<br />
{7} VX_D28<br />
VX_D29 {7}<br />
VX_D26<br />
C18<br />
85<br />
VX_D27<br />
88<br />
87<br />
88<br />
87<br />
{7}<br />
{7} VX_D30<br />
VX_D31 {7}<br />
{7} VX_D28<br />
VX_D29<br />
90<br />
{7}<br />
C19<br />
89<br />
90<br />
{7} VX_D30<br />
C19<br />
89<br />
VX_D31<br />
C20<br />
C19<br />
C20<br />
C19<br />
{7}<br />
{4,13} nNEP_PRESENT<br />
92<br />
C20<br />
91<br />
IN_PWR {10,12}<br />
{4,13} nNEP_PRESENT<br />
92<br />
C20<br />
91<br />
IN_PWR<br />
94<br />
93<br />
{10,12}<br />
{2} SA_RDY<br />
SA_nCS_5 {2,6} DC3P3V<br />
94<br />
93<br />
SA_nCS_5 {2,6}<br />
B B<br />
{7} VX_nWE<br />
SA_nCS_4 {2,6}<br />
{7} {2}<br />
VX_nWE<br />
SA_RDY<br />
96<br />
95<br />
96<br />
95<br />
SA_nCS_4<br />
DC3P3V<br />
{2,6}<br />
{6,7} VX_nOE<br />
98<br />
97<br />
SA_nCS_3 {2,6}<br />
DC3P3V<br />
{6,7} VX_nOE<br />
98<br />
97<br />
SA_nCS_3 {2,6} DC3P3V<br />
{13,14}<br />
100<br />
99<br />
DC_15V<br />
nNEP_REG_CS {6,10}<br />
{13,14} DC_15V<br />
100<br />
99<br />
nNEP_REG_CS {6,10}<br />
{3,10,11}<br />
102<br />
101<br />
nRESET_IN<br />
nNEP_FLASH_CS {6}<br />
{3,10,11} nRESET_IN<br />
102<br />
101<br />
nNEP_FLASH_CS {6}<br />
{3,6,11,13} nRESET_OUT<br />
104<br />
C21<br />
103<br />
SA_nCS_0 {2,6}<br />
{3,6,11,13} nRESET_OUT<br />
104<br />
C21<br />
103<br />
SA_nCS_0 {2,6}<br />
C22<br />
C21<br />
C22<br />
C21<br />
{6,10} CF_GFX_RESET<br />
106<br />
C22<br />
105<br />
{6,10} CF_GFX_RESET<br />
106<br />
C22<br />
105<br />
{3,10} GFX_IRQ_CF_BVD2<br />
108<br />
107<br />
SYSCLK {8,13} {3,10} GFX_IRQ_CF_BVD2<br />
108<br />
107<br />
SYSCLK {8,13}<br />
110<br />
110<br />
{13} VDD_FAULT C23<br />
109<br />
{13} VDD_FAULT C23<br />
109<br />
C24<br />
C23<br />
C24<br />
C23<br />
112<br />
{3,10} SA1111_IRQ_CF_BVD1<br />
C24<br />
111<br />
SA_nPOE {2,6}<br />
112<br />
{10,12} IN_PWR<br />
SA_nPWE {2,6}<br />
{3,10} SA1111_IRQ_CF_BVD1<br />
C24<br />
111<br />
SA_nPOE<br />
114<br />
113<br />
114<br />
113<br />
{2,6}<br />
{2,6} SA_nIOIS16<br />
SA_nPIOW {2,6}<br />
{10,12} IN_PWR<br />
SA_nPWE<br />
116<br />
115<br />
116<br />
115<br />
{2,6}<br />
{2,6} SA_nIOIS16<br />
SA_nPIOW<br />
118<br />
117<br />
{2,6}<br />
{2,6} SA_nPWAIT<br />
SA_nPIOR {2,6}<br />
118<br />
117<br />
{2,6} SA_nPWAIT<br />
SA_nPIOR<br />
120<br />
119<br />
{2,6}<br />
{2} SA_PSKTSEL<br />
SA_nPCE_1 {2,6}<br />
120<br />
119<br />
{2} SA_PSKTSEL<br />
SA_nPCE_1 {2,6}<br />
{2,6} SA_nPREG<br />
122<br />
121<br />
SA_nPCE_2 {2,6}<br />
{2,6} SA_nPREG<br />
122<br />
121<br />
SA_nPCE_2 {2,6}<br />
124<br />
C25<br />
123<br />
124<br />
C25<br />
123<br />
C26<br />
C25<br />
C26<br />
C25<br />
126<br />
{11} DVAL_1<br />
C26<br />
125<br />
SA_BT_RXD {2,11}<br />
126<br />
SA_BT_RXD {2,11}<br />
{11} DVAL_0<br />
SA_BT_TXD {2,11}<br />
{11} DVAL_1<br />
C26<br />
125<br />
128<br />
127<br />
128<br />
127<br />
{11} DVAL_0<br />
SA_BT_TXD {2,11}<br />
130<br />
{11} DREQ_0<br />
C27<br />
129<br />
SWAP_FLASH {6}<br />
130<br />
{11} DREQ_0<br />
C27<br />
129<br />
SWAP_FLASH<br />
C28<br />
C27<br />
C28<br />
C27<br />
{6}<br />
{3,10} GPIO_0<br />
132<br />
C28<br />
131<br />
SA_FF_TXD {2,10}<br />
{3,10} GPIO_0<br />
132<br />
C28<br />
131<br />
SA_FF_TXD<br />
134<br />
133<br />
{2,10}<br />
A {3,9} USB_WAKE<br />
SA_FF_RXD {2,10}<br />
134<br />
133<br />
{3,9} USB_WAKE<br />
SA_FF_RXD<br />
136<br />
135<br />
136<br />
135<br />
{2,10}<br />
A<br />
{2,10,12} SA_I2C_SDA<br />
138<br />
137<br />
{2,10,12} SA_I2C_SCL<br />
nVBATT_LOW_IRQ {3,12}<br />
{2,10,12} SA_I2C_SDA<br />
138<br />
137<br />
{2,10,12} SA_I2C_SCL<br />
nVBATT_LOW_IRQ<br />
140<br />
139<br />
140<br />
139<br />
{3,12}<br />
536279-6<br />
536279-6<br />
<strong>PXA250</strong> Processor Reference Design<br />
8<br />
Expansion<br />
Header 1<br />
7<br />
6<br />
5<br />
4<br />
Expansion<br />
Header 2<br />
3<br />
Size Rev<br />
B<br />
2.07<br />
Date:<br />
Tuesday, February 05, 2002<br />
Sheet 15 of 16<br />
2<br />
1
8<br />
B B<br />
A A<br />
<strong>PXA250</strong> Processor Reference Design<br />
1<br />
Pg. 16<br />
Sheet 16 of 16<br />
1<br />
7<br />
6<br />
5<br />
4<br />
3<br />
2<br />
Copyright 2002 <strong>Intel</strong> Corporation<br />
Revision Tracking Changes<br />
R 2.00 - 09-21-01 - Inital Release<br />
R 2.01 - 09-25-01 - CHRGR_PRESENT signal changed to nCHRGR_PRESENT to properly represent active low signal - Pages 2, 3 & 12<br />
R 2.01 - 09-25-01 - R281, nCHRGR_PRESENT 100k pull-up added - Page 2<br />
R 2.01 - 09-25-01 - R262, PLL_SENSE pull-down, removed from DNI list - Page 3<br />
R 2.01 - 09-25-01 - C60, C65, R97 & R98 Removed from schematics - Page 8<br />
D D<br />
R 2.01 - 09-25-01 - C3 & C4 values changed to 1uF - Page 9<br />
R 2.01 - 09-25-01 - U20 powered from AUDIO3P3V instead of DC3P3V - Page 9<br />
R 2.01 - 09-25-01 - C138 Added to DNI List - Page 12<br />
R 2.02 - 09-28-01 - U10, XCR3032C CPLD, replaced with newer XPLA3 XCR3032XL - Page 6<br />
R 2.02 - 09-28-01 - Changed U43 part description to properly reflect part - Page 12<br />
R 2.02 - 09-28-01 - R276 9.76k resistor replaced with 19.6k resistor - Page 12<br />
R 2.02 - 09-28-01 - R276 .15 ohm resistor replaced with .1 ohm resistor - Page 12<br />
R 2.02 - 09-28-01 - U33, XCR3128 CPLD, replaced with newer XPLA3 XCR3128XL - Page 13<br />
R 2.03 - 10-10-01 - Y4, Changed component vendor - Page 3<br />
R 2.03 - 10-10-01 - R275, Changed component vendor - Page 12<br />
R 2.03 - 10-10-01 - R276, 19.6k resistor, replaced with 20k resistor - Page 12<br />
R 2.04 - 10-12-01 - Q1, P-channel MOSFET, replaced with a higher power dissipating component - Page 12<br />
R 2.05 - 10-16-01 - C53,C54,C55 & C56 Moved to prevent coupling with the UCB1400 - Page 8<br />
R 2.05 - 10-16-01 - R282, 0 ohm resistor, Added UCB1400 power test point- Page 8<br />
R 2.05 - 10-16-01 - R99, 0 ohm resistor, replaced with 10 ohm resistor - Page 8<br />
R 2.05 - 10-16-01 - R99 connected to AUDIO3P3V - Page 8<br />
R 2.06 - 11-09-01 - Y4, Changed component vendor - Page 3<br />
R 2.06 - 11-09-01 - R275, Changed component vendor - Page 12<br />
R 2.06 - 11-09-01 - Changed C143 part description to properly reflect part- Page 12<br />
R 2.07 - 02-05-02 - U2, 3.1V Reset Supervisor, replaced with 2.7V Reset Supervisor - Page 3<br />
R 2.07 - 02-05-02 - R112 & R115, 27.4 ohm resistor, replaced with 0 ohm resistor- Page 9<br />
R 2.07 - 02-05-02 - R168, 150K resistor, replaced with a 160K resistor - Page 12<br />
R 2.07 - 02-05-02 - R170, 100K resistor, added to DNI list - Page 12<br />
C R 2.07 - 02-05-02 - R210, 1K resistor, disconnected from IN_PWR net <strong>and</strong> connected to DC3P3V instead - Page 12<br />
C<br />
Size Rev<br />
B<br />
2.07<br />
8<br />
7<br />
6<br />
5<br />
4<br />
3<br />
Date:<br />
Tuesday, February 05, 2002<br />
2
Example Form Factor Reference Design Schematic Diagrams<br />
B-18 <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide
BBPXA2xx Development Baseboard<br />
Schematic Diagram<br />
C<br />
C.1 Schematic Diagram<br />
The BBPXA2xx schematic is on the following pages.<br />
<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide C-1
Page Function Page Function Page Function<br />
BBPXA2xx<br />
Table of Contents<br />
2 Top level block diagram<br />
18 SWITCHES<br />
34 LOGIC ANALYZER<br />
3 Processor Card Connector<br />
4 Data Buffers/Transceivers<br />
5 Data Buffers/Transceivers<br />
6 Address BUFFERS/TRANSCEIVERS<br />
7 SPX ADDRESS BUFFERS<br />
8 CONTROL BUFFERS/TRANSCEIVERS<br />
9 X ADDRESS BUFFERS<br />
10 BFR ADDRESS BUFFERS<br />
11 SRAM<br />
12 FLASH<br />
13 ROM<br />
14 REGISTER & CONTROL<br />
15 HEX DISPLAY HIGH<br />
16 HEX DISPLAY LOW<br />
17 LEDs & HEX SWITCHES<br />
19 SPII SPROM<br />
20 SA-1111 INTERFACE<br />
21 CF & PCMCIA I/O<br />
22 CF & PCMCIA PU<br />
23 SA-1111 USB KB/MS<br />
24 BUFFER CONTROL LOGIC<br />
25 LCD BUFFERS<br />
26 IrDA & FF SERIAL & USB<br />
27 CS4201 CODEC<br />
28 UCB1400 CODEC<br />
29 BB TOUCH SCREEN & GPIO HEADER<br />
30 CODEC MUX & SPII 2.5V<br />
31 SDCARD & BT SERIAL<br />
32 10Mbps ETHERNET<br />
33 XPANSION PORT<br />
35 RESET & FAULT SWITCHES<br />
36 3.3V & 5V SUPPLY<br />
37 POWER SUPPLY INPUT<br />
38 SPARES
BBPXA2xx Development Baseboard Schematic Diagram<br />
C-40 <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide
<strong>PXA250</strong> Processor Card Schematic<br />
Diagram<br />
D<br />
D.1 Schematic Diagram<br />
The DC<strong>PXA250</strong> processor card schematic is on the following pages.<br />
<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide D-1
DC<strong>PXA250</strong> Processor Card<br />
32-bit version<br />
TABLE OF CONTENTS<br />
PAGE FUNCTION<br />
2 PROCESSOR --- <strong>PXA250</strong> 32-BIT<br />
3 SDRAM<br />
4 CONNECTOR (MEMORY <strong>and</strong> I/O SIGNALS)<br />
5 CLOCKS<br />
6 JTAG CONNECTOR &<br />
PLL <strong>and</strong> CORE VOLTAGE REGULATORS<br />
7 VOLTAGE REGULATOR CONTROL<br />
CPLD AND I/O EXPANDER<br />
8 Visibility<br />
9-11 Bus Terminators
<strong>PXA210</strong> Processor Card Schematic<br />
Diagram<br />
E<br />
E.1 Schematic Diagram<br />
The DC<strong>PXA210</strong> processor card schematic is on the following pages.<br />
<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide E-1
DC<strong>PXA210</strong> Processor Card<br />
4 CONNECTOR (MEMORY <strong>and</strong> I/O SIGNALS)<br />
6 JTAG CONNECTOR &<br />
PLL <strong>and</strong> CORE VOLTAGE REGULATORS<br />
9-13 Bus Terminators <strong>and</strong> Signal MUX<br />
16-bit version<br />
TABLE OF CONTENTS<br />
PAGE FUNCTION<br />
2 PROCESSOR --- <strong>PXA210</strong> 16-BIT<br />
3 SDRAM<br />
5 CLOCKS<br />
7 VOLTAGE REGULATOR CONTROL<br />
CPLD AND I/O EXPANDER<br />
8 Visibility
<strong>PXA210</strong> Processor Card Schematic Diagram<br />
<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide E-3