datasheet: pdf
datasheet: pdf datasheet: pdf
AM26LV32 LOW-VOLTAGE HIGH-SPEED QUADRUPLE DIFFERENTIAL LINE RECEIVER SLLS202D – MAY 1995 – REVISED APRIL 2000 electrical characteristics over recommended supply-voltage and operating free-air temperature ranges (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VIT+ Differential input high-threshold voltage 0.2 V VIT– Differential input low-threshold voltage –0.2 V VIK Enable input clamp voltage II = – 18 mA –0.8 –1.5 V VOH High-level output voltage VID = 200 mV, IOH = – 5 mA 2.4 3.2 V VOL Low-level output voltage VID = – 200 mV, IOL = 5 mA 0.17 0.5 V IOZ High-impedance-state output current VO = 0 to VCC ±50 µA IIH(E) High-level enable input current VCC = 0 or 3 V, VI = 5.5 V 10 IIL(E) Low-level enable input current VCC = 3.6 V, VI = 0 V –10 rI Input resistance 7 12 kΩ II Input current VI = 5.5 V or – 0.3 V, All other inputs GND ±700 µA ICC Supply current VI(E) = VCC or GND, No load, line inputs open 8 17 mA Cpd Power dissipation capacitance‡ One channel 150 pF † All typical values are at VCC = 3.3 V and TA = 25°C. ‡ Cpd determines the no-load dynamic current: IS = Cpd × VCC × f + ICC. switching characteristics, V CC = 3.3 V, T A = 25°C tPLH tPHL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Propagation delay time, low- to high-level output Propagation delay time, high- to low-level output See Figure 1 µA 8 16 20 ns 8 16 20 ns tt Transistion time (tr or tf) See Figure 1 5 ns tPZH Output-enable time to high level See Figure 2 17 40 ns tPZL Output-enable time to low level See Figure 3 10 40 ns tPHZ Output-disable time from high level See Figure 2 20 40 ns tPLZ Output-disable time from low level See Figure 3 16 40 ns tsk(p) § Pulse skew 4 6 ns tsk(o) Pulse skew 4 6 ns tsk(pp) # Pulse skew (device to device) 6 9 ns § tsk(p) is |tPLH – tPHL| of each channel of the same device. tsk(o) is the maximum difference in propagation delay times between any two channels of the same device switching in the same direction. # tsk(pp) is the maximum difference in propagation delay times between any two channels of any two devices switching in the same direction. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION AM26LV32 LOW-VOLTAGE HIGH-SPEED QUADRUPLE DIFFERENTIAL LINE RECEIVER SLLS202D – MAY 1995 – REVISED APRIL 2000 Generator (see Note B) 50 Ω A B 50 Ω Y VO CL = 15 pF (see Note A) A Input B tPLH tPHL 2 V 1 V VCC G G (see Note C) Output 90% 90% 50% 50% 10% 10% tr tf VOH VOL NOTES: A. CL includes probe and jig capacitance. B. The input pulse is supplied by a generator having the following characteristics: ZO = 50 Ω, PRR = 10 MHz, tr and tf (10% to 90%) ≤ 2 ns, 50% duty cycle. C. To test the active-low enable G, ground G and apply an inverted waveform G. Figure 1. t PLH and t PHL Test Circuit and Voltage Waveforms VID = 1 V A B Y VO Generator (see Note B) 50 Ω G G RL = 2 kΩ CL = 15 pF (see Note A) VCC (see Note C) Input 50% 50% VCC 0 V tPZH tPHZ Output VOH VOH – 0.3 V Voff ≈ 0 NOTES: A. CL includes probe and jig capacitance. B. The input pulse is supplied by a generator having the following characteristics: ZO = 50 Ω, PRR = 10 MHz, tr and tf (10% to 90%) ≤ 2 ns, 50% duty cycle. C. To test the active-low enable G, ground G and apply an inverted waveform G. Figure 2. t PZH and t PHZ Test Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5
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PARAMETER MEASUREMENT INFORMATION<br />
AM26LV32<br />
LOW-VOLTAGE HIGH-SPEED<br />
QUADRUPLE DIFFERENTIAL LINE RECEIVER<br />
SLLS202D – MAY 1995 – REVISED APRIL 2000<br />
Generator<br />
(see Note B)<br />
50 Ω<br />
A<br />
B<br />
50 Ω<br />
Y<br />
VO<br />
CL = 15 pF<br />
(see Note A)<br />
A<br />
Input<br />
B<br />
tPLH<br />
tPHL<br />
2 V<br />
1 V<br />
VCC<br />
G G<br />
(see Note C)<br />
Output<br />
90% 90%<br />
50% 50%<br />
10% 10%<br />
tr<br />
tf<br />
VOH<br />
VOL<br />
NOTES: A. CL includes probe and jig capacitance.<br />
B. The input pulse is supplied by a generator having the following characteristics: ZO = 50 Ω, PRR = 10 MHz, tr and tf (10% to 90%)<br />
≤ 2 ns, 50% duty cycle.<br />
C. To test the active-low enable G, ground G and apply an inverted waveform G.<br />
Figure 1. t PLH and t PHL Test Circuit and Voltage Waveforms<br />
VID = 1 V<br />
A B<br />
Y<br />
VO<br />
Generator<br />
(see Note B)<br />
50 Ω<br />
G<br />
G<br />
RL = 2 kΩ<br />
CL = 15 pF<br />
(see Note A)<br />
VCC<br />
(see Note C)<br />
Input<br />
50%<br />
50%<br />
VCC<br />
0 V<br />
tPZH<br />
tPHZ<br />
Output<br />
<br />
VOH<br />
VOH – 0.3 V<br />
Voff ≈ 0<br />
NOTES: A. CL includes probe and jig capacitance.<br />
B. The input pulse is supplied by a generator having the following characteristics: ZO = 50 Ω, PRR = 10 MHz, tr and tf (10% to 90%)<br />
≤ 2 ns, 50% duty cycle.<br />
C. To test the active-low enable G, ground G and apply an inverted waveform G.<br />
Figure 2. t PZH and t PHZ Test Circuit and Voltage Waveforms<br />
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265<br />
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