16-bit Serial DAC

19-1572; Rev 0; 12/99
Low-Cost, +5V, Serial-Input,
Voltage-Output, 16-Bit DAC
General Description
The MAX5541 serial-input, voltage-output, 16-bit
monotonic digital-to-analog converter (DAC) operates
from a single +5V supply. The DAC output is
unbuffered, resulting in low 0.3mA supply current and
low 1LSB offset error. The DAC output range is 0V to
V REF . The DAC latch accepts a 16-bit serial word. A
power-on reset circuit clears the DAC output to 0V
(unipolar mode) when power is initially applied.
The 10MHz 3-wire serial interface is SPI/QSPI/
MICROWIRE compatible and interfaces directly with
optocouplers for applications requiring isolation. The
MAX5541 is available in an 8-pin SO package.
Features
♦ Full 16-Bit Performance Without Adjustments
♦ +5V Single-Supply Operation
♦ Low Power: 1.5mW
♦ 1µs Settling Time
♦ Unbuffered Voltage Output Directly Drives 60kΩ
Loads
♦ SPI/QSPI/MICROWIRE-Compatible Serial Interface
♦ Power-On Reset Circuit Clears DAC Output to 0V
(unipolar mode)
♦ Schmitt Trigger Inputs for Direct Optocoupler
Interface
MAX5541
Applications
High-Resolution Offset and Gain Adjustment
Industrial Process Control
Automated Test Equipment
Data Acquisition Systems
PART
MAX5541CSA
MAX5541ESA
Ordering Information
TEMP. RANGE PIN-PACKAGE
0°C to +70°C 8 SO
-40°C to +85°C 8 SO
Pin Configuration
Functional Diagram
TOP VIEW
V DD
OUT
1
8
V DD
REF
MAX5541
16-BIT DAC
OUT
AGND
REF
CS
2
3
4
MAX5541
7
6
5
DGND
DIN
SCLK
CS
DIN
SCLK
CONTROL
LOGIC
16-BIT DATA LATCH
SERIAL INPUT REGISTER
AGND
SO
DGND
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products 1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.

Low-Cost, +5V, Serial-Input,
Voltage-Output, 16-Bit DAC
MAX5541
ABSOLUTE MAXIMUM RATINGS
V DD to DGND............................................................-0.3V to +6V
CS, SCLK, DIN to DGND..........................................-0.3V to +6V
REF to AGND, DGND..................................-0.3V to (V DD +0.3V)
AGND to DGND.....................................................-0.3V to +0.3V
OUT to AGND, DGND.................................. ............-0.3V to V DD
Maximum Current into Any Pin............................................50mA
Continuous Power Dissipation (T A = +70°C)
8-Pin SO (derate 5.88mW/°C above +70°C)................471mW
Operating Temperature Ranges
MAX5541CSA .....................................................0°C to +70°C
MAX5541ESA ..................................................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10sec) ............................ +300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V DD = +5V ±5%, V REF = +2.5V, V AGND = V DGND = 0, T A = T MIN to T MAX , unless otherwise noted. Typical values are at T A = +25°C.)
Resolution
PARAMETER
Gain-Error Tempco
DAC Output Resistance
Power-Supply Rejection
REFERENCE INPUT
Reference Input Range
Reference Input Resistance
(Note 4)
N
R OUT
PSR
V REF
R REF
T A = +25°C
T A = T MIN to T MAX
T A = T MIN to T MAX
T A = +25°C
T A = T MIN to T MAX
(Note 2)
4.75V ≤ V DD ≤ 5.25V
(Note 3)
CONDITIONS
Integral Nonlinearity INL V DD = 5V
±4 ±16
Zero-Code Offset Error
Zero-Code Tempco
Gain Error (Note 1)
SYMBOL
STATIC PERFORMANCE—ANALOG SECTION (R L = ∞)
Differential Nonlinearity
Output Settling Time
DNL
ZSE
ZS TC
Guaranteed monotonic
DYNAMIC PERFORMANCE—ANALOG SECTION (R L = ∞)
Voltage-Output Slew Rate
SR
MIN TYP MAX
16
2.0 3.0
11.5
±0.5 ±1.0
±0.05
±0.1
6.25
±1
±2
±5
±10
±1.0
UNITS
Bits
LSB
LSB
ppm/°C
LSB
ppm/°C
kΩ
LSB
C L = 10pF (Note 5) 25 V/µs
To ± 1 /2LSB of FS, C L = 10pF 1 µs
Bits
V
kΩ
2 _______________________________________________________________________________________

Low-Cost, +5V, Serial-Input,
Voltage-Output, 16-Bit DAC
ELECTRICAL CHARACTERISTICS (continued)
(V DD = +5V ±5%, V REF = +2.5V, V AGND = V DGND = 0, T A = T MIN to T MAX , unless otherwise noted. Typical values are at T A = +25°C.)
PARAMETER
DAC Glitch Impulse
SYMBOL
CONDITIONS
Major-carry transition
Digital Feedthrough
Code = 0000 hex, CS = V DD ,
SCLK = V DIN = 0 to V DD levels
DYNAMIC PERFORMANCE—REFERENCE SECTION
Reference -3dB Bandwidth BW Code = FFFF hex
Reference Feedthrough
Code = 0000 hex, V REF = 1Vp-p at 100kHz
Signal-to-Noise Ratio
SNR
Reference Input Capacitance C IN
Code = 0000 hex
Code = FFFF hex
STATIC PERFORMANCE—DIGITAL INPUTS
Input High Voltage
V IH
Input Low Voltage
V IL
Input Current
I IN V IN = 0
Input Capacitance
C IN (Note 6)
Hysteresis Voltage
V H
POWER SUPPLY
Positive Supply Range
V DD
Positive Supply Current
I DD
Power Dissipation
PD
MIN TYP MAX
10
2.4
10
1
1
92
75
120
0.40
0.8
±1
10
4.75 5.25
0.3 1.1
1.5
UNITS
nVs
nVs
MHz
mVp-p
dB
pF
V
V
µA
pF
V
V
mA
mW
MAX5541
TIMING CHARACTERISTICS
(V DD = +5V ±5%, V REF = +2.5V, V AGND = V DGND = 0, CMOS inputs, T A = T MIN to T MAX , unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
SCLK Frequency
f CLK
10
MHz
SCLK Pulse Width High
t CH
45
ns
SCLK Pulse Width Low
t CL
45
ns
CS Low to SCLK High Setup
t CSS0
45
ns
CS High to SCLK High Setup
t CSS1
45
ns
SCLK High to CS Low Hold
t CSH0
(Note 6)
30
ns
SCLK High to CS High Hold
t CSH1
45
ns
DIN to SCLK High Setup
t DS
40
ns
DIN to SCLK High Hold
t DH
0
ns
V DD High to CS Low
(power-up delay)
20
µs
Note 1: Gain Error tested at V REF = +2.0V, +2.5V, and +3.0V.
Note 2: R OUT tolerance is typically ±20%.
Note 3: Min/Max ranges guaranteed by gain-error test. Operation outside min/max limits will result in degraded performance.
Note 4: Reference input resistance is code dependent, minimum at 8555 hex.
Note 5: Slew-rate value is measured from 0% to 63%.
Note 6: Guaranteed by design. Not production tested.
_______________________________________________________________________________________ 3

Low-Cost, +5V, Serial-Input,
Voltage-Output, 16-Bit DAC
MAX5541
(V DD = +5V, V REF = +2.5V, T A = +25°C, unless otherwise noted.)
SUPPLY CURRENT (mA)
0.50
0.45
0.40
0.35
0.30
0.25
SUPPLY CURRENT
vs. TEMPERATURE
0.20
-40 -20 0 20 40 60 80 100
TEMPERATURE (°C)
MAX5541-01
SUPPLY CURRENT (mA)
0.35
0.34
0.33
0.32
0.31
0.30
0.29
SUPPLY CURRENT
vs. REFERENCE VOLTAGE
0.28
0 1 2 3 4 5 6
REFERENCE VOLTAGE (V)
Typical Operating Characteristics
MAX5541-02
ZERO-CODE OFFSET ERROR (LSB)
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
ZERO-CODE OFFSET ERROR
vs. TEMPERATURE
-0.8
-1.0
-60 -20 20 60 100 140
TEMPERATURE (°C)
MAX5541-03
1.0
0.8
INTEGRAL NONLINEARITY
vs. TEMPERATURE
MAX5541-04
1.0
0.8
DIFFERENTIAL NONLINEARITY
vs. TEMPERATURE
MAX5541-05
1.0
0.8
GAIN ERROR
vs. TEMPERATURE
MAX5541-06
0.6
0.6
0.6
INL (LSB)
0.4
0.2
0
-0.2
-0.4
-0.6
-INL
+INL
DNL (LSB)
0.4
0.2
0
-0.2
-0.4
-0.6
-DNL
+DNL
GAIN ERROR (LSB)
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-0.8
-0.8
-1.0
-60 -20 20 60 100 140
-1.0
-60 -20 20 60 100 140
-1.0
-60 -20 20 60 100 140
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
INL (LSB)
1.00
0.75
0.50
0.25
0
-0.25
-0.50
-0.75
INTEGRAL NONLINEARITY
vs. CODE
MAX5541-07
DNL (LSB)
1.00
0.75
0.50
0.25
0
-0.25
-0.50
-0.75
DIFFERENTIAL NONLINEARITY
vs. CODE
MAX5541-08
REFERENCE CURRENT (µA)
200
160
120
80
40
REFERENCE CURRENT
vs. CODE
MAX5541-09
-1.00
0 10k 20k 30k 40k 50k 60k 70k
-1.00
0 10k 20k 30k 40k 50k 60k 70k
0
0 10k 20k 30k 40k 50k 60k 70k
DAC CODE
DAC CODE
DAC CODE
4 _______________________________________________________________________________________

Low-Cost, +5V, Serial-Input,
Voltage-Output, 16-Bit DAC
Typical Operating Characteristics (continued)
(V DD = +5V, V REF = +2.5V, T A = +25°C, unless otherwise noted.)
FULL-SCALE STEP RESPONSE
(f SCLK = 10MHz)
MAX5541-10
FULL-SCALE STEP RESPONSE
(f SCLK = 20MHz)
MAX5541-11
MAX5541
OUT
500mV/div
OUT
500mV/div
C L = 13pF, R L = ∞
1µs/div
C L = 13pF, R L = ∞
400ns/div
MAJOR-CARRY OUTPUT GLITCH
DIGITAL FEEDTHROUGH
MAX5541-12
MAX5541-13
CS
5V/div
SCLK
5V/div
OUT
AC-COUPLED
100mV/div
OUT
AC-COUPLED
50mV/div
2µs/div
CODE = 0000 hex
2µs/div
______________________________________________________________Pin Description
PIN
1
2
3
4
5
6
7
8
NAME
OUT
AGND
REF
CS
SCLK
DIN
DGND
V DD
FUNCTION
DAC Output Voltage
Analog Ground
Voltage Reference Input. Connect to external +2.5V reference.
Chip-Select Input
Serial-Clock Input. Duty cycle must be between 40% and 60%.
Serial-Data Input
Digital Ground
+5V Supply Voltage
_______________________________________________________________________________________ 5

Low-Cost, +5V, Serial-Input,
Voltage-Output, 16-Bit DAC
MAX5541
Detailed Description
The MAX5541 voltage-output, 16-bit digital-to-analog
converter (DAC) offers 16-bit monotonicity with less
than 1LSB differential linearity error. Serial-data transfer
minimizes the number of package pins required.
The MAX5541 is composed of two matched DAC sections,
with a 12-bit inverted R-2R DAC forming the 12
LSBs and the 4 MSBs derived from 15 identically
matched resistors. This architecture allows the lowest
glitch energy to be transferred to the DAC output on
major-carry transitions. It also decreases the DAC output
impedance by a factor of eight compared to a standard
R-2R ladder, allowing unbuffered operation in
medium-load applications. Figure 1 is the Timing
Diagram.
Digital Interface
The MAX5541 digital interface is a standard 3-wire connection
compatible with SPI/QSPI/MICROWIRE interfaces.
The chip-select input (CS) frames the serial data
loading at the data input pin (DIN). Immediately following
CS’s high-to-low transition, the data is shifted
synchronously and latched into the input register on the
rising edge of the serial-clock input (SCLK). After 16
data bits have been loaded into the serial input register,
it transfers its contents to the DAC latch on CS’s
low-to-high transition (Figure 2). Note that if CS does
not remain low during the entire 16 SCLK cycles, data
will be corrupted. In this case, reload the DAC latch
with a new 16-bit word.
External Reference
The MAX5541 operates with external voltage references
from 2V to 3V. The reference voltage determines
the DAC’s full-scale output voltage.
Power-On Reset
The MAX5541 has a power-on reset circuit to set the
DAC’s output to 0V in unipolar mode when V DD is first
applied. This ensures that unwanted DAC output voltages
will not occur immediately following a system
power-up, such as after power loss. In bipolar mode,
the DAC output is set to -V REF .
CS
t CSH1
t CSS1
t CSHO
t CSSO
t CH
t CL
SCLK
;;;;;;;;;
t DS
t DH
DIN D15 D14 D0
Figure 1. Timing Diagram
CS
SCLK
DAC
UPDATED
; ; ;;
DIN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
MSB
Figure 2. 3-Wire Interface Timing Diagram
LSB
6 _______________________________________________________________________________________

Low-Cost, +5V, Serial-Input,
Voltage-Output, 16-Bit DAC
Applications Information
Reference and Analog Ground Inputs
The MAX5541 operates with external voltage references
from 2V to 3V, and maintains 16-bit performance with
proper reference selection and application. Ideally, the
reference’s temperature coefficient should be less than
0.4ppm/°C to maintain 16-bit accuracy to within 1LSB
over the commercial (0°C to +70°C) temperature range.
Since this converter is designed as an inverted R-2R
voltage-mode DAC, the input resistance seen by the
voltage reference is code dependent. The worst-case
input-resistance variation is from 11.5kΩ (at code 8555
hex) to 200kΩ (at code 0000 hex). The maximum
change in load current for a 2.5V reference is 2.5V/
11.5kΩ = 217µA; therefore, the required load regulation
is 7ppm/mA for a maximum error of 0.1LSB. This implies
a reference output impedance of 60kΩ) without degradation of INL or DNL; only
the gain error is increased by externally loading the
DAC output.
External Output Buffer Amplifier
In unipolar mode, the output amplifier is used in a voltage-follower
connection. The DAC’s output resistance
is constant and is independent of input code; however,
the output amplifier’s input impedance should still be as
high as possible to minimize gain errors. The DAC’s
output capacitance is also independent of input code,
thus simplifying stability requirements on the external
amplifier.
In single-supply applications, precision amplifiers with
input common-mode ranges including AGND are available;
however, their output swings do not normally
include the negative rail (AGND) without significant performance
degradation. A single-supply op amp, such
as the MAX495, is suitable if the application does not
use codes near zero.
Since the LSBs for a 16-bit DAC are extremely small
(38.15µV for V REF = 2.5V), pay close attention to the
external amplifier’s input specification. The input offset
voltage can degrade the zero-scale error and might
require an output offset trim to maintain full accuracy if
the offset voltage is greater than 1/2LSB. Similarly, the
input bias current multiplied by the DAC output resistance
(typically 6.25kΩ) contributes to the zero-scale
error. Temperature effects also must be taken into consideration.
Over the commercial temperature range, the
offset voltage temperature coefficient (referenced to
+25°C) must be less than 0.42µV/°C to add less than
1/2LSB of zero-scale error. The external amplifier’s
input resistance forms a resistive divider with the DAC
output resistance, which results in a gain error. To contribute
less than 1/2LSB of gain error, the input resistance
typically must be greater than:
1 ⎡ 1 ⎤
6.25kΩ
/ ⎢ ⎥ 205MΩ
2 14
⎣⎢
2 ⎦⎥ =
The settling time is affected by the buffer input capacitance,
the DAC’s output capacitance, and PC board
capacitance. The typical DAC output voltage settling
time is 1µs for a full-scale step. Settling time can be significantly
less for smaller step changes. Assuming a
single time-constant exponential settling response, a
full-scale step takes 12 time constants to settle to within
1/2LSB of the final output voltage. The time constant is
equal to the DAC output resistance multiplied by the
total output capacitance. The DAC output capacitance
is typically 10pF. Any additional output capacitance will
increase the settling time.
MAX5541
_______________________________________________________________________________________ 7

Low-Cost, +5V, Serial-Input,
Voltage-Output, 16-Bit DAC
MAX5541
The external buffer amplifier’s gain-bandwidth product
is important because it increases the settling time by
adding another time constant to the output response.
The effective time constant of two cascaded systems,
each with a single time-constant response, is approximately
the root square sum of the two time constants.
The DAC output’s time constant is 1µs / 12 = 83ns,
ignoring the effect of additional capacitance. If the time
constant of an external amplifier with 1MHz bandwidth
is 1 / 2π (1MHz) = 159ns, then the effective time constant
of the combined system is:
( ) + ( )
⎡ 2 2⎤
⎢ 96ns 159ns ⎥ 186ns
⎣
⎢
⎦
⎥ =
This suggests that the settling time to within 1/2LSB of
the final output voltage, including the external buffer
amplifier, will be approximately 12 • 180ns = 2.15µs.
Digital Inputs and Interface Logic
The digital interface for the 16-bit DAC is based on a 3-
wire standard that is SPI/QSPI/MICROWIRE compatible.
The three digital inputs (CS, DIN, and SCLK) load
the digital input data serially into the DAC.
All of the digital inputs include Schmitt-trigger buffers to
accept slow-transition interfaces. This means that optocouplers
can interface directly to the MAX5541 without
additional external logic. The digital inputs are TTL/
CMOS-logic compatible.
Unipolar Configuration
Figure 3 shows the MAX5541 configured for unipolar
operation with an external op amp. The op amp is set for
unity gain, and Table 1 shows the codes for this circuit.
Table 1. Unipolar Code Table
DAC LATCH CONTENTS
MSB
LSB
1111 1111 1111 1111
1000 0000 0000 0000
0000 0000 0000 0001
0000 0000 0000 0000
V REF • (65,535 / 65,536)
V REF • (32,768 / 65,536) = 1/ 2 V REF
V REF • (1 / 65,536)
0V
ANALOG OUTPUT, V OUT
Power-Supply Bypassing and
Ground Management
For optimum system performance, use PC boards with
separate analog and digital ground planes. Wire-wrap
boards are not recommended. Connect the two ground
planes together at the low-impedance power-supply
source. Connect DGND and AGND together at the IC.
The best ground connection can be achieved by connecting
the DAC’s DGND and AGND pins together and
connecting that point to the system analog ground
plane. If the DAC’s DGND is connected to the system
digital ground, digital noise may get through to the
DAC’s analog portion.
Bypass V DD with a 0.1µF ceramic capacitor connected
between V DD and AGND. Mount it with short leads
close to the device. Ferrite beads can also be used to
further isolate the analog and digital power supplies.
TRANSISTOR COUNT: 2209
SUBSTRATE CONNECTED TO DGND
Chip Information
+5V
+2.5V
10µF
0.1µF
0.1µF
MC68XXXX
V DD
REF
(REFS)
PCS0
MOSI
SCLK
CS
DIN
SCLK
MAX5541
OUT
MAX495
EXTERNAL OP AMP
UNIPOLAR
OUT
DGND
AGND_
Figure 3. Typical Operating Circuit
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implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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