ADC JTAG I/O Intel LXT971ALC Ethernet Phy Altera EPXA1F484C3 ...
ADC JTAG I/O Intel LXT971ALC Ethernet Phy Altera EPXA1F484C3 ... ADC JTAG I/O Intel LXT971ALC Ethernet Phy Altera EPXA1F484C3 ...
5 4 3 2 1 D D C C SDQ[15:0] B20 C20 F18 C21 E20 F19 F20 G18 H19 G20 E22 H18 G21 H20 H17 H22 SDQ0 SDQ1 SDQ2 SDQ3 SDQ4 SDQ5 SDQ6 SDQ7 SDQ8 SDQ9 SDQ10 SDQ11 SDQ12 SDQ13 SDQ14 SDQ15 MT48LC16M16_TSOP54 IC5 B B13 G13 D13 A15 F13 C13 E13 D14 DQM-ECC DQS-ECC DQ-ECC0 DQ-ECC1 DQ-ECC2 DQ-ECC3 DQ-ECC4 DQ-ECC5 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 IC1B EPXA1F484C3 SDRAM Interface SDRAM Interface pins are not available as user I/Os! These pins are reserved for future functionallity and should be left unconnected SDA0 SDA1 SDA2 SDA3 SDA4 SDA5 SDA6 SDA7 SDA8 SDA9 SDA10 SDA11 SDA12 SDA13-BA0 SDA14-BA1 CLK CLKn CASn CLKE RAS WEn DQM0 DQM1 CS-N0 CS-N1 DQS0 DQS1 DDR-VS0 DDR-VS1 DDR-VS2 B17 G16 D16 F16 A19 E16 B18 F17 C17 D17 B19 D18 D19 C19 E18 C15 J16 A17 E15 C14 F14 E21 J20 G15 B16 D22 J17 D21 G22 B15 R8 10k R7 10k 3V3 RN20 4x330R SDR_CLK SDR_SDR_ SDR_CKE SDR_RAS SDR_WE SDR_DQML SDR_DQMH SDR_CS RN32 4x330R 8 7 6 5 1 2 3 4 8 7 6 5 1 2 3 4 8 7 6 5 1 2 3 4 8 7 6 5 1 2 3 4 3V3 RN21 4x330R RN38 4x330R 3V3 23 24 25 26 29 30 31 32 33 34 22 35 36 20 21 38 17 37 15 39 18 16 19 1 14 27 3 9 43 49 6 12 46 52 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 BA0 BA1 CLK CAS CKE DQML DQMH RAS WE CS VDD1 VDD2 VDD3 VDDQ1 VDDQ2 VDDQ3 VDDQ4 VSSQ1 VSSQ2 VSSQ3 VSSQ4 DQ0 2 DQ1 4 DQ2 5 7 DQ3 8 DQ4 DQ5 10 DQ6 11 DQ7 13 DQ8 42 44 DQ9 DQ10 45 DQ11 47 DQ12 48 DQ13 50 51 DQ14 53 DQ15 GND1 GND2 GND3 28 41 54 NC 40 SDQ0 SDQ1 SDQ2 SDQ3 SDQ4 SDQ5 SDQ6 SDQ7 SDQ8 SDQ9 SDQ10 SDQ11 SDQ12 SDQ13 SDQ14 SDQ15 GND B A 3V3 C15 C13 C12 C94 C91 C9 C10 C16 A 10n 47n 10n 47n 10n 47n 10n 47n Company : KIP Uni-Heidelberg / Lindenstruth Editor : Dirk Gottschalk Title DCS SDRAM Interface Size Document Number Rev A3 02 1.60 Date: 2003.12.19 14:00 Sheet 2 of 14 5 4 3 2 1
5 4 3 2 1 D C B A MTDIp MTDIn connected to ADC page 10 3V3 3V3 L1intTrig CRSTO GND ARdyn ADout ADin ADMCLK Header_07x2x2mm JTAG Master Output AP1 AP2 ARstn ACSn IO_C7 page 4 TTCrx C83 470n CON9 1 2 3 4 5 6 7 8 9 10 1112 1314 R97 C82 100n page 8 DCS-ROB con 100R 3V3 R102 10k C76 10n RN5 4x22R 8 7 6 5 1 2 3 4 1 2 3 4 RN6 8 7 6 5 4x22R C225 1n VErrIn Shaded area shows devices not used for KIP/TRD K18 IO-139 K19 IO-137 K20 IO-143 K21 IO-145 K15 IO-140 L15 IO-142 L16 IO-144 K17 IO-138 IC29 acts as a level translator from 1V8 to 3V3. MTCK 1V8 IC4 2 OUTA 3 OUTA 6 OUTB 5 OUTB 10 OUTC 11 OUTC 14 OUTD 13 OUTD AM26LV31C_SO16 1V8 nCfgNext 1V8 differential JTAG interface driver C224 1n EPXA1F484C3 IC1L L17 IO-147 IO-150 L18 IO-149 IO-153 L19 IO-141 L20 Block 13 I/Os IO-151 IO-146 IO-148 VCC 16 GND 8 R98 2k2 R81 100R R83 100R C88 100n IO-159 R22 IO-158 P22 IO-156 P20 R159 IC29 LMV7239M5 3V3 M19 M17 M16 L21 ASclk C95 1n +V 5 Out 1 -V 2 R87 100k 3V3 Boot_Fl TTCrx page 4 10k 4 -In +In 3 SCL SDA MTMS IO-157 N22 IO-154 N16 E_MJTG IO-155 M22 MTDI IO-152 M20 INA 1 INB 7 INC 9 IND 15 G 4 G 12 R160 C136 R18 100k 10n IC8 10k ShdwnNext 1 Sense1 VCC 8 2 7 Sense2 WDI 3 PFI PFO 6 4 GND RST 5 TPS3306-18DGK power supply supervisor and watchdog timer Test_Point TP29 1 R161 WD_In TP2 1 IO_C1 R90 3k3 3 R91 47k IO_C6 IO_C3 330R TD_CE IO_C4 IO_C2 page 8 DCS-ROB con MTDO D19 2 1 BAR43A page 4 TTCrx C86 100n 1 2 R121 150R 4 5 IC27 page 8 DCS-ROB con 3V3 Out VCC connected to TTCrx page 4 Dout0 1 LED6 green_0603 ShdwnNext IO_C5 TTC_rdy MRSTn TP13 GND 3 B 2 A 1 NC7SV86P5X R132 10k R15 4k7 Init_Done TP4 1 to TTCrx page 4 Dout1 Dout2 Dout3 Dout4 Dout5 R88 1 2 R117 10k 0R_Jmpr 1 D16 3 BAR43A optional R115 0R_Jmpr R116 TP3 nSTATUS C89 1n R24 4k7 3V3 K4 RDYnBSY * AB12 nSTATUS R4 nCONFIG R5 MSEL0 T3 MSEL1 K7 INIT-DONE * V12 CONF-DONE P19 nCE H3 nCEO N20 nCS * P17 CS * P16 nRS * M21 nWS * P18 10k DATA0 K3 DATA1 * J1 DATA2 * L5 DATA3 * L4 DATA4 * L6 DATA5 * L22 DATA6 * M18 DATA7 * R16 DCLK L7 CLKUSR * H4 nRESET H1 nPOR R22 10k debug_en must be high to switch off internal watchdog timer for testing and debugging! TMS page 8 DCS-ROB con page 6 flash eprom RSTn RSTn page 8 DCS-ROB con MRSTn IC1D EPXA1F484C3 3V3 Configuration pins and ports Pins with an (*) are available as user I/O, too. VERR Debug_EN TCK TD_FC DEBUG-EN JSELECT TCK Y11 TDI T20 TDO J4 TMS U11 TRST J6 Proc-TCK G3 Proc-TDI G7 Proc-TDO G2 Proc-TMS H6 G6 Proc-TRST Boot-Flash page 5 power K6 H5 J5 PTDO * DEV-OE U16 * DEV-CLRn R20 EN_SELECT EN_SELECT is reserved for future use. Connect to GND. R21 100R R76 0R_Jmpr C80 10n R14 10k H2 nCfgIn PTCK TP21 TP23 1 1 Header_05x2x2mm standart JTAG IF 1 2 3 4 5 6 7 8 9 10 1 1 PTDI TP22 1 3V3 1 2 3 4 TP25 3V3 RN42 4x10k PTRST E_Pause 8 7 6 5 IO_C0 connected to Ethernet page 9 DEV-OE and DEV-CLRn where expected not to be used as dedicated pins C26 1n R104 330R TP24 PTMS CON4 1 OC3 4 2 3 LTV357T TCK TD_EF TMS JTAG_Drvr_Dis 8 7 6 5 1 2 3 4 RN4 4x10k R56 3k3 R55 C227 10n 10k nShdwn MTDI 3V3 CRSTI page 8 DCS-ROB con page 5 power 4 3 OC1 LTV357T C78 470n C230 1n R67 10k 1 2 3V3 3 13 5 11 C77 100n IC6 OUTA OUTB OUTC OUTD 4 G 12 G R77 10k C149 10n VCC 16 GND 8 4 3 4 3 4 3 INA 2 INA 1 INB 14 INB 15 INC 6 INC 7 IND 10 IND 9 AM26LV32C_SO16 differential JTAG interface receiver OC4 LTV357T OC5 LTV357T OC2 LTV357T AN_GND TDOFn TDOFp 1 2 C109 1 2 1 2 R61 150R R73 150R C190 10n C148 10n 10n R170 100R R171 100R R172 100R Header_07x2x2mm JTAG Input CON5 1 2 3 4 5 6 7 8 9 10 1112 1314 R65 150R R101 150R R173 100R AN_GND ( adjacent neibourhood board ground ) D C B A Company : KIP Uni-Heidelberg / Lindenstruth Editor : Dirk Gottschalk Title DCS JTAG Interface Size Document Number Rev A3 03 1.62 5 4 3 2 Date: 2005.02.18 13:40 Sheet 3 of 14 1
- Page 1: 5 4 3 2 1 Power Input D ADC Inputs
- Page 5 and 6: 5 4 3 2 1 D C GND layer trace to po
- Page 7 and 8: 5 4 3 2 1 D D 3V3 3V3 C182 100n CON
- Page 9 and 10: 5 4 3 2 1 R144 51R C237 47n CON2 3V
- Page 11 and 12: 5 5 4 4 3 3 2 2 1 1 D D C C B B A A
- Page 13 and 14: 5 4 3 2 1 D PLL Configuration Table
5<br />
4<br />
3<br />
2<br />
1<br />
D<br />
D<br />
C<br />
C<br />
SDQ[15:0]<br />
B20<br />
C20<br />
F18<br />
C21<br />
E20<br />
F19<br />
F20<br />
G18<br />
H19<br />
G20<br />
E22<br />
H18<br />
G21<br />
H20<br />
H17<br />
H22<br />
SDQ0<br />
SDQ1<br />
SDQ2<br />
SDQ3<br />
SDQ4<br />
SDQ5<br />
SDQ6<br />
SDQ7<br />
SDQ8<br />
SDQ9<br />
SDQ10<br />
SDQ11<br />
SDQ12<br />
SDQ13<br />
SDQ14<br />
SDQ15<br />
MT48LC16M16_TSOP54<br />
IC5<br />
B<br />
B13<br />
G13<br />
D13<br />
A15<br />
F13<br />
C13<br />
E13<br />
D14<br />
DQM-ECC<br />
DQS-ECC<br />
DQ-ECC0<br />
DQ-ECC1<br />
DQ-ECC2<br />
DQ-ECC3<br />
DQ-ECC4<br />
DQ-ECC5<br />
DQ0<br />
DQ1<br />
DQ2<br />
DQ3<br />
DQ4<br />
DQ5<br />
DQ6<br />
DQ7<br />
DQ8<br />
DQ9<br />
DQ10<br />
DQ11<br />
DQ12<br />
DQ13<br />
DQ14<br />
DQ15<br />
IC1B<br />
<strong>EPXA1F484C3</strong><br />
SDRAM Interface<br />
SDRAM Interface pins are not<br />
available as user I/Os!<br />
These pins are reserved<br />
for future functionallity<br />
and should be left<br />
unconnected<br />
SDA0<br />
SDA1<br />
SDA2<br />
SDA3<br />
SDA4<br />
SDA5<br />
SDA6<br />
SDA7<br />
SDA8<br />
SDA9<br />
SDA10<br />
SDA11<br />
SDA12<br />
SDA13-BA0<br />
SDA14-BA1<br />
CLK<br />
CLKn<br />
CASn<br />
CLKE<br />
RAS<br />
WEn<br />
DQM0<br />
DQM1<br />
CS-N0<br />
CS-N1<br />
DQS0<br />
DQS1<br />
DDR-VS0<br />
DDR-VS1<br />
DDR-VS2<br />
B17<br />
G16<br />
D16<br />
F16<br />
A19<br />
E16<br />
B18<br />
F17<br />
C17<br />
D17<br />
B19<br />
D18<br />
D19<br />
C19<br />
E18<br />
C15<br />
J16<br />
A17<br />
E15<br />
C14<br />
F14<br />
E21<br />
J20<br />
G15<br />
B16<br />
D22<br />
J17<br />
D21<br />
G22<br />
B15<br />
R8<br />
10k<br />
R7<br />
10k<br />
3V3<br />
RN20<br />
4x330R<br />
SDR_CLK<br />
SDR_SDR_<br />
SDR_CKE<br />
SDR_RAS<br />
SDR_WE<br />
SDR_DQML<br />
SDR_DQMH<br />
SDR_CS<br />
RN32<br />
4x330R<br />
8<br />
7<br />
6<br />
5<br />
1<br />
2<br />
3<br />
4<br />
8<br />
7<br />
6<br />
5<br />
1<br />
2<br />
3<br />
4<br />
8<br />
7<br />
6<br />
5<br />
1<br />
2<br />
3<br />
4<br />
8<br />
7<br />
6<br />
5<br />
1<br />
2<br />
3<br />
4<br />
3V3<br />
RN21<br />
4x330R<br />
RN38<br />
4x330R<br />
3V3<br />
23<br />
24<br />
25<br />
26<br />
29<br />
30<br />
31<br />
32<br />
33<br />
34<br />
22<br />
35<br />
36<br />
20<br />
21<br />
38<br />
17<br />
37<br />
15<br />
39<br />
18<br />
16<br />
19<br />
1<br />
14<br />
27<br />
3<br />
9<br />
43<br />
49<br />
6<br />
12<br />
46<br />
52<br />
A0<br />
A1<br />
A2<br />
A3<br />
A4<br />
A5<br />
A6<br />
A7<br />
A8<br />
A9<br />
A10<br />
A11<br />
A12<br />
BA0<br />
BA1<br />
CLK<br />
CAS<br />
CKE<br />
DQML<br />
DQMH<br />
RAS<br />
WE<br />
CS<br />
VDD1<br />
VDD2<br />
VDD3<br />
VDDQ1<br />
VDDQ2<br />
VDDQ3<br />
VDDQ4<br />
VSSQ1<br />
VSSQ2<br />
VSSQ3<br />
VSSQ4<br />
DQ0<br />
2<br />
DQ1<br />
4<br />
DQ2<br />
5<br />
7<br />
DQ3<br />
8<br />
DQ4<br />
DQ5<br />
10<br />
DQ6<br />
11<br />
DQ7<br />
13<br />
DQ8<br />
42<br />
44<br />
DQ9<br />
DQ10<br />
45<br />
DQ11<br />
47<br />
DQ12<br />
48<br />
DQ13<br />
50<br />
51<br />
DQ14<br />
53<br />
DQ15<br />
GND1<br />
GND2<br />
GND3<br />
28<br />
41<br />
54<br />
NC 40<br />
SDQ0<br />
SDQ1<br />
SDQ2<br />
SDQ3<br />
SDQ4<br />
SDQ5<br />
SDQ6<br />
SDQ7<br />
SDQ8<br />
SDQ9<br />
SDQ10<br />
SDQ11<br />
SDQ12<br />
SDQ13<br />
SDQ14<br />
SDQ15<br />
GND<br />
B<br />
A<br />
3V3<br />
C15<br />
C13<br />
C12<br />
C94<br />
C91<br />
C9<br />
C10<br />
C16<br />
A<br />
10n<br />
47n<br />
10n<br />
47n<br />
10n<br />
47n<br />
10n<br />
47n<br />
Company : KIP Uni-Heidelberg / Lindenstruth<br />
Editor : Dirk Gottschalk<br />
Title<br />
DCS SDRAM Interface<br />
Size Document Number Rev<br />
A3<br />
02 1.60<br />
Date: 2003.12.19 14:00<br />
Sheet 2 of<br />
14<br />
5<br />
4<br />
3<br />
2<br />
1
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