ADC JTAG I/O Intel LXT971ALC Ethernet Phy Altera EPXA1F484C3 ...
ADC JTAG I/O Intel LXT971ALC Ethernet Phy Altera EPXA1F484C3 ... ADC JTAG I/O Intel LXT971ALC Ethernet Phy Altera EPXA1F484C3 ...
5 4 3 2 1 Routing Hints for the DCS Board D Place 10nF and 100nF capacitors as close as possible to the devices. Place power vias as close as possible to the related decoupling capacitors not to the related device. This may not allways work with BGAs but should work with all non BGA packages. See picture. wrong via* via* device via* via* okay D *via to supply or GND planes Grounding scheme for PLL, TTCrx and 120MHz LVDS driver C QOsc 40MHz PLL 3V3 Vreg C PLL_GND MUX1 PLL LVDS driver PLL_GND R124 B B Board_GND TTCrx Optical Link Receiver A A Wednesday 2003.12.17 10:10 Editor : Dirk Gottschalk Title DCS Board Routing Hints Size Document Number Rev A4 12 1.60 5 4 3 Date: 2003.12.17 13:30 Sheet 12 of 14 2 1
5 4 3 2 1 D PLL Configuration Table for TPC and TRD D TRD TPC default frequency 120 MHz 40 MHz R68 no device 10k R99 0R_Jmpr no device R100 no device no device R105 no device no device R107 0R_Jmpr no device C R108 no device 10k C R109 0R_Jmpr 10k R110 0R_Jmpr 10k RN48 no device 4x0R_Jmpr B B A Company : KIP Uni-Heidelberg / Lindenstruth Editor : Dirk Gottschalk A Title PLL Clock Configuration Size Document Number Rev A4 13 1.61 5 4 3 Date: 2005.05.02 10:00 Sheet 13 of 14 2 1
- Page 1 and 2: 5 4 3 2 1 Power Input D ADC Inputs
- Page 3 and 4: 5 4 3 2 1 D C B A MTDIp MTDIn conne
- Page 5 and 6: 5 4 3 2 1 D C GND layer trace to po
- Page 7 and 8: 5 4 3 2 1 D D 3V3 3V3 C182 100n CON
- Page 9 and 10: 5 4 3 2 1 R144 51R C237 47n CON2 3V
- Page 11: 5 5 4 4 3 3 2 2 1 1 D D C C B B A A
5<br />
4<br />
3<br />
2<br />
1<br />
Routing Hints for the DCS Board<br />
D<br />
Place 10nF and 100nF capacitors as close as possible<br />
to the devices. Place power vias as close as possible to<br />
the related decoupling capacitors not to the related<br />
device. This may not allways work with BGAs but should<br />
work with all non BGA packages. See picture.<br />
wrong<br />
via*<br />
via*<br />
device<br />
via*<br />
via*<br />
okay<br />
D<br />
*via to supply or GND planes<br />
Grounding scheme for PLL, TTCrx and 120MHz LVDS driver<br />
C<br />
QOsc<br />
40MHz<br />
PLL 3V3<br />
Vreg<br />
C<br />
PLL_GND<br />
MUX1 PLL LVDS<br />
driver<br />
PLL_GND<br />
R124<br />
B<br />
B<br />
Board_GND<br />
TTCrx<br />
Optical Link<br />
Receiver<br />
A<br />
A<br />
Wednesday 2003.12.17 10:10<br />
Editor : Dirk Gottschalk<br />
Title<br />
DCS Board Routing Hints<br />
Size Document Number Rev<br />
A4<br />
12 1.60<br />
5<br />
4<br />
3<br />
Date: 2003.12.17 13:30<br />
Sheet 12 of<br />
14<br />
2<br />
1
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