D-Series Syringe Pumps - Isco

D Series Syringe Pumps
Section 4 Theory of Operation
provides hysteresis to insure the reset signal switches without
bouncing. The calibrated switching point is the low to high transition
which occurs when the +5 volt supply exceeds 4.875 volts.
The front panel ON/STANDBY switch also exerts control over
the reset circuit. In normal operation with the reset signal high,
transistor Q101 is turned on. When the front panel switch is
changed to STANDBY, it is designed to switch the reset signal
low, halting the microprocessor after a delay, sufficient enough to
allow saving microprocessor RAM information in the external
non-volatile RAM. When pin 3 of P105 switches high, an
interrupt routine is activated by pin 15 of U104 which initiates
the transfer. With pin 3 of P105 at 5 volts and Q101 turned on, 5
volts is placed across R101. This creates in effect a hardware
“request to reset.” When pin 3 of U101 goes high, pin 7 will be
pulled low activating the reset and turning off Q101. Anything
which pulls the reset signal low will release the Q101 “latch” and
accomplish this. The microprocessor has the ability to internally
pull the reset signal low which is done after all necessary variables
have been transferred to the external SRAM and the
display has been cleared. The reset signal will then remain low
until the front panel switch is set to ON and the +5 volt supply is
greater than 4.875 volts. The active low reset signal is inverted
by U127 to provide an active high reset signal for U129, U123,
and U128.
Keypad Scan Circuit
Display
The front panel keypad is scanned by the microprocessor at a
rate of one row per millisecond. Each row of the keypad driver
outputs of U128 is sequentially set high, followed by a read of the
columns which are normally pulled low by R104. The keypad is
debounced by software time delay.
The four line LCD display is connected to the 8-bit wide bus to
allow the microprocessor to output display information and read
back display status information. Additional control signals are
needed for the interface and are provided by U128. The display
read/write (D-R/W) signal is active high for a read cycle and low
for a write to the display. The display register select (D-RS) controls
data flow in the display controller. A read or write is signaled
by a momentary low to high pulse on one of the two display
enable signals (DISP EN1 and DISP EN2), which control the
upper and lower half of the display, respectively. The upper half
of the display is decoded in address space as chip select 10 (CS10)
and the lower two lines by chip select 11 (CS11).
The display viewing angle adjustment is under software control
and may be selected by pressing the MENU key. The adjustment
is made by varying the voltage at pin 6 of P104. The HSO.1 pin of
the microprocessor outputs a pulse width modulated signal
which drives the gate of MOSFET Q103. The resulting pulse
signal is filtered by R122 and C139 to drive the display. R123
provides a minimal current to prevent the display from being
turned completely off.
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