D-Series Syringe Pumps - Isco

D Series Syringe Pumps
Section 4 Theory of Operation
only by the pump connected to the PUMP A connector on the rear
panel. For this reason, care should be taken to remove mains
power before connecting or disconnecting the pumps from the
rear panel of the controller.
The supplies required are +5 volts for the digital circuitry and
±15 volts for the analog interface circuitry. Other supplies
derived from these, using zener diode circuits are ±11 volt supplies
for the RS-232 serial interface driver, U107, ±5.2 volt supplies
for the analog to digital (A/D) converter, U129, +12 volts for
the analog input interface and multiplexer U130, and -3 volts for
the analog input interface circuit.
The A/D converter voltage reference VREF, is generated from the
+15 volt supply by U133, with R135 as the adjustment. See
section 5.11.5 for the adjustment procedure. Battery BT101
maintains the static RAM memory for one month without power
to the pump if fully charged. The battery charging circuit uses
diodes CR101 and CR102 to direct power to the memory chips
U105 and U106 for memory retention and for normal operation
(charging). The unregulated supply to the +5 volt regulator in the
pump is brought to the controller for the purpose of monitoring
the transformer secondary. This voltage labeled +10 volts at
TP112, is divided by R120 and R121 and monitored by the
internal microprocessor A/D converter. When the supply begins
to drop (as in a power failure), the microprocessor detects the
drop with enough time to save operating conditions and execute a
graceful shutdown.
Microprocessor and Memory
Microprocessor Reset Circuit
The heart of the controller is the INTEL 80C196 embedded
microprocessor U104. The operating code (or firmware) is contained
as 16-bit wide information split into two 8-bit EPROMs
U102 (low byte) and U103 (high byte). Some static RAM (SRAM)
is built into the microprocessor but the bulk is provided by
battery backed SRAMs U105 (low byte) and U106 (high byte)
also as split 16 bit wide information. The microprocessor bus
functions as a zero wait state 16 bit wide bus or as a slower 3
wait state 8- bit wide bus. The selection is under the control of
the chip select or address decoding circuit. The wait state generation
is internal to the processor. All peripheral chips other than
the RAM and ROM, are operated on the slower 8-bit bus, which
is buffered through U108, a bi-directional buffer. The microprocessor
is designed to address a 64-Kilobyte space. To access more
code memory, this system utilizes a paged memory method which
allows access to 512 K bytes of code memory (with 27C020s
installed), in addition to the 16 K of SRAM. The additional
address bits are output through U112, a programmable logic
device.
The microprocessor reset signal is generated by voltage monitor
circuit U101. The microprocessor has an internal pull-up on the
active low reset signal. The open drain output at pin 7 pulls the
reset signal low when the +5 volt supply drops below about 4.75
volts. Refer to section 5.11.1 for calibration instructions. R108
4-2