Application Note AN-1077 - International Rectifier

Application Note AN-1077
VOLTAGE FEEDBACK LOOP
vˆ
o
VIN
îchg
r =
RL
C O
RL
d
POWER STAGE
G(s)
VO
Figure 11 - Small Signal low frequency model
for the boost power stage
OCC Modulator
H3(s)
vm
VREF
ERROR
AMPLIFIER
H2(s)
VFB
Figure 10 - Voltage Loop
Output Divider
H1(s)
The open loop gain is given by the product:
T
1 2
⋅
3
( s ) = G( s ) ⋅ H ( s ) ⋅ H ( s ) H ( s ) (25)
OUTPUT DIVIDER: ( s )
H 1
The output divider scales the output voltage to be
compared with the reference voltage in the error amplifier.
Therefore:
V
OUT
( RFB
1
+ RFB2
+ RFB3)
VREF
= (26)
R
V
H ( s ) =
FB3
REF
1
(27)
Vo
This stage simply attenuates the output voltage
signal, by a fixed amount:
H = 0.
018 = 34.
8dB
1
−
POWER STAGE: H ( s ) ⋅G(
s )
The low frequency small signal equivalent circuit
for the boost power stage is shown in Figure 11. An
explanation of this model can be found in [7][8].
3
Definitions:
R
L
: Load Resistance
C
O : Output (bulk) capacitor
vˆ
m
: Modulation Voltage – this is the output of the Voltage
Error Amplifier
G
DC
: DC gain of the current amplifier – it is set internally
the IC at 2.5V/V
V : Peak value of input voltage (i.e. ⋅ 2
in
V )
inRMS max
For a constant power load the actual RL is negative.
This is the typical case when the PFC load is a
DC-DC stage: if the input voltage of that stage is reduced
it will react by increasing the current, in order to
maintain the output power constant.
In this case R L will cancel with r and will yield:
vˆ
o
1
= (28)
î sC
chg
When a purely resistive load is present we have:
vˆ
î
o
chg
o
RL
/ 2
= (29)
RL
1+
sCo
2
We will not consider the resistive load case here,
since in the majority of cases the PFC load is the input
of another DC-DC converter.
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