IRFP4568PBF Datasheet

PD -96175
IRFP4568PbF
Applications
l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency Circuits
Benefits
l Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
l Fully Characterized Capacitance and Avalanche
SOA
l Enhanced body diode dV/dt and dI/dt Capability
l Lead-Free
G
D
S
V DSS
HEXFET ® Power MOSFET
150V
R DS(on) typ.
max.
4.8m:
5.9m:
I D (Silicon Limited) 171
D
S
D
G
TO-247AC
IRFP4568PbF
G D S
Gate Drain Source
Absolute Maximum Ratings
Symbol Parameter Max.
Units
I D @ T C = 25°C Continuous Drain Current, V GS @ 10V (Silicon Limited)
171
I D @ T C = 100°C Continuous Drain Current, V GS @ 10V (Silicon Limited)
121
A
I DM
Pulsed Drain Current c
684
P D @T C = 25°C Maximum Power Dissipation 517
W
Linear Derating Factor
3.45
W/°C
V GS Gate-to-Source Voltage ± 30
V
dv/dt Peak Diode Recovery e 18.5
V/ns
T J
Operating Junction and
-55 to + 175
T STG
Storage Temperature Range
Soldering Temperature, for 10 seconds
300
°C
(1.6mm from case)
Mounting torque, 6-32 or M3 screw
10lbxin (1.1Nxm)
Avalanche Characteristics
E AS (Thermally limited)
Single Pulse Avalanche Energy d 763
mJ
I AR
Avalanche Currentc See Fig. 14, 15, 22a, 22b,
A
E AR
Repetitive Avalanche Energy f mJ
Thermal Resistance
Symbol Parameter Typ. Max. Units
R θJC Junction-to-Case j ––– 0.29
R θCS Case-to-Sink, Flat Greased Surface 0.24 –––
R θJA Junction-to-Ambient ij ––– 40
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°C/W
09/08/08

IRFP4568PbF
Static @ T J = 25°C (unless otherwise specified)
Symbol Parameter Min. Typ. Max. Units
V (BR)DSS Drain-to-Source Breakdown Voltage 150 ––– ––– V
∆V (BR)DSS /∆T J Breakdown Voltage Temp. Coefficient ––– 0.17 ––– V/°C
R DS(on) Static Drain-to-Source On-Resistance ––– 4.8 5.9 mΩ
V GS(th) Gate Threshold Voltage 3.0 ––– 5.0 V
I DSS
I GSS
Drain-to-Source Leakage Current
Gate-to-Source Forward Leakage
–––
–––
–––
–––
20
100
Gate-to-Source Reverse Leakage
–––
–––
–––
–––
250
-100
µA
nA
R G Internal Gate Resistance ––– 1.0 ––– Ω
Dynamic @ T J = 25°C (unless otherwise specified)
Symbol Parameter Min. Typ. Max. Units
Conditions
gfs Forward Transconductance 162 ––– ––– S V DS = 50V, I D = 103A
Q g Total Gate Charge ––– 151 227 I D = 103A
Q gs Gate-to-Source Charge ––– 52 –––
Q gd Gate-to-Drain ("Miller") Charge ––– 55 –––
Q sync Total Gate Charge Sync. (Q g - Q gd ) ––– 96 –––
t d(on) Turn-On Delay Time ––– 27 –––
t r Rise Time ––– 119 –––
t d(off) Turn-Off Delay Time ––– 47 –––
t f Fall Time ––– 84 –––
C iss Input Capacitance ––– 10470 –––
C oss Output Capacitance ––– 977 –––
C rss Reverse Transfer Capacitance ––– 203 –––
C oss eff. (ER) Effective Output Capacitance (Energy Related) h ––– 897 –––
C oss eff. (TR) Effective Output Capacitance (Time Related)g ––– 1272 –––
Diode Characteristics
Symbol Parameter Min. Typ. Max. Units
Conditions
I S
Continuous Source Current
MOSFET symbol
D
––– ––– 171 A
(Body Diode)
showing the
I SM
Pulsed Source Current
integral reverse
G
––– ––– 684 A
(Body Diode)c
S
p-n junction diode.
V SD Diode Forward Voltage ––– ––– 1.3 V T J = 25°C, I S = 103A, V GS = 0V f
t rr Reverse Recovery Time ––– 110 ––– T J = 25°C V R = 100V,
ns
––– 133 ––– T J = 125°C I F = 103A
Q rr Reverse Recovery Charge ––– 515 ––– T J = 25°C di/dt = 100A/µs f
nC
––– 758 ––– T J = 125°C
I RRM Reverse Recovery Current ––– 8.8 ––– A T J = 25°C
t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
nC
ns
pF
Conditions
V GS = 0V, I D = 250µA
Reference to 25°C, I D = 5mAc
V GS = 10V, I D = 103A f
V DS = V GS , I D = 250µA
V DS =150V, V GS = 0V
V DS = 150V, V GS = 0V, T J = 125°C
V GS = 20V
V GS = -20V
V DS = 75V
V GS = 10V f
I D = 103A, V DS =0V, V GS = 10V f
V DD = 98V
I D =103A
R G =1.0Ω
V GS = 10V f
V GS = 0V
V DS = 50V
ƒ = 1.0MHz, (See Fig 5)
V GS = 0V, V DS = 0V to 120V h(SeeFig.11)
V GS = 0V, V DS = 0V to 120V g
Notes:
Repetitive rating; pulse width limited by max. junction
temperature.
‚ Limited by T Jmax , starting T J = 25°C, L = 0.144mH
R G = 25Ω, I AS = 103A, V GS =10V. Part not recommended for use
above this value.
ƒ I SD ≤ 103A, di/dt ≤ 360A/µs, V DD ≤ V (BR)DSS , T J ≤ 175°C.
„ Pulse width ≤ 400µs; duty cycle ≤ 2%.
… C oss eff. (TR) is a fixed capacitance that gives the same charging time
as C oss while V DS is rising from 0 to 80% V DSS .
† C oss eff. (ER) is a fixed capacitance that gives the same energy as
C oss while V DS is rising from 0 to 80% V DSS .
‡ When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
mended footprint and soldering techniques refer to application note #AN-994.
ˆ R θ is measured at T J approximately 90°C.
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C, Capacitance (pF)
I D , Drain-to-Source Current (A)
I D , Drain-to-Source Current (A)
V GS , Gate-to-Source Voltage (V)
R DS(on) , Drain-to-Source On Resistance
I D , Drain-to-Source Current (A)
(Normalized)
IRFP4568PbF
1000
100
10
VGS
TOP 15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
1000
100
VGS
TOP 15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
1
0.1
≤60µs PULSE WIDTH
Tj = 25°C
4.5V
0.01
0.1 1 10 100
V DS , Drain-to-Source Voltage (V)
10
4.5V
≤60µs PULSE WIDTH
Tj = 175°C
1
0.1 1 10 100
V DS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
100
T J = 175°C
3.0
2.5
I D = 103A
V GS = 10V
10
T J = 25°C
2.0
1.5
1
V DS = 50V
≤60µs PULSE WIDTH
0.1
3 4 5 6 7 8 9
V GS , Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
1.0
0.5
-60 -40 -20 0 20 40 60 80 100120140160180
T J , Junction Temperature (°C)
Fig 4. Normalized On-Resistance vs. Temperature
1000000
100000
10000
V GS = 0V, f = 1 MHZ
C iss
= C gs
+ C gd
, C ds
SHORTED
C rss
= C gd
C oss
= C ds
+ C gd
C iss
0 50 100 150 200
14.0
12.0
10.0
8.0
I D = 103A
V DS = 120V
V DS = 75V
VDS= 30V
1000
100
C oss
C rss
6.0
4.0
2.0
10
0.0
1 10 100 1000
V DS , Drain-to-Source Voltage (V)
Q G , Total Gate Charge (nC)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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Drain Current (A)
I D ,
I SD , Reverse Drain Current (A)
Energy (µJ)
E AS , Single Pulse Avalanche Energy (mJ)
I D , Drain-to-Source Current (A)
Drain-to-Source Breakdown Voltage (V)
V (BR)DSS ,
IRFP4568PbF
1000
100
T J = 175°C
T J = 25°C
10000
1000
100
OPERATION IN THIS AREA
LIMITED BY R DS (on)
100µsec
1msec
10
DC
10
10msec
V GS = 0V
1
Tc = 25°C
Tj = 175°C
Single Pulse
1.0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
V SD , Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
0.1
0.1 1 10 100 1000
V DS , Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
180
160
190
185
Id = 5mA
140
120
100
80
60
180
175
170
165
160
155
40
150
20
145
12.0
10.0
0
25 50 75 100 125 150 175
T C , Case Temperature (°C)
Fig 9. Maximum Drain Current vs.
Case Temperature
8.0
6.0
140
-60 -40 -20 0 20 40 60 80 100120140160180
3500
3000
2500
2000
1500
T J , Temperature ( °C )
Fig 10. Drain-to-Source Breakdown Voltage
I D
TOP 21.5A
29.3A
BOTTOM 103A
4.0
2.0
1000
500
0.0
0 20 40 60 80 100 120 140 160
V DS, Drain-to-Source Voltage (V)
0
25 50 75 100 125 150 175
Starting T J , Junction Temperature (°C)
Fig 11. Typical C OSS Stored Energy
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
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E AR , Avalanche Energy (mJ)
Avalanche Current (A)
IRFP4568PbF
1
Thermal Response ( Z thJC ) °C/W
0.1
0.01
0.001
D = 0.50
0.20
0.10
0.05
0.02
0.01
SINGLE PULSE
( THERMAL RESPONSE )
τ J
τ J
τ 1 τ
τ 2 τ 3
1
τ 2 τ 3
Ci= τi/Ri
Ci i/Ri
R 1 R 2 R 3
R 1 R 2 R 3
0.0001
1E-006 1E-005 0.0001 0.001 0.01 0.1
t 1 , Rectangular Pulse Duration (sec)
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
τ C
τ
Ri (°C/W) τi (sec)
0.06336 0.000278
0.11088 0.005836
0.11484 0.053606
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
1000
100
Duty Cycle = Single Pulse
0.01
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Tj = 150°C and
Tstart =25°C (Single Pulse)
10
0.05
0.10
1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Τj = 25°C and
Tstart = 150°C.
0.1
1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
900
800
700
600
500
400
300
200
100
TOP Single Pulse
BOTTOM 1.0% Duty Cycle
I D = 103A
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of T jmax . This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asT jmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. P D (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. I av = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed T jmax (assumed as
25°C in Figure 14, 15).
t av = Average time in avalanche.
D = Duty cycle in avalanche = t av ·f
Z thJC (D, t av ) = Transient thermal resistance, see Figures 13)
0
25 50 75 100 125 150 175
Starting T J , Junction Temperature (°C)
Fig 15. Maximum Avalanche Energy vs. Temperature
P D (ave) = 1/2 ( 1.3·BV·I av ) = DT/ Z thJC
I av = 2DT/ [1.3·BV·Z th ]
E AS (AR) = P D (ave)·t av
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Gate threshold Voltage (V)
V GS(th) ,
I RR (A)
Q RR (A)
Q RR (A)
I RR (A)
IRFP4568PbF
6.0
5.5
5.0
4.5
4.0
60
50
40
I F = 68A
V R = 100V
T J = 25°C
T J = 125°C
3.5
30
3.0
2.5
2.0
1.5
I D = 250µA
I D = 1.0mA
ID = 1.0A
20
10
1.0
-75 -50 -25 0 25 50 75 100 125 150 175
T J , Temperature ( °C )
Fig 16. Threshold Voltage vs. Temperature
0
0 200 400 600 800 1000
di F /dt (A/µs)
Fig. 17 - Typical Recovery Current vs. di f /dt
70
60
50
40
I F = 103A
V R = 100V
T J = 25°C
T J = 125°C
3600
3200
2800
2400
I F = 68A
V R = 100V
T J = 25°C
T J = 125°C
30
20
2000
1600
1200
10
800
0
0 200 400 600 800 1000
di F /dt (A/µs)
Fig. 18 - Typical Recovery Current vs. di f /dt
400
0 200 400 600 800 1000
di F /dt (A/µs)
Fig. 19 - Typical Stored Charge vs. di f /dt
4000
3600
3200
2800
I F = 103A
V R = 100V
T J = 25°C
T J = 125°C
2400
2000
1600
1200
800
400
0 200 400 600 800 1000
di F /dt (A/µs)
Fig. 20 - Typical Stored Charge vs. di f /dt
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IRFP4568PbF
+
‚
-
D.U.T
+
ƒ
-
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
„
+
Reverse
Recovery
Current
Driver Gate Drive
Period
P.W.
D.U.T. I SD Waveform
Body Diode Forward
Current
di/dt
D.U.T. V DS Waveform
Diode Recovery
dv/dt
D =
P.W.
Period
V GS =10V
V DD
*
R G
• dv/dt controlled by RG
• Driver same type as D.U.T.
• I SD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
V DD
+
-
Re-Applied
Voltage
Body Diode
Inductor Curent Current
Forward Drop
Ripple ≤ 5%
I SD
* V GS = 5V for Logic Level Devices
Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET ® Power MOSFETs
15V
tp
V (BR)DSS
L
DRIVER
R G
20V V GS
tp
V DS
+
D.U.T
IAS
0.01Ω
- V DD
A
I AS
Fig 22a. Unclamped Inductive Test Circuit
Fig 22b. Unclamped Inductive Waveforms
V DS
R D
V DS
V GS
D.U.T.
90%
R G
+
-
V DD
V10V
GS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
10%
V GS
t d(on) t r t d(off) t f
Fig 23a. Switching Time Test Circuit
Fig 23b. Switching Time Waveforms
Current Regulator
Same Type as D.U.T.
Vds
Id
50KΩ
Vgs
12V
.2µF
.3µF
V GS
D.U.T.
+
V
- DS
Vgs(th)
3mA
I G I D
Current Sampling Resistors
Qgs1 Qgs2 Qgd Qgodr
Fig 24a. Gate Charge Test Circuit
Fig 24b. Gate Charge Waveform
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IRFP4568PbF
TO-247AC Package Outline
Dimensions are shown in millimeters (inches)
TO-247AC Part Marking Information
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TO-247AC package is not recommended for Surface Mount Application.
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 09/2008
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