PCIe Devices - PLX Technology
PCIe Devices - PLX Technology
PCIe Devices - PLX Technology
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Address Method and TLP Headers<br />
n<br />
The following address methods are allowed<br />
l<br />
Memory reads and writes<br />
– Uses 1 or 2 DW defining address (32-bit or 64-bit)<br />
• Mapped to system memory resources<br />
l<br />
I/O reads and writes<br />
– Uses 1 DW defining I/O address (32-bit I/O addressing<br />
only)<br />
• Mapped to system I/O resources (1 DW payload)<br />
l<br />
Configuration reads and writes<br />
– Uses 1 DW defining targeted bus, device, function<br />
number, and DW location in devices configuration space<br />
Copyright by Dashcourses, Inc. 2009<br />
l<br />
Implicit<br />
– Destination address defined in the command<br />
2-80
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