PCIe Devices - PLX Technology
PCIe Devices - PLX Technology
PCIe Devices - PLX Technology
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<strong>PCIe</strong> Link Attributes (continued)<br />
n<br />
Key design attributes for a <strong>PCIe</strong> Link are:<br />
l<br />
l<br />
Lanes<br />
– A Link must support at least one Lane<br />
• Each Lane represents a set of differential signal pairs (Transmit<br />
and Receive)<br />
– A Link may aggregate multiple Lanes denoted by xN<br />
• Currently supported values of N are<br />
– x1, x2, x4, x8, x12, x16, and x32<br />
– A maximum of 80/160 Gbps of raw bandwidth in each<br />
direction<br />
Initialization<br />
– Link initialized in hardware (no firmware or OS software)<br />
– Link set up follows a negotiation of Lane widths and frequency<br />
of operation by agents embedded at each end of the Link<br />
l<br />
Symmetry<br />
– Each Link must support a symmetric number of Lanes in each<br />
direction<br />
Copyright by Dashcourses, Inc. 2009<br />
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