PCIe Devices - PLX Technology
PCIe Devices - PLX Technology
PCIe Devices - PLX Technology
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<strong>PCIe</strong> Dual Simplex x1 Link<br />
<strong>PCIe</strong> Device<br />
<strong>PCIe</strong> Device<br />
Tx<br />
D+<br />
D+<br />
Rx<br />
D-<br />
D-<br />
To/from <strong>PCIe</strong> device<br />
Physical Layer 8B/10B<br />
encoding/decoding logic<br />
To/from <strong>PCIe</strong> device<br />
Physical Layer 8B/10B<br />
encoding/decoding logic<br />
Rx<br />
D+<br />
D-<br />
D+<br />
D-<br />
Tx<br />
n<br />
Transmitters drive, and receivers must detect a 0.8 to<br />
1.2 V peak-to-peak signal when driven into a 50 ohm load<br />
l<br />
l<br />
Copyright by Dashcourses, Inc. 2009<br />
Each dual-simplex pair form a x1, 2.5 or 5 GT/s, connection referred to as<br />
a Lane<br />
<strong>PCIe</strong> Links are composed of one or more Lanes, each Lane<br />
1-54