PCIe Devices - PLX Technology
PCIe Devices - PLX Technology PCIe Devices - PLX Technology
PCIe Traffic Differentiation n Separate data flows can be assigned different TC/VC combinations l If priorities are assigned, switch arbitration rules are handled on a per VC basis PCIe Device PCIe Link PCIe Device VC0/TC0 Packets VC0/TC0 Packets VC1/TC1 Packets VC0/TC0 Packets VC1/TC1 Packets VC0/TC0 Packets VC1/TC1 Packets VC1/TC1 Packets Copyright by Dashcourses, Inc. 2009 1-44
PCIe Root Complex n A Root Complex (RC) denotes the root of an I/O hierarchy that connects a CPU/memory subsystem to the I/O subsystem 1 l A Root Port is a virtual PCI/PCI bridge that originates a PCIe Hierarchy domain from a Root Complex 1 In PCI this would be the ‘host/PCI’ bus bridge providing access to bus 0 Copyright by Dashcourses, Inc. 2009 1-45
- Page 1 and 2: Presents PCI Express Overview By Pa
- Page 3 and 4: What This Presentation Is About n T
- Page 5 and 6: Specifications n The current PCIe s
- Page 7 and 8: Presentation Layout Section 1 - PCI
- Page 9 and 10: PCI Specification History n n n PCI
- Page 11 and 12: PCIe Compatibility and New Features
- Page 13 and 14: PCIe Interconnect - Chip-to-Board C
- Page 15 and 16: PCIe Design Possibilities Embedded
- Page 17 and 18: Compatibility with Existing PCI Spe
- Page 19 and 20: New Features n Improved data integr
- Page 21 and 22: Scalable Topologies n Hierarchies u
- Page 23 and 24: PCI and PCI-X Architecture and Comm
- Page 25 and 26: PCIe Command Execution Host System
- Page 27 and 28: PCIe Transactions and Packets n PCI
- Page 29 and 30: PCI Devices n n n PCI is based on a
- Page 31 and 32: PCI Topology with Multiple Host/PCI
- Page 33 and 34: PCIe Device/Function PCIe Single Fu
- Page 35 and 36: PCIe System Fabric PCIe Root Comple
- Page 37 and 38: PCI/PCI-X/PCIe Bridges n Bridges ar
- Page 39 and 40: PCI/PCI-X Arbitration Example n n F
- Page 41 and 42: PCIe Processing and Priorities n PC
- Page 43: Mythical Example VC ID and Priority
- Page 47 and 48: PCIe Root Complex Model Host system
- Page 49 and 50: PCIe Switch Structure Upstream Port
- Page 51 and 52: PCIe Interrupts Host System Bus Whe
- Page 53 and 54: PCIe Link is a Point-to-Point Conne
- Page 55 and 56: PCIe Differential Drivers n PCIe de
- Page 57 and 58: PCIe Link Attributes (continued) n
- Page 59 and 60: PCIe Can be Aggregated n PCIe devic
- Page 61 and 62: MBps vs. Gbps?? n Comparing data ra
- Page 63 and 64: PCI Configuration Header Types n Fi
- Page 65 and 66: PCI Configuration Header Type 0 PCI
- Page 67 and 68: Host PCI Bridge Discovery n n n Acc
- Page 69 and 70: PCIe Primary/Secondary Bus Scheme P
- Page 71 and 72: Optional Registers (continued) Last
- Page 73 and 74: PCIe Configuration Space DWord 1000
- Page 75 and 76: Key Aspects of Transaction Layer n
- Page 77 and 78: PCIe Transactions n Software will t
- Page 79 and 80: Address Space and Transaction Type
- Page 81 and 82: TLP size Varies n TLP construction
- Page 83 and 84: PCIe Transaction Movement Host Syst
- Page 85 and 86: TLP Packet Components n TLP packets
- Page 87 and 88: TLP Receiver Processing n Received
- Page 89 and 90: Message Codes n Messages are define
- Page 91 and 92: Section 3 PCIe Data Link Layer Copy
- Page 93 and 94: Key Aspects of Data Link Layer n At
<strong>PCIe</strong> Traffic Differentiation<br />
n<br />
Separate data flows can be assigned different<br />
TC/VC combinations<br />
l<br />
If priorities are assigned, switch arbitration rules are<br />
handled on a per VC basis<br />
<strong>PCIe</strong> Device<br />
<strong>PCIe</strong> Link<br />
<strong>PCIe</strong> Device<br />
VC0/TC0 Packets<br />
VC0/TC0 Packets<br />
VC1/TC1 Packets<br />
VC0/TC0 Packets<br />
VC1/TC1 Packets<br />
VC0/TC0 Packets<br />
VC1/TC1 Packets<br />
VC1/TC1 Packets<br />
Copyright by Dashcourses, Inc. 2009<br />
1-44
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