PCIe Devices - PLX Technology
PCIe Devices - PLX Technology PCIe Devices - PLX Technology
PCI/PCI-X Device/Function PCI Single Function Device PCI Bus PCI Bus and Control Signals UART (Function) I/O PCI Multiple Function Device PCI Bus PCI Bus and Control Signals FDDI (Function) SCSI (Function) IDE Bus SCSI Bus Copyright by Dashcourses, Inc. 2009 1-30
PCI Topology with Multiple Host/PCI Bus Bridge Processor Processor Processor Bus=0 Subor=2 Host/PCI Bridge 1 Main Memory Host/PCI-X Bridge Bus=3 Subor=4 PCI Bus 0 PCI/PCI Bridge Pri=0 Sec=1 Subor=2 Pri=3 Sec=4 Subor=4 PCI-X/PCI-X Bridge PCI Bus 3 Pri=1 Sec=2 Subor=2 PCI/PCI Bridge PCI Bus 1 PCI Bus 4 PCI Bus 2 1 Only 1 Host/PCI bus numbered ‘0’. Initial starting point for bus enumeration. Copyright by Dashcourses, Inc. 2009 1-31
- Page 1 and 2: Presents PCI Express Overview By Pa
- Page 3 and 4: What This Presentation Is About n T
- Page 5 and 6: Specifications n The current PCIe s
- Page 7 and 8: Presentation Layout Section 1 - PCI
- Page 9 and 10: PCI Specification History n n n PCI
- Page 11 and 12: PCIe Compatibility and New Features
- Page 13 and 14: PCIe Interconnect - Chip-to-Board C
- Page 15 and 16: PCIe Design Possibilities Embedded
- Page 17 and 18: Compatibility with Existing PCI Spe
- Page 19 and 20: New Features n Improved data integr
- Page 21 and 22: Scalable Topologies n Hierarchies u
- Page 23 and 24: PCI and PCI-X Architecture and Comm
- Page 25 and 26: PCIe Command Execution Host System
- Page 27 and 28: PCIe Transactions and Packets n PCI
- Page 29: PCI Devices n n n PCI is based on a
- Page 33 and 34: PCIe Device/Function PCIe Single Fu
- Page 35 and 36: PCIe System Fabric PCIe Root Comple
- Page 37 and 38: PCI/PCI-X/PCIe Bridges n Bridges ar
- Page 39 and 40: PCI/PCI-X Arbitration Example n n F
- Page 41 and 42: PCIe Processing and Priorities n PC
- Page 43 and 44: Mythical Example VC ID and Priority
- Page 45 and 46: PCIe Root Complex n A Root Complex
- Page 47 and 48: PCIe Root Complex Model Host system
- Page 49 and 50: PCIe Switch Structure Upstream Port
- Page 51 and 52: PCIe Interrupts Host System Bus Whe
- Page 53 and 54: PCIe Link is a Point-to-Point Conne
- Page 55 and 56: PCIe Differential Drivers n PCIe de
- Page 57 and 58: PCIe Link Attributes (continued) n
- Page 59 and 60: PCIe Can be Aggregated n PCIe devic
- Page 61 and 62: MBps vs. Gbps?? n Comparing data ra
- Page 63 and 64: PCI Configuration Header Types n Fi
- Page 65 and 66: PCI Configuration Header Type 0 PCI
- Page 67 and 68: Host PCI Bridge Discovery n n n Acc
- Page 69 and 70: PCIe Primary/Secondary Bus Scheme P
- Page 71 and 72: Optional Registers (continued) Last
- Page 73 and 74: PCIe Configuration Space DWord 1000
- Page 75 and 76: Key Aspects of Transaction Layer n
- Page 77 and 78: PCIe Transactions n Software will t
- Page 79 and 80: Address Space and Transaction Type
PCI/PCI-X Device/Function<br />
PCI Single Function Device<br />
PCI Bus<br />
PCI Bus and<br />
Control Signals<br />
UART<br />
(Function)<br />
I/O<br />
PCI Multiple Function Device<br />
PCI Bus<br />
PCI Bus and<br />
Control Signals<br />
FDDI<br />
(Function)<br />
SCSI<br />
(Function)<br />
IDE Bus<br />
SCSI Bus<br />
Copyright by Dashcourses, Inc. 2009<br />
1-30
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