PCIe Devices - PLX Technology
PCIe Devices - PLX Technology PCIe Devices - PLX Technology
PCIe Packet Delineation or Framing n PCIe packets are detected or delineated at receiver by matching predefined symbols l l l Referred to as framing symbols Detection of predefined symbol sets determines where the first bit of the packet is and how the packet will be decoded – Received as a TLP or DLLP Beginning and ending packet symbols are required for all validated packets Physical/Data Link Header Transaction Layer Header Payload ECRC LCRC 11010110100100010101101001011010001011100010111010001011010010111101011101000101111001010000001011010110101 Device A PCIe Link Serial Packets Serial Packets Device B Packet Framing Symbols Copyright by Dashcourses, Inc. 2009 1-28
PCI Devices n n n PCI is based on a defined bus structure One or more PCI compliant devices attached to the PCI bus l Each PCI device may contain up to eight PCI functions – PCI function - a logical device • For example a sound card, a video card, or an IDE controller – Devices control 1-8 logical functions Devices may be a master or a target l l l Masters may initiate a bus transaction – Require a request/grant (REQ#/GNT#) pair wired to an arbiter for each master on the bus Targets may not initiate a bus transaction – Exception is a PCI-X target completing a split transaction response Devices attach to PCI busses by way of bridges Copyright by Dashcourses, Inc. 2009 1-29
- Page 1 and 2: Presents PCI Express Overview By Pa
- Page 3 and 4: What This Presentation Is About n T
- Page 5 and 6: Specifications n The current PCIe s
- Page 7 and 8: Presentation Layout Section 1 - PCI
- Page 9 and 10: PCI Specification History n n n PCI
- Page 11 and 12: PCIe Compatibility and New Features
- Page 13 and 14: PCIe Interconnect - Chip-to-Board C
- Page 15 and 16: PCIe Design Possibilities Embedded
- Page 17 and 18: Compatibility with Existing PCI Spe
- Page 19 and 20: New Features n Improved data integr
- Page 21 and 22: Scalable Topologies n Hierarchies u
- Page 23 and 24: PCI and PCI-X Architecture and Comm
- Page 25 and 26: PCIe Command Execution Host System
- Page 27: PCIe Transactions and Packets n PCI
- Page 31 and 32: PCI Topology with Multiple Host/PCI
- Page 33 and 34: PCIe Device/Function PCIe Single Fu
- Page 35 and 36: PCIe System Fabric PCIe Root Comple
- Page 37 and 38: PCI/PCI-X/PCIe Bridges n Bridges ar
- Page 39 and 40: PCI/PCI-X Arbitration Example n n F
- Page 41 and 42: PCIe Processing and Priorities n PC
- Page 43 and 44: Mythical Example VC ID and Priority
- Page 45 and 46: PCIe Root Complex n A Root Complex
- Page 47 and 48: PCIe Root Complex Model Host system
- Page 49 and 50: PCIe Switch Structure Upstream Port
- Page 51 and 52: PCIe Interrupts Host System Bus Whe
- Page 53 and 54: PCIe Link is a Point-to-Point Conne
- Page 55 and 56: PCIe Differential Drivers n PCIe de
- Page 57 and 58: PCIe Link Attributes (continued) n
- Page 59 and 60: PCIe Can be Aggregated n PCIe devic
- Page 61 and 62: MBps vs. Gbps?? n Comparing data ra
- Page 63 and 64: PCI Configuration Header Types n Fi
- Page 65 and 66: PCI Configuration Header Type 0 PCI
- Page 67 and 68: Host PCI Bridge Discovery n n n Acc
- Page 69 and 70: PCIe Primary/Secondary Bus Scheme P
- Page 71 and 72: Optional Registers (continued) Last
- Page 73 and 74: PCIe Configuration Space DWord 1000
- Page 75 and 76: Key Aspects of Transaction Layer n
- Page 77 and 78: PCIe Transactions n Software will t
PCI <strong>Devices</strong><br />
n<br />
n<br />
n<br />
PCI is based on a defined bus structure<br />
One or more PCI compliant devices attached to<br />
the PCI bus<br />
l<br />
Each PCI device may contain up to eight PCI functions<br />
– PCI function - a logical device<br />
• For example a sound card, a video card, or an IDE controller<br />
– <strong>Devices</strong> control 1-8 logical functions<br />
<strong>Devices</strong> may be a master or a target<br />
l<br />
l<br />
l<br />
Masters may initiate a bus transaction<br />
– Require a request/grant (REQ#/GNT#) pair wired to an arbiter<br />
for each master on the bus<br />
Targets may not initiate a bus transaction<br />
– Exception is a PCI-X target completing a split transaction<br />
response<br />
<strong>Devices</strong> attach to PCI busses by way of bridges<br />
Copyright by Dashcourses, Inc. 2009<br />
1-29
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