PCIe Devices - PLX Technology
PCIe Devices - PLX Technology PCIe Devices - PLX Technology
PCIe Commands TLP Type Fmt [1:0] Type [4:0] Description MRd 00 and 01 0 0000 Memory Read Request MRdLk 00 and 01 0 0001 Memory Read Request Locked MWr 10 and 11 0 0000 Memory Write Request IORd 00 0 0010 I/O Read Request IOWr CfgRd0 CfgWr0 CfgRd1 CfgWr1 Msg MsgD 10 0 0010 I/O Write Request 00 0 0100 Configuration Read Type 0 10 0 0100 Configuration Write Type 0 00 0 0101 Configuration Read Type 1 10 0 0101 Configuration Write Type 1 01 1 0r 2 r 1 r 0 Message Request, sub-field r[2:0] Specifies the Message routing mechanism 11 1 0r 2 r 1 r 0 Message Request with data payload, sub-field r[2:0] Specifies Message routing mechanism Copyright by Dashcourses, Inc. 2009 1-24
PCIe Command Execution Host System PCIe Device Device Function Configuration R/W Configuration R/W Memory R/W Requestor Completer Memory R/W I/O R/W I/O R/W Messages Messages Root Complex Transaction Layer Transaction Layer Data Link Layer Data Link Layer Physical Layer Physical Layer PCIe Link PCIe Packet PCIe Transaction Copyright by Dashcourses, Inc. 2009 1-25
- Page 1 and 2: Presents PCI Express Overview By Pa
- Page 3 and 4: What This Presentation Is About n T
- Page 5 and 6: Specifications n The current PCIe s
- Page 7 and 8: Presentation Layout Section 1 - PCI
- Page 9 and 10: PCI Specification History n n n PCI
- Page 11 and 12: PCIe Compatibility and New Features
- Page 13 and 14: PCIe Interconnect - Chip-to-Board C
- Page 15 and 16: PCIe Design Possibilities Embedded
- Page 17 and 18: Compatibility with Existing PCI Spe
- Page 19 and 20: New Features n Improved data integr
- Page 21 and 22: Scalable Topologies n Hierarchies u
- Page 23: PCI and PCI-X Architecture and Comm
- Page 27 and 28: PCIe Transactions and Packets n PCI
- Page 29 and 30: PCI Devices n n n PCI is based on a
- Page 31 and 32: PCI Topology with Multiple Host/PCI
- Page 33 and 34: PCIe Device/Function PCIe Single Fu
- Page 35 and 36: PCIe System Fabric PCIe Root Comple
- Page 37 and 38: PCI/PCI-X/PCIe Bridges n Bridges ar
- Page 39 and 40: PCI/PCI-X Arbitration Example n n F
- Page 41 and 42: PCIe Processing and Priorities n PC
- Page 43 and 44: Mythical Example VC ID and Priority
- Page 45 and 46: PCIe Root Complex n A Root Complex
- Page 47 and 48: PCIe Root Complex Model Host system
- Page 49 and 50: PCIe Switch Structure Upstream Port
- Page 51 and 52: PCIe Interrupts Host System Bus Whe
- Page 53 and 54: PCIe Link is a Point-to-Point Conne
- Page 55 and 56: PCIe Differential Drivers n PCIe de
- Page 57 and 58: PCIe Link Attributes (continued) n
- Page 59 and 60: PCIe Can be Aggregated n PCIe devic
- Page 61 and 62: MBps vs. Gbps?? n Comparing data ra
- Page 63 and 64: PCI Configuration Header Types n Fi
- Page 65 and 66: PCI Configuration Header Type 0 PCI
- Page 67 and 68: Host PCI Bridge Discovery n n n Acc
- Page 69 and 70: PCIe Primary/Secondary Bus Scheme P
- Page 71 and 72: Optional Registers (continued) Last
- Page 73 and 74: PCIe Configuration Space DWord 1000
<strong>PCIe</strong> Commands<br />
TLP Type<br />
Fmt<br />
[1:0]<br />
Type<br />
[4:0] Description<br />
MRd<br />
00 and 01<br />
0 0000<br />
Memory Read Request<br />
MRdLk<br />
00 and 01<br />
0 0001<br />
Memory Read Request Locked<br />
MWr<br />
10 and 11<br />
0 0000<br />
Memory Write Request<br />
IORd<br />
00<br />
0 0010<br />
I/O Read Request<br />
IOWr<br />
CfgRd0<br />
CfgWr0<br />
CfgRd1<br />
CfgWr1<br />
Msg<br />
MsgD<br />
10 0 0010 I/O Write Request<br />
00 0 0100 Configuration Read Type 0<br />
10 0 0100 Configuration Write Type 0<br />
00 0 0101 Configuration Read Type 1<br />
10 0 0101 Configuration Write Type 1<br />
01 1 0r 2<br />
r 1<br />
r 0<br />
Message Request, sub-field r[2:0]<br />
Specifies the Message routing mechanism<br />
11 1 0r 2<br />
r 1<br />
r 0<br />
Message Request with data payload, sub-field r[2:0]<br />
Specifies Message routing mechanism<br />
Copyright by Dashcourses, Inc. 2009<br />
1-24
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