PCIe Devices - PLX Technology
PCIe Devices - PLX Technology PCIe Devices - PLX Technology
New Features (continued) n Ability to differentiate services (Quality of Service or QoS) l l l l Configurable arbitration policy within every component End-to-end QoS tag with each packet Support for isochronous traffic Packet prioritization n Hot Plug and Hot Swap Support l l Support for legacy PCI Software model for all form factors Copyright by Dashcourses, Inc. 2009 1-20
Scalable Topologies n Hierarchies using PCI bridge and switch configurations l l PCIe-PCI bridge – Box-to-box connection to legacy PCI based machines – PCIe to PCI or PCI-X bus bridging Network type capability with point-to-point serial connections by way of PCIe switches n Ability to aggregate ‘Lanes’ to increase bandwidth through core hierarchical fabric components l Greater bandwidth by ‘striping’ PCIe Links Copyright by Dashcourses, Inc. 2009 1-21
- Page 1 and 2: Presents PCI Express Overview By Pa
- Page 3 and 4: What This Presentation Is About n T
- Page 5 and 6: Specifications n The current PCIe s
- Page 7 and 8: Presentation Layout Section 1 - PCI
- Page 9 and 10: PCI Specification History n n n PCI
- Page 11 and 12: PCIe Compatibility and New Features
- Page 13 and 14: PCIe Interconnect - Chip-to-Board C
- Page 15 and 16: PCIe Design Possibilities Embedded
- Page 17 and 18: Compatibility with Existing PCI Spe
- Page 19: New Features n Improved data integr
- Page 23 and 24: PCI and PCI-X Architecture and Comm
- Page 25 and 26: PCIe Command Execution Host System
- Page 27 and 28: PCIe Transactions and Packets n PCI
- Page 29 and 30: PCI Devices n n n PCI is based on a
- Page 31 and 32: PCI Topology with Multiple Host/PCI
- Page 33 and 34: PCIe Device/Function PCIe Single Fu
- Page 35 and 36: PCIe System Fabric PCIe Root Comple
- Page 37 and 38: PCI/PCI-X/PCIe Bridges n Bridges ar
- Page 39 and 40: PCI/PCI-X Arbitration Example n n F
- Page 41 and 42: PCIe Processing and Priorities n PC
- Page 43 and 44: Mythical Example VC ID and Priority
- Page 45 and 46: PCIe Root Complex n A Root Complex
- Page 47 and 48: PCIe Root Complex Model Host system
- Page 49 and 50: PCIe Switch Structure Upstream Port
- Page 51 and 52: PCIe Interrupts Host System Bus Whe
- Page 53 and 54: PCIe Link is a Point-to-Point Conne
- Page 55 and 56: PCIe Differential Drivers n PCIe de
- Page 57 and 58: PCIe Link Attributes (continued) n
- Page 59 and 60: PCIe Can be Aggregated n PCIe devic
- Page 61 and 62: MBps vs. Gbps?? n Comparing data ra
- Page 63 and 64: PCI Configuration Header Types n Fi
- Page 65 and 66: PCI Configuration Header Type 0 PCI
- Page 67 and 68: Host PCI Bridge Discovery n n n Acc
- Page 69 and 70: PCIe Primary/Secondary Bus Scheme P
New Features (continued)<br />
n<br />
Ability to differentiate services (Quality of<br />
Service or QoS)<br />
l<br />
l<br />
l<br />
l<br />
Configurable arbitration policy within every component<br />
End-to-end QoS tag with each packet<br />
Support for isochronous traffic<br />
Packet prioritization<br />
n<br />
Hot Plug and Hot Swap Support<br />
l<br />
l<br />
Support for legacy PCI<br />
Software model for all form factors<br />
Copyright by Dashcourses, Inc. 2009<br />
1-20
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