PCIe Devices - PLX Technology

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Low Latency and High Bandwidth n n n Low-overhead l Maximize application payload bandwidth, and link efficiency – Application and/or local OS determines required mix Low-latency communications l Maximum allowable delay or processing time through link devices within the fabric – Can calculate (deterministic) delay on end-to-end basis within the fabric High speed serial interconnect l l l 2.5 and 5.0 Gbps wire speed – called GT/s or giga transfers per second – Can be aggregated Low pin count per device and connector interface Longer connection runs – Traces on PCBs or cables external Copyright by Dashcourses, Inc. 2009 1-18
New Features n Improved data integrity l l Link-level data integrity for all types of transactions and packets – Sequence Number and Link CRC (LCRC) within data link layer header provided End-to-end CRC (ECRC) data integrity for high availability solutions n Error handling l l Legacy PCI-level error handling Advanced error reporting and handling for improved fault isolation and recovery Copyright by Dashcourses, Inc. 2009 1-19
Page 1 and 2: Presents PCI Express Overview By Pa
Page 3 and 4: What This Presentation Is About n T
Page 5 and 6: Specifications n The current PCIe s
Page 7 and 8: Presentation Layout Section 1 - PCI
Page 9 and 10: PCI Specification History n n n PCI
Page 11 and 12: PCIe Compatibility and New Features
Page 13 and 14: PCIe Interconnect - Chip-to-Board C
Page 15 and 16: PCIe Design Possibilities Embedded
Page 17: Compatibility with Existing PCI Spe
Page 21 and 22: Scalable Topologies n Hierarchies u
Page 23 and 24: PCI and PCI-X Architecture and Comm
Page 25 and 26: PCIe Command Execution Host System
Page 27 and 28: PCIe Transactions and Packets n PCI
Page 29 and 30: PCI Devices n n n PCI is based on a
Page 31 and 32: PCI Topology with Multiple Host/PCI
Page 33 and 34: PCIe Device/Function PCIe Single Fu
Page 35 and 36: PCIe System Fabric PCIe Root Comple
Page 37 and 38: PCI/PCI-X/PCIe Bridges n Bridges ar
Page 39 and 40: PCI/PCI-X Arbitration Example n n F
Page 41 and 42: PCIe Processing and Priorities n PC
Page 43 and 44: Mythical Example VC ID and Priority
Page 45 and 46: PCIe Root Complex n A Root Complex
Page 47 and 48: PCIe Root Complex Model Host system
Page 49 and 50: PCIe Switch Structure Upstream Port
Page 51 and 52: PCIe Interrupts Host System Bus Whe
Page 53 and 54: PCIe Link is a Point-to-Point Conne
Page 55 and 56: PCIe Differential Drivers n PCIe de
Page 57 and 58: PCIe Link Attributes (continued) n
Page 59 and 60: PCIe Can be Aggregated n PCIe devic
Page 61 and 62: MBps vs. Gbps?? n Comparing data ra
Page 63 and 64: PCI Configuration Header Types n Fi
Page 65 and 66: PCI Configuration Header Type 0 PCI
Page 67 and 68: Host PCI Bridge Discovery n n n Acc
Page 69 and 70:
PCIe Primary/Secondary Bus Scheme P
Page 71 and 72:
Optional Registers (continued) Last
Page 73 and 74:
PCIe Configuration Space DWord 1000
Page 75 and 76:
Key Aspects of Transaction Layer n
Page 77 and 78:
PCIe Transactions n Software will t
Page 79 and 80:
Address Space and Transaction Type
Page 81 and 82:
TLP size Varies n TLP construction
Page 83 and 84:
PCIe Transaction Movement Host Syst
Page 85 and 86:
TLP Packet Components n TLP packets
Page 87 and 88:
TLP Receiver Processing n Received
Page 89 and 90:
Message Codes n Messages are define
Page 91 and 92:
Section 3 PCIe Data Link Layer Copy
Page 93 and 94:
Key Aspects of Data Link Layer n At
Page 95 and 96:
Data Link Layer Created Packets - T
Page 97 and 98:
Data Link Layer Received Packets Pa
Page 99 and 100:
Data Link Layer Handling of TLPs n
Page 101 and 102:
Link Initialization and Flow Contro
Page 103 and 104:
Initialization n Example TS1/TS2 l
Page 105 and 106:
Flow Control n Example credit excha
Page 107 and 108:
Basic DLLP Header Fields n All Data
Page 109 and 110:
Transaction Layer Buffer Space and
Page 111 and 112:
PCIe Power Management Overview n PC
Page 113 and 114:
Link Training and Status State Mach
Page 115 and 116:
Normal Operations n Once the Link i
Page 117 and 118:
Sequence Number - Transmit Requesto
Page 119 and 120:
Section 4 PCIe Physical Layer Copyr
Page 121 and 122:
Physical Layer Overview n The PCIe
Page 123 and 124:
Physical Layer Packets Packet deliv
Page 125 and 126:
Scrambling n Scrambling is a techni
Page 127 and 128:
8B/10B Signal Encoding Data Byte Na
Page 129 and 130:
Special Symbols n Framing and Link
Page 131 and 132:
Other Ordered Sets n n Electrical I
Page 133 and 134:
Link Training Ordered Sets n Using
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