PCIe Devices - PLX Technology
PCIe Devices - PLX Technology PCIe Devices - PLX Technology
Low Latency and High Bandwidth n n n Low-overhead l Maximize application payload bandwidth, and link efficiency – Application and/or local OS determines required mix Low-latency communications l Maximum allowable delay or processing time through link devices within the fabric – Can calculate (deterministic) delay on end-to-end basis within the fabric High speed serial interconnect l l l 2.5 and 5.0 Gbps wire speed – called GT/s or giga transfers per second – Can be aggregated Low pin count per device and connector interface Longer connection runs – Traces on PCBs or cables external Copyright by Dashcourses, Inc. 2009 1-18
New Features n Improved data integrity l l Link-level data integrity for all types of transactions and packets – Sequence Number and Link CRC (LCRC) within data link layer header provided End-to-end CRC (ECRC) data integrity for high availability solutions n Error handling l l Legacy PCI-level error handling Advanced error reporting and handling for improved fault isolation and recovery Copyright by Dashcourses, Inc. 2009 1-19
- Page 1 and 2: Presents PCI Express Overview By Pa
- Page 3 and 4: What This Presentation Is About n T
- Page 5 and 6: Specifications n The current PCIe s
- Page 7 and 8: Presentation Layout Section 1 - PCI
- Page 9 and 10: PCI Specification History n n n PCI
- Page 11 and 12: PCIe Compatibility and New Features
- Page 13 and 14: PCIe Interconnect - Chip-to-Board C
- Page 15 and 16: PCIe Design Possibilities Embedded
- Page 17: Compatibility with Existing PCI Spe
- Page 21 and 22: Scalable Topologies n Hierarchies u
- Page 23 and 24: PCI and PCI-X Architecture and Comm
- Page 25 and 26: PCIe Command Execution Host System
- Page 27 and 28: PCIe Transactions and Packets n PCI
- Page 29 and 30: PCI Devices n n n PCI is based on a
- Page 31 and 32: PCI Topology with Multiple Host/PCI
- Page 33 and 34: PCIe Device/Function PCIe Single Fu
- Page 35 and 36: PCIe System Fabric PCIe Root Comple
- Page 37 and 38: PCI/PCI-X/PCIe Bridges n Bridges ar
- Page 39 and 40: PCI/PCI-X Arbitration Example n n F
- Page 41 and 42: PCIe Processing and Priorities n PC
- Page 43 and 44: Mythical Example VC ID and Priority
- Page 45 and 46: PCIe Root Complex n A Root Complex
- Page 47 and 48: PCIe Root Complex Model Host system
- Page 49 and 50: PCIe Switch Structure Upstream Port
- Page 51 and 52: PCIe Interrupts Host System Bus Whe
- Page 53 and 54: PCIe Link is a Point-to-Point Conne
- Page 55 and 56: PCIe Differential Drivers n PCIe de
- Page 57 and 58: PCIe Link Attributes (continued) n
- Page 59 and 60: PCIe Can be Aggregated n PCIe devic
- Page 61 and 62: MBps vs. Gbps?? n Comparing data ra
- Page 63 and 64: PCI Configuration Header Types n Fi
- Page 65 and 66: PCI Configuration Header Type 0 PCI
- Page 67 and 68: Host PCI Bridge Discovery n n n Acc
Low Latency and High Bandwidth<br />
n<br />
n<br />
n<br />
Low-overhead<br />
l<br />
Maximize application payload bandwidth, and link efficiency<br />
– Application and/or local OS determines required mix<br />
Low-latency communications<br />
l<br />
Maximum allowable delay or processing time through link<br />
devices within the fabric<br />
– Can calculate (deterministic) delay on end-to-end basis within<br />
the fabric<br />
High speed serial interconnect<br />
l<br />
l<br />
l<br />
2.5 and 5.0 Gbps wire speed – called GT/s or giga transfers<br />
per second<br />
– Can be aggregated<br />
Low pin count per device and connector interface<br />
Longer connection runs<br />
– Traces on PCBs or cables external<br />
Copyright by Dashcourses, Inc. 2009<br />
1-18
Change language