PCIe Devices - PLX Technology
PCIe Devices - PLX Technology PCIe Devices - PLX Technology
PCIe Protocol Stack Logical Layering Application and System Software Application and System Software Transaction Layer Transaction Layer Data Link Layer Physical Layer Logical Sub-block PCIe Specification Data Link Layer Physical Layer Logical Sub-block Physical Sub-block Physical Sub-block TX RX Packet TX RX Packet Copyright by Dashcourses, Inc. 2009 1-16
Compatibility with Existing PCI Specification n n Ability to enumerate and configure PCIe hardware using PCI system configuration software (OS) with no modifications l l l PCI devices (across a PCIe-PCI bridge) must be accessible by existing OSs and device drivers PCIe add-in card must be accessible to existing OSs and capable of being configured Compatibility includes – Boot over existing OS – Support existing I/O device drivers (at binary level) – Support existing applications New software required to configure/enable new PCIe functionality by adopting the PCI configuration paradigm Copyright by Dashcourses, Inc. 2009 1-17
- Page 1 and 2: Presents PCI Express Overview By Pa
- Page 3 and 4: What This Presentation Is About n T
- Page 5 and 6: Specifications n The current PCIe s
- Page 7 and 8: Presentation Layout Section 1 - PCI
- Page 9 and 10: PCI Specification History n n n PCI
- Page 11 and 12: PCIe Compatibility and New Features
- Page 13 and 14: PCIe Interconnect - Chip-to-Board C
- Page 15: PCIe Design Possibilities Embedded
- Page 19 and 20: New Features n Improved data integr
- Page 21 and 22: Scalable Topologies n Hierarchies u
- Page 23 and 24: PCI and PCI-X Architecture and Comm
- Page 25 and 26: PCIe Command Execution Host System
- Page 27 and 28: PCIe Transactions and Packets n PCI
- Page 29 and 30: PCI Devices n n n PCI is based on a
- Page 31 and 32: PCI Topology with Multiple Host/PCI
- Page 33 and 34: PCIe Device/Function PCIe Single Fu
- Page 35 and 36: PCIe System Fabric PCIe Root Comple
- Page 37 and 38: PCI/PCI-X/PCIe Bridges n Bridges ar
- Page 39 and 40: PCI/PCI-X Arbitration Example n n F
- Page 41 and 42: PCIe Processing and Priorities n PC
- Page 43 and 44: Mythical Example VC ID and Priority
- Page 45 and 46: PCIe Root Complex n A Root Complex
- Page 47 and 48: PCIe Root Complex Model Host system
- Page 49 and 50: PCIe Switch Structure Upstream Port
- Page 51 and 52: PCIe Interrupts Host System Bus Whe
- Page 53 and 54: PCIe Link is a Point-to-Point Conne
- Page 55 and 56: PCIe Differential Drivers n PCIe de
- Page 57 and 58: PCIe Link Attributes (continued) n
- Page 59 and 60: PCIe Can be Aggregated n PCIe devic
- Page 61 and 62: MBps vs. Gbps?? n Comparing data ra
- Page 63 and 64: PCI Configuration Header Types n Fi
- Page 65 and 66: PCI Configuration Header Type 0 PCI
<strong>PCIe</strong> Protocol Stack Logical Layering<br />
Application and<br />
System Software<br />
Application and<br />
System Software<br />
Transaction Layer<br />
Transaction Layer<br />
Data Link Layer<br />
Physical Layer<br />
Logical Sub-block<br />
<strong>PCIe</strong><br />
Specification<br />
Data Link Layer<br />
Physical Layer<br />
Logical Sub-block<br />
Physical Sub-block<br />
Physical Sub-block<br />
TX<br />
RX<br />
Packet<br />
TX<br />
RX<br />
Packet<br />
Copyright by Dashcourses, Inc. 2009<br />
1-16
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