PCIe Devices - PLX Technology

More documents

Recommendations

Info

Link Initialization n Link Initialization consists of the following l Configuring – Discovering and determining Link width, data rate, lane reversal, and polarity inversion – Restarting a port from low power states l Link training – Data rate negotiation – Bit lock, symbol lock, and lane priority on a per lane basis – Link width negotiation n Receivers may optionally check for violations of the Link Initialization and Training protocols l If enabled to do so and a training error occurs it is reported as a Training error with the associated port – A Training error is considered to be fatal to the Link Copyright by Dashcourses, Inc. 2009 4-132
Link Training Ordered Sets n Using training ordered sets TS1 and TS2, each end of the link determines the following l Bit lock – frequent 1 0 transitions allow receiver to ‘bit lock’ onto the transmitters clock – Link signaling rate • 2.5 Gbps current support (enhancements planed) l Symbol lock – Uses COMM symbol as the start of TS1 and TS2 training sets • Establishes symbol boundary sensing at receiver l Lane-to-Lane de-skew – Receiver adding/removing fixed latency on each lane of a link to align serial bit stream of the packet across the link • Compensates for trace and impedance mismatches due to routing, board materials, and within transceivers Copyright by Dashcourses, Inc. 2009 4-133
Page 1 and 2:
Presents PCI Express Overview By Pa
Page 3 and 4:
What This Presentation Is About n T
Page 5 and 6:
Specifications n The current PCIe s
Page 7 and 8:
Presentation Layout Section 1 - PCI
Page 9 and 10:
PCI Specification History n n n PCI
Page 11 and 12:
PCIe Compatibility and New Features
Page 13 and 14:
PCIe Interconnect - Chip-to-Board C
Page 15 and 16:
PCIe Design Possibilities Embedded
Page 17 and 18:
Compatibility with Existing PCI Spe
Page 19 and 20:
New Features n Improved data integr
Page 21 and 22:
Scalable Topologies n Hierarchies u
Page 23 and 24:
PCI and PCI-X Architecture and Comm
Page 25 and 26:
PCIe Command Execution Host System
Page 27 and 28:
PCIe Transactions and Packets n PCI
Page 29 and 30:
PCI Devices n n n PCI is based on a
Page 31 and 32:
PCI Topology with Multiple Host/PCI
Page 33 and 34:
PCIe Device/Function PCIe Single Fu
Page 35 and 36:
PCIe System Fabric PCIe Root Comple
Page 37 and 38:
PCI/PCI-X/PCIe Bridges n Bridges ar
Page 39 and 40:
PCI/PCI-X Arbitration Example n n F
Page 41 and 42:
PCIe Processing and Priorities n PC
Page 43 and 44:
Mythical Example VC ID and Priority
Page 45 and 46:
PCIe Root Complex n A Root Complex
Page 47 and 48:
PCIe Root Complex Model Host system
Page 49 and 50:
PCIe Switch Structure Upstream Port
Page 51 and 52:
PCIe Interrupts Host System Bus Whe
Page 53 and 54:
PCIe Link is a Point-to-Point Conne
Page 55 and 56:
PCIe Differential Drivers n PCIe de
Page 57 and 58:
PCIe Link Attributes (continued) n
Page 59 and 60:
PCIe Can be Aggregated n PCIe devic
Page 61 and 62:
MBps vs. Gbps?? n Comparing data ra
Page 63 and 64:
PCI Configuration Header Types n Fi
Page 65 and 66:
PCI Configuration Header Type 0 PCI
Page 67 and 68:
Host PCI Bridge Discovery n n n Acc
Page 69 and 70:
PCIe Primary/Secondary Bus Scheme P
Page 71 and 72:
Optional Registers (continued) Last
Page 73 and 74:
PCIe Configuration Space DWord 1000
Page 75 and 76:
Key Aspects of Transaction Layer n
Page 77 and 78:
PCIe Transactions n Software will t
Page 79 and 80:
Address Space and Transaction Type
Page 81 and 82: TLP size Varies n TLP construction
Page 83 and 84: PCIe Transaction Movement Host Syst
Page 85 and 86: TLP Packet Components n TLP packets
Page 87 and 88: TLP Receiver Processing n Received
Page 89 and 90: Message Codes n Messages are define
Page 91 and 92: Section 3 PCIe Data Link Layer Copy
Page 93 and 94: Key Aspects of Data Link Layer n At
Page 95 and 96: Data Link Layer Created Packets - T
Page 97 and 98: Data Link Layer Received Packets Pa
Page 99 and 100: Data Link Layer Handling of TLPs n
Page 101 and 102: Link Initialization and Flow Contro
Page 103 and 104: Initialization n Example TS1/TS2 l
Page 105 and 106: Flow Control n Example credit excha
Page 107 and 108: Basic DLLP Header Fields n All Data
Page 109 and 110: Transaction Layer Buffer Space and
Page 111 and 112: PCIe Power Management Overview n PC
Page 113 and 114: Link Training and Status State Mach
Page 115 and 116: Normal Operations n Once the Link i
Page 117 and 118: Sequence Number - Transmit Requesto
Page 119 and 120: Section 4 PCIe Physical Layer Copyr
Page 121 and 122: Physical Layer Overview n The PCIe
Page 123 and 124: Physical Layer Packets Packet deliv
Page 125 and 126: Scrambling n Scrambling is a techni
Page 127 and 128: 8B/10B Signal Encoding Data Byte Na
Page 129 and 130: Special Symbols n Framing and Link
Page 131: Other Ordered Sets n n Electrical I
show all

PCIe Devices - PLX Technology

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?