PCIe Devices - PLX Technology
PCIe Devices - PLX Technology
PCIe Devices - PLX Technology
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Link Initialization<br />
n<br />
Link Initialization consists of the following<br />
l Configuring<br />
– Discovering and determining Link width, data rate, lane<br />
reversal, and polarity inversion<br />
– Restarting a port from low power states<br />
l Link training<br />
– Data rate negotiation<br />
– Bit lock, symbol lock, and lane priority on a per lane<br />
basis<br />
– Link width negotiation<br />
n<br />
Receivers may optionally check for violations of the Link<br />
Initialization and Training protocols<br />
l If enabled to do so and a training error occurs it is reported as a<br />
Training error with the associated port<br />
– A Training error is considered to be fatal to the Link<br />
Copyright by Dashcourses, Inc. 2009<br />
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