PCIe Devices - PLX Technology

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Logical Sub-Block Services n The Physical Layer Logical sub-block performs the following l Symbol encoding/decoding – Per ANSI X3.230-1994, clause 11, and IEEE 802.3z, 36.2.4 • Encoding allows for 12 special symbols used for framing and Link management • Used for Link Transmitting – Adding framing symbols to symbol encoded packet, feeding packet byte stream to the appropriate Physical Layer Lane • Used for Receiving – Receiving serial byte stream from device’s receive port, stripping framing symbols, decoding received packet, and passing packet to the Data Link Layer l Link initialization, training, and status state rules l Link error recovery Copyright by Dashcourses, Inc. 2009 4-126
8B/10B Signal Encoding Data Byte Name Data Byte Value Current Current Bits RD- RD+ HGF EDCBA abcdei fghj abcdei fghj D0.0 00 000 00000 100111 0100 011000 1011 D31.7 FF 111 11111 101011 0001 010100 1110 Byte stream 8 bits 3 bits 5 bits 4 bits 6 bits Symbol stream 10 bits To physical transmitter Copyright by Dashcourses, Inc. 2009 4-127
Page 1 and 2:
Presents PCI Express Overview By Pa
Page 3 and 4:
What This Presentation Is About n T
Page 5 and 6:
Specifications n The current PCIe s
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Presentation Layout Section 1 - PCI
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PCI Specification History n n n PCI
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PCIe Compatibility and New Features
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PCIe Interconnect - Chip-to-Board C
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PCIe Design Possibilities Embedded
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Compatibility with Existing PCI Spe
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New Features n Improved data integr
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Scalable Topologies n Hierarchies u
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PCI and PCI-X Architecture and Comm
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PCIe Command Execution Host System
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PCIe Transactions and Packets n PCI
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PCI Devices n n n PCI is based on a
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PCI Topology with Multiple Host/PCI
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PCIe Device/Function PCIe Single Fu
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PCIe System Fabric PCIe Root Comple
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PCI/PCI-X/PCIe Bridges n Bridges ar
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PCI/PCI-X Arbitration Example n n F
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PCIe Processing and Priorities n PC
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Mythical Example VC ID and Priority
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PCIe Root Complex n A Root Complex
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PCIe Root Complex Model Host system
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PCIe Switch Structure Upstream Port
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PCIe Interrupts Host System Bus Whe
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PCIe Link is a Point-to-Point Conne
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PCIe Differential Drivers n PCIe de
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PCIe Link Attributes (continued) n
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PCIe Can be Aggregated n PCIe devic
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MBps vs. Gbps?? n Comparing data ra
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PCI Configuration Header Types n Fi
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PCI Configuration Header Type 0 PCI
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Host PCI Bridge Discovery n n n Acc
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PCIe Primary/Secondary Bus Scheme P
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Optional Registers (continued) Last
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PCIe Configuration Space DWord 1000
Page 75 and 76: Key Aspects of Transaction Layer n
Page 77 and 78: PCIe Transactions n Software will t
Page 79 and 80: Address Space and Transaction Type
Page 81 and 82: TLP size Varies n TLP construction
Page 83 and 84: PCIe Transaction Movement Host Syst
Page 85 and 86: TLP Packet Components n TLP packets
Page 87 and 88: TLP Receiver Processing n Received
Page 89 and 90: Message Codes n Messages are define
Page 91 and 92: Section 3 PCIe Data Link Layer Copy
Page 93 and 94: Key Aspects of Data Link Layer n At
Page 95 and 96: Data Link Layer Created Packets - T
Page 97 and 98: Data Link Layer Received Packets Pa
Page 99 and 100: Data Link Layer Handling of TLPs n
Page 101 and 102: Link Initialization and Flow Contro
Page 103 and 104: Initialization n Example TS1/TS2 l
Page 105 and 106: Flow Control n Example credit excha
Page 107 and 108: Basic DLLP Header Fields n All Data
Page 109 and 110: Transaction Layer Buffer Space and
Page 111 and 112: PCIe Power Management Overview n PC
Page 113 and 114: Link Training and Status State Mach
Page 115 and 116: Normal Operations n Once the Link i
Page 117 and 118: Sequence Number - Transmit Requesto
Page 119 and 120: Section 4 PCIe Physical Layer Copyr
Page 121 and 122: Physical Layer Overview n The PCIe
Page 123 and 124: Physical Layer Packets Packet deliv
Page 125: Scrambling n Scrambling is a techni
Page 129 and 130: Special Symbols n Framing and Link
Page 131 and 132: Other Ordered Sets n n Electrical I
Page 133 and 134: Link Training Ordered Sets n Using
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PCIe Devices - PLX Technology

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