PCIe Devices - PLX Technology
PCIe Devices - PLX Technology
PCIe Devices - PLX Technology
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Normal Data Link Layer Operation<br />
n<br />
<strong>PCIe</strong> describes Sequence Number generation in<br />
terms of conceptual counters, timers, and flags<br />
l<br />
Actual silicon implementation (registers and field bit<br />
definitions) of these functions will be vendor specific<br />
n<br />
Normal operation involves passing conditioned<br />
TLPs to the Physical Layer and receiving an Ack<br />
or Nak referencing a specific TLP<br />
l<br />
Flow control, buffer sizes, and link utilization will be<br />
determined by use of these counters, timers, and flags<br />
n<br />
Implemented on a link-by-link basis throughout<br />
the fabric<br />
Copyright by Dashcourses, Inc. 2009<br />
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