PCIe Devices - PLX Technology
PCIe Devices - PLX Technology PCIe Devices - PLX Technology
PCIe Link PM State Diagram L0s L0 L2 L1 L2/L3 Ready L3 Copyright by Dashcourses, Inc. 2009 3-110
PCIe Power Management Overview n PCIe PM provides the following services l l l l Mechanism to identify power management capabilities of a given function Ability to transition a function into a certain PM state Notification of the current PM state of a function The option to wakeup the system on a specific event n PCIe PM is compatible with the PCI PM l PCI Bus Power Management Interface Specification Revision 1.1 and the Advanced Configuration and Power Interface (ACPI) Specification revision 2.0 – Legacy PM software will have to be re-written to take advantage of PCIe PM enhanced capabilities • PCIe PM states are not directly visible to legacy bus driver software Copyright by Dashcourses, Inc. 2009 3-111
- Page 59 and 60: PCIe Can be Aggregated n PCIe devic
- Page 61 and 62: MBps vs. Gbps?? n Comparing data ra
- Page 63 and 64: PCI Configuration Header Types n Fi
- Page 65 and 66: PCI Configuration Header Type 0 PCI
- Page 67 and 68: Host PCI Bridge Discovery n n n Acc
- Page 69 and 70: PCIe Primary/Secondary Bus Scheme P
- Page 71 and 72: Optional Registers (continued) Last
- Page 73 and 74: PCIe Configuration Space DWord 1000
- Page 75 and 76: Key Aspects of Transaction Layer n
- Page 77 and 78: PCIe Transactions n Software will t
- Page 79 and 80: Address Space and Transaction Type
- Page 81 and 82: TLP size Varies n TLP construction
- Page 83 and 84: PCIe Transaction Movement Host Syst
- Page 85 and 86: TLP Packet Components n TLP packets
- Page 87 and 88: TLP Receiver Processing n Received
- Page 89 and 90: Message Codes n Messages are define
- Page 91 and 92: Section 3 PCIe Data Link Layer Copy
- Page 93 and 94: Key Aspects of Data Link Layer n At
- Page 95 and 96: Data Link Layer Created Packets - T
- Page 97 and 98: Data Link Layer Received Packets Pa
- Page 99 and 100: Data Link Layer Handling of TLPs n
- Page 101 and 102: Link Initialization and Flow Contro
- Page 103 and 104: Initialization n Example TS1/TS2 l
- Page 105 and 106: Flow Control n Example credit excha
- Page 107 and 108: Basic DLLP Header Fields n All Data
- Page 109: Transaction Layer Buffer Space and
- Page 113 and 114: Link Training and Status State Mach
- Page 115 and 116: Normal Operations n Once the Link i
- Page 117 and 118: Sequence Number - Transmit Requesto
- Page 119 and 120: Section 4 PCIe Physical Layer Copyr
- Page 121 and 122: Physical Layer Overview n The PCIe
- Page 123 and 124: Physical Layer Packets Packet deliv
- Page 125 and 126: Scrambling n Scrambling is a techni
- Page 127 and 128: 8B/10B Signal Encoding Data Byte Na
- Page 129 and 130: Special Symbols n Framing and Link
- Page 131 and 132: Other Ordered Sets n n Electrical I
- Page 133 and 134: Link Training Ordered Sets n Using
<strong>PCIe</strong> Power Management Overview<br />
n<br />
<strong>PCIe</strong> PM provides the following services<br />
l<br />
l<br />
l<br />
l<br />
Mechanism to identify power management capabilities of a<br />
given function<br />
Ability to transition a function into a certain PM state<br />
Notification of the current PM state of a function<br />
The option to wakeup the system on a specific event<br />
n<br />
<strong>PCIe</strong> PM is compatible with the PCI PM<br />
l PCI Bus Power Management Interface Specification Revision<br />
1.1 and the Advanced Configuration and Power Interface (ACPI)<br />
Specification revision 2.0<br />
– Legacy PM software will have to be re-written to<br />
take advantage of <strong>PCIe</strong> PM enhanced capabilities<br />
• <strong>PCIe</strong> PM states are not directly visible to legacy bus driver software<br />
Copyright by Dashcourses, Inc. 2009<br />
3-111
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